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Related Manuals for SBS Technologies P-Octal Series
Summary of Contents for SBS Technologies P-Octal Series
- Page 1 Artisan Technology Group is your source for quality new and certified-used/pre-owned equipment SERVICE CENTER REPAIRS WE BUY USED EQUIPMENT • FAST SHIPPING AND DELIVERY Experienced engineers and technicians on staff Sell your excess, underutilized, and idle used equipment at our full-service, in-house repair center We also offer credit for buy-backs and trade-ins •...
- Page 2 Px-Octal PC•MIP Modules with Eight Serial Channels User Manual © SBS Technologies, Inc. Subject to change without notice. Part No. 89004225 Rev. 3.0 20050114 Hardware Revision: P1: B P2: B Artisan Technology Group - Quality Instrumentation ... Guaranteed | (888) 88-SOURCE | www.artisantg.com...
- Page 3 PC•MIP Modules with Technologies, Inc. QuickPack, SDpacK and Unilin Eight Serial Channels are trademarks of SBS Technologies, Inc. PC•MIP is a trademark of SBS Technologies, Inc. and MEN Micro Inc. SBS Technologies, Inc. 1284 Corporate Center Drive SBS Technologies, Inc. acknowledges the St.
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Page 4: Table Of Contents
Table of Contents PRODUCT DESCRIPTION________________________________________________ 1 BLOCK DIAGRAMS_____________________________________________________ 2 QUICK START _________________________________________________________ 5 UART R _________________________________________________________ 5 ESET ____________________________________________ 6 HANNEL ONFIGURATION ____________________________________________ 6 HANNEL ONFIGURATION ___________________________________________ 6 RANSMITTING AND EADING CHANNEL NUMBERING _________________________________________________ 7 PCI CONFIGURATION REGISTERS ________________________________________ 8 MEMORY SPACE______________________________________________________ 10 ______________________________________ 11 LTERA... - Page 5 List of Figures 1. B 232 ___________________________________ 2 IGURE LOCK IAGRAM ERSION 2. B 422 ___________________________________ 3 IGURE LOCK IAGRAM ERSION 3. B - TTL V ___________________________________ 4 IGURE LOCK IAGRAM ERSION 4. Q - 232 IGURE UICK TART ONNECTIONS TO RANSMIT HARACTERS _____________________________________________________________ 5...
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Page 6: Product Description
Product Description The Px-Octal product family provides eight channels of EIA-232, EIA-422, or TTL-compatible (3.3V) asynchronous serial communication on a Type I (flexible I/O) or Type II (front panel I/O) PC•MIP module. The high channel density makes the Px-Octal module ideal for communications applications that require a large number of serial channels in a small space. -
Page 7: Block Diagrams
Block Diagrams RS232 TRANSCEIVERS PCI BUS ALTERA EPF6016 QUAD CONTROL UART LOGIC TARGET DATA MEGA CORE CHAN 1 ADDRESS CONTROL CLOCK CONTROL REGISTER QUAD FIFO READY UART REGISTER DATA GLOBAL INTERUPT ADDRESS VECTOR CHAN 8 CONTROL CLOCK 7.3728 OPTIONAL CUSTOM CLOCK CLOCK Figure 1. -
Page 8: Figure 2. Block Diagram
RS422 PCI BUS CHAN 1 TRANCEIVERS ALTERA EPF6016 QUAD CONTROL UART LOGIC TARGET DATA MEGA CORE ADDRESS CONTROL Switchable Termination Resistors CLOCK CONTROL REGISTER QUAD FIFO READY CHAN 8 UART REGISTER DATA GLOBAL INTERUPT ADDRESS STATUS CONTROL Switchable CLOCK Termination Resistors 7.3728 OPTIONAL... -
Page 9: Figure 3. Block Diagram - Ttl
DIRECT TTL PCI BUS ALTERA EPF6016 CONNECTION QUAD CONTROL UART LOGIC TARGET DATA MEGA CORE CHAN 1 ADDRESS CONTROL CLOCK CONTROL REGISTER QUAD FIFO READY UART REGISTER DATA GLOBAL INTERUPT ADDRESS VECTOR CHAN 8 CONTROL CLOCK 7.3728 OPTIONAL CUSTOM CLOCK CLOCK Figure 3. -
Page 10: Quick Start
Quick Start Each channel is implemented by a unique set of UART registers but also shares the global control, FIFO ready, and interrupt status registers implemented in the Altera device. This section illustrates how to: 1. Configure Channel 1 and Channel 8 for 9600 baud rate, 8 data bits, 1 stop bit, and no parity 2. -
Page 11: Channel 1 Configuration
Channel 1 Configuration 1. Write 0x80 to offset 0x0030 (Enables access to Special Register.) 2. Write 0x0C to offset 0x0000 Write 0x00 to offset 0x0010 (Sets baud rate to 9600.) 3. Write 0x03 to offset 0x0030 (Exits Special Register mode and sets 8 data bits, 1 stop bit, no parity.) 4. -
Page 12: Channel Numbering
Channel Numbering The Px-Octal uses two quad UARTs (UART 0 and UART 1). Please refer to the Exar ST16C854 Data Sheet for a complete definition of all the UART registers. UART channels are labeled as follows: Channel Number UART Number UART Channel Figure 7. -
Page 13: Pci Configuration Registers
PCI Configuration Registers PCI Configuration Registers can be accessed only through PCI Configuration Read and Configuration Write cycles. Px-Octal PCI configuration space follows PCI Local Bus Specification, Revision 2.1, which defines sixteen 32-bit words of block configuration space. The registers within this range identify the device, control PCI bus functions, and indicate PCI bus status. -
Page 14: Figure 9. Read -Only Pci C
The following table specifies read-only PCI Configuration register values. For a detailed description of these registers, please refer to PCI Local Bus Specification, Revision 2.1. Register Value Vendor ID 0x124b Device ID 0x0001 Revision ID 0x0001 Class Code 0x0007 Header Type 0x0000 Subsystem Vendor ID 0x124b... -
Page 15: Memory Space
Memory Space The host system accesses the Px-Octal via a 33 MHz, 32-bit PC•MIP interface that is PCI Specification 2.1 compliant. The board contains two sets of registers. One set is implemented in the Altera device and consists of the Control Register (CR), FIFO Ready Registers (FRR), and the Global Interrupt Status Register (GISR). -
Page 16: Altera-Implemented Registers
Altera-Implemented Registers Registers implemented in the Altera device consist of the Control Register (CR), FIFO Ready Registers (FRR), and the Global Interrupt Status Register (GISR). CR Control Register OSC1_PRSNT UART_RESET OSCSEL INTENABLE CLKSEL_1 CLKSEL_0 Read UART_RESET OSCSEL INTENABLE CLKSEL_1 CLKSEL_0 Write OSC1_PRSNT Reset... -
Page 17: Frr14 Fifo Ready Channels 1-4
FRR14 FIFO Ready Channels 1-4 C4_RXRDY C3_RXRDY C2_RXRDY C1_RXRDY C4_TXRDY C3_TXRDY C2_TXRDY C1_TXRDY Read Write Reset FIFO Ready Channels 1-4 reflect the status of Transmit FIFO Channels 1-4 and Receive FIFO Channels 1-4. C4_RXRDY Channel 4 RXRDY This bit reflects status of the RXRDY pin on Channel 4 of the UART, which in turn indicates status of the Channel 4 Receive FIFO. - Page 18 This bit reflects status of the TXRDY pin on Channel 1 of the UART, which in turn indicates status of the Channel 1 Transmit FIFO. A one indicates that the Transmit FIFO trigger level has been reached. A zero indicates that the Transmit FIFO is below the trigger level.
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Page 19: Frr58 Fifo Ready Channels 5-8
FRR58 FIFO Ready Channels 5-8 C8_RXRDY C7_RXRDY C6_RXRDY C5_RXRDY C8_TXRDY C7_TXRDY C6_TXRDY C5_TXRDY Read Write Reset FIFO Ready Channels 5-8 reflect the status of Transmit FIFO Channels 5-8 and Receive FIFO Channels 5-8. C8_RXRDY Channel 8 RXRDY This bit reflects status of the RXRDY pin on Channel 8 of the UART, which in turn indicates status of the Channel 8 Receive FIFO. - Page 20 This bit reflects status of the TXRDY pin on Channel 5 of the UART, which in turn indicates status of the Channel 5 Transmit FIFO. A one indicates that the Transmit FIFO trigger level has been reached. A zero indicates that the Transmit FIFO is below the trigger level.
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Page 21: Gisr Global Interrupt Status Register
GISR Global Interrupt Status Register CH8_IRQ CH7_IRQ CH6_IRQ CH5_IRQ CH4_IRQ CH3_IRQ CH2_IRQ CH1_IRQ Read Write Reset The Global Interrupt Status Register reflects the interrupt status of Channels 1-8. Each bit reflects the interrupt status on its respective channel. A one indicates an active interrupt. -
Page 22: Uart-Implemented Registers
UART-Implemented Registers Each UART channel contains a set of 15 registers accessible at the base address offsets of its channel. For additional information regarding UART registers, please refer to the Exar XR16C854 datasheet. Register Name Register Size Access Type Address Offset 8 bits Read 0x0000... -
Page 23: Interrupts
Interrupts Interrupt Architecture Each of the two UARTs has four interrupt lines, INT A through D. All eight lines are ORed together in the FPGA, gated with the INTENABLE bit in the Control Register, and output to the PCI bus via INTA#. Each of the eight UART interrupt lines may be monitored via a bit in the Global Interrupt Status Register. -
Page 24: User Options
User Options User-Supplied Oscillator A user-supplied oscillator may be installed in the User Oscillator Location (OSC1) in order to provide baud rates not supported by the standard 7.3728 MHz oscillator. The user-supplied oscillator must be a HCMOS/TTL 5.0V D.C. device in a four pin, J- lead, surface mount package and must be less than or equal to 24 MHz with a 10% (or better) duty cycle. -
Page 25: Connector Pin Assignments
Connector Pin Assignments Connector J1 carries part of the PCI bus to the module. Connector J2 carries the rest of the signals. J1 Pin Signal J1 Pin Signal Reserved-r Reserved-r Reserved-r Reserved-r –12V TRST# +12V Ground INTA# INTB# INTC# INTD# PRSNT1# Reserved-q Reserved-q... -
Page 26: Figure 16. Connector J2 Pin
Connector J2 carries part of the PCI bus to the module. Connector J1 carries the rest of the signals. J2 Pin Signal J2 Pin Signal AD[17] AD[16] C/BE[2]# +3.3V Ground FRAME# IRDY# Ground +3.3V TRDY# DEVSEL# Ground Ground STOP# LOCK# +3.3V PERR# SDONE... -
Page 27: Figure 17. The P1-Octal -232 F
I/O on the P1-Octal-232 is via a flexible I/O Connector J3 as shown in the table below. This connector does not exist on P2-Octal-232. Signal numbers reflect pin assignments when the module is plugged into a carrier board and I/O is accessed via a user connector. -
Page 28: Figure 18. The P1-Octal -422 F
I/O on the P1-Octal-422 is via a flexible I/O Connector J3 as shown in the table below. This connector does not exist on P2-Octal-422. Signal numbers reflect pin assignments when the module is plugged into a carrier board and I/O is accessed via a user connector. -
Page 29: Figure 19. The P1-Octal -Ttl F
I/O on the P1-Octal-TTL is via a flexible I/O Connector J3 as shown in the table below. Signal numbers reflect pin assignments when the module is plugged into a carrier board and I/O is accessed via a user connector. J3 Pin Signal J3 Pin Signal... -
Page 30: Figure 20. The P2-Octal -232 F
I/O on the P2-Octal-232 is via front panel connector, J4. This connector does not exist on P1-Octal-232. The connector is a Champ36 female (AMP 787641-1) with mating part (AMP 787131-2). Pin No. Channel Direction Function Figure 20. The P2-Octal-232 Front Panel Connector J4 Pin Assignments Artisan Technology Group - Quality Instrumentation ... -
Page 31: Figure 21. The P2-Octal -422 F
I/O on the P2-Octal-422 is via front panel connector, J4. This connector does not exist on P1-Octal-422. The connector is a Champ36 female (AMP 787641-1) with mating part (AMP 787131-2). Pin No. Channel Direction Signal TxD- TxD+ RxD- RxD+ TxD- TxD+ RxD- RxD+... -
Page 32: P1-Octal-232 Specifications
P1-Octal-232 Specifications Form Factor PC•MIP Type I Single-Wide 8H PC•MIP Interface PC•MIP draft specification (ANSI/VITA-29), Revision 0.9 32-bit, PCI Specification, Revision 2.1 PCI Controller Altera EPF6016 UART Two Exar XR16C854 Physical Interface Texas Instruments SN75C188 and SN75C189 Number of Channels Eight Physical Levels Supported EIA-232... -
Page 33: P1-Octal-422 Specifications
P1-Octal-422 Specifications Form Factor PC•MIP Type I Single-Wide 8H PC•MIP Interface PC•MIP draft specification (ANSI/VITA-29), Revision 0.9 32-bit, PCI Specification, Revision 2.1 PCI Controller Altera EPF6016 UART Two Exar XR16C854 Physical Interface Dallas Semiconductor DS26C31, DS26C32A Number of Channels Eight Physical Levels Supported EIA-422 Maximum Data Rate... -
Page 34: P1-Octal-Ttl Specifications
P1-Octal-TTL Specifications Form Factor PC•MIP Type I Single-Wide 8H PC•MIP Interface PC•MIP draft specification (ANSI/VITA-29), Revision 0.9 32-bit, PCI Specification, Revision 2.1 PCI Controller Altera EPF6016 UART Two Exar XR16C854 Physical Interface TTL-compatible (3.3V) Number of Channels Eight Physical Levels Supported TTL-compatible (3.3V) Maximum Data Rate 115 Kbaud... -
Page 35: P2-Octal-232 Specifications
P2-Octal-232 Specifications Form Factor PC•MIP Type II Single-Wide 8H PC•MIP Interface PC•MIP draft specification (ANSI/VITA-29), Revision 0.9 32-bit, PCI Specification, Revision 2.1 PCI Controller Altera EPF6016 UART Two Exar XR16C854 Physical Interface Texas Instruments SN75C188 and SN75C189 Number of Channels Eight Physical Levels Supported EIA-232... -
Page 36: P2-Octal-422 Specifications
P2-Octal-422 Specifications Form Factor PC•MIP Type I Single-Wide 8H PC•MIP Interface PC•MIP draft specification (ANSI/VITA-29), Revision 0.9 32-bit, PCI Specification, Revision 2.1 PCI Controller Altera EPF6016 UART Two Exar XR16C854 Physical Interface Dallas Semiconductor DS26C31, DS26C32A Number of Channels Eight Physical Levels Supported EIA-422 Maximum Data Rate... -
Page 37: Repair
For service of SBS Technologies products not purchased directly from SBS Technologies, contact your reseller. Products returned to SBS Technologies for repair by other than the original customer will be treated as out-of- warranty. SBS Technologies, Inc. - Page 38 Artisan Technology Group is your source for quality new and certified-used/pre-owned equipment SERVICE CENTER REPAIRS WE BUY USED EQUIPMENT • FAST SHIPPING AND DELIVERY Experienced engineers and technicians on staff Sell your excess, underutilized, and idle used equipment at our full-service, in-house repair center We also offer credit for buy-backs and trade-ins •...