Detailed Circuit Analysis: Ss-800Avs; Synthesizer Pwb - SAC SS-800AVS Manual

2.2 Detailed Circuit Analysis: SS-800AVS
2.2.1 Synthesizer PWB:
Q1 in conjunction with the components of the Synthesizer Programming
PWB and CRI form a voltage controlled Colpits oscillator. Coarse
adjustment of the oscillator frequency is determined by the values
of LI, Cl, C2, C3, and C4 of PWB 129. L1 is adjusted during initial
tuneup to bring the oscillator output to the correct frequency.
As the desired frequency is~approached, the phase-lock circuits of
PWB 128 will capture control of the oscillator tuning by changing
the DC bias voltage to capacitance diode CRI. Within the capture
tuning region, changes to L1 will produce no change in the oscillator
frequency but will cause changes in the CRI bias voltage. If the
oscillator output frequency is less than the switch selected fre-
quency, the bias voltage will be forced to .approximately 9 volts,
or minimum capacitance in diode CRI. If the oscillator output
frequency is higher than the switch selected frequency, the bias
voltage will be approximately 0 volts, or maximum capacitance in
diode CRI. Monitoring the bias voltage thus enables the technician
to rapidly tune the oscillator to the selected frequency. Q2 buffers
and amplifies the output of the Q1 oscillator to drive the RF output
and the phase-lock logic circuits. The output of buffer Q2 is fed
to programmable divider U3 where the oscillator frequency is divided
by a number N equal to twice the number selected on the frequency
programming switches. For example, if 342 KHz were selected on the
programming switches, N would be equal to 684. With the oscillator
operating at 342 KHz, an output pulse would occur from U3 at 342
KHz divided by 684 or 500 HZo The output pulse width from U3 is
equal to the length of one cycle at the operating frequency, or 2.9
microseconds at 342 KHz. The 500 Hz U3 output is compared by a
phase detector in integrated circuit U2 with a reference 500 Hz
signal produced by crystal oscillator and divider Ul. The error
voltage output from phase detector U2, consisting of a DC voltage
with a small 500 Hz ripple, is applied through the low-pass filter
(C6, R8, C5, R9, C4) to the capacitance diode CRI. This completes
the control loop and enables the locking of the LC oscillator to
the crystal reference oscillator. Q3, Q4, and DSI furnish an
indication of a locked state whenever DSl is lit. This is derived
from a lock indication produced in phase-lock detector U2. The
synthesizer output signal is fed from pin 2 on the Synthesizer PWB
to a modified AM Oscillator PWB.
SS-800AVS Southern Avionics
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