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The memory address control logic (P. 11, middle)
decodes the commands from the microprocessor
directing the MAC and CPR counters (P. 12) to
either load data or count up or down. The output
signals from the control circuit (MACRLOD,
MACRUPl, MACRDNl, MACCLOD, MACCUPC,
MACCDNC) are applied to the input pins (4, 5, 11)
of the up/down counters (H21, H22) on page 12.
The H2l counter circuit determines in what row
the cursor is positioned and feeds this data to a
compare circuit to determine whether the cursor is
on the same row as it was when loaded. The H22
circuit feeds character position holding counters,
which keep track of where the cursor is now and
where it was first loaded. When the (MACR=CPRR)
compare is made, the program terminates the
transmission.
Monitor Drive Logic (Schematic P. 19)
The monitor driver circuit provides horizontal and
vertical deflection signals to the CRT. The char-
acter position counter (CPC) clocks the 112 flip-flop
and provides position information on terminal 14,
pin 8 to the monitor. At column 80, a CPC pulse
is gated to the character line counter.
When
CHC= 9 and CLC= 23, the vertical drive circuit
counter is enabled.
Vertical drive (V DRIVE)
information is output to the monitor from 14,
pin 9.
Blink and Blank Fields (Schematic P. 6, 7)
The video logic contains circuitry to produce a
blinking field of data. The blink clock (produced
by a one-shot counter) is gated with bit 6 of the
character generator word (bit 6=true) to the indi-
cator video multiplexer to produce a field blinking
rate of four images per second. The blink clock is
also applied as input pulses to a selection circuit
(P. 6) for determining blink/blank.
The blank field operation is used for security pur-
poses. The operator may designate particular fields
in the character memory (RAM) to be non-display
fields.
The video indicator multiplexer decodes
inputs to the character generator to determine if
the blank field status should be set. The blank bit
is applied to the same selection circuit as the blink
bit for determining its condition before it is input
to the video shift register.
4-19
Flip-flop K4 (P. 6) sets the save blink field
(SAVBLKFLD) and save blank field (SAVSUPFLD).
Flip-flop K5 (P. 6) sets the set blink field (BLK
FLD) and set blank (suppress) field (SUPFLD)
status.
4.1.8 Data Memory Address Logic (Schematic P. 3)
The memory address register (MACe and MACR
on P. 12) is used to keep track of read and write
memory data locations. The register outputs are
sent to the data memory address logic (2: 1 data
selectors). The memory address register output sig-
nals (MACCl-7 and MACRl-5) are paired with
character line and position counter signals to gen-
erate line and position coordinates for the display
data.
These coordinates are fed to another data
selector circuit, which generates the proper RAM
address.
4.1.9 Protect Mode Logic (Schematic P. 19)
The protect mode status bit is used as a global
condition by the program to disable the over-
writing of any characters in the RAM for which the
write protect bit (bit 8) is set.
Flip-flop B13 is set, identifying the protect mode,
when the input gate (C 13) decodes the set protect
mode command from the microprogram. The out-
put signal (PROTMODE) is input to the operational
mode multiplexer, which transmits the protect
mode condition on the COND B output to the
con trol logic. All data subsequently written into
the RAM is checked to determine if bit 8 (write
protect bit) is set.
With protect mode initiated, all characters with
their write protect bit set are protected against
overwriting. Multiplexer input gate (C 14) detects
protected characters upon input to the multiplexer.
Output (COND B) informs the control logic that a
character is protected.
4.1.10 Program Counter Logic (Schematic P. 8)
The program counter performs the same function
in the ADM-2 as in any other system. The counter
addresses command memory locations (ROM ad-
dresses) in sequential order, unless ajump condition
exists; then it accesses the specified location set
forth in the program. The counter is controlled
by program counter control logic and by the condi-
tion input logic.
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