Write Processing - Wiznet WIZ610io User Manual

wizchip_cs_deselect();//CS=1, SPI end

3.3 Write processing

In the VDM, CSn(High-to-Low) by HOST informs the start of SPI frame and CSn(Low to High) by
HOST informs the end of SPI Frame to W6100.
In the control phase, RW is "1" to indicate write access and OM[1:0] is "00" to indicate VDM.
The data bits transmitted through MOSI are synchronized to the SCLK (Falling-Edge).
If more than one byte of data is transmitted continuously, it supports sequential data write.
uint8_t tAD[3];
// Address
tAD[0] = (uint8_t)((AddrSel & 0x00FF0000) >> 16);
tAD[1] = (uint8_t)((AddrSel & 0x0000FF00) >> 8);
tAD[2] = (uint8_t)(AddrSel & 0x000000ff);
wizchip_cs_select();
tAD[2] |= (_W6100_SPI_WRITE_ | _W6100_SPI_OP_);
WIZ610io User Manual (WIZnet Co.,Ltd.)
< Write Sequence >
//send buffer
//CS=0, SPI start
// Control Byte
9