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4I24M PARALLEL PORT MANUAL
Version 1.0
Copyright 1997 by MESA ELECTRONICS Richmond, CA. Printed in the United States of America.
All rights reserved. This document and the data disclosed herein is not to be reproduced, used,
disclosed in whole or in part to anyone without the written permission of MESA ELECTRONICS.
Mesa Electronics
4175 Lakeside Drive, Suite #100
Richmond, CA 94806-1950
Tel (510) 223-9272 - Fax (510) 223-9585
E-Mail: tech@mesanet.com
- Website: www.mesanet.com
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Table of Contents
Summary of Contents for MESA Electronic 4I24M Series
- Page 1 4I24M PARALLEL PORT MANUAL Version 1.0 Copyright 1997 by MESA ELECTRONICS Richmond, CA. Printed in the United States of America. All rights reserved. This document and the data disclosed herein is not to be reproduced, used, disclosed in whole or in part to anyone without the written permission of MESA ELECTRONICS. Mesa Electronics 4175 Lakeside Drive, Suite #100 Richmond, CA 94806-1950...
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Page 2: Table Of Contents
4I24M USER'S MANUAL TABLE OF CONTENTS HANDLING PRECAUTIONS Static electricity ............... . INTRODUCTION General . -
Page 3: Handling Precautions
4I24M USER'S MANUAL HANDLING PRECAUTIONS STATIC ELECTRICITY The CMOS integrated circuits on the 4I24M can be damaged by exposure to electrostatic discharges. The following precautions should be taken when handling the 4I24M to prevent possible damage. A. Leave the 4I24M in its antistatic bag until needed. B. -
Page 4: Introduction
4I24M USER'S MANUAL INTRODUCTION GENERAL The MESA 4I24 series of cards are 96 bit parallel I/O interfaces implemented on the PC/104 bus. The 4I24 uses 4 (4I24, 4I24I) or 3 (4I24M) socketed 82C55 PIO chips to give for a total of 96 I/O bits (4I24, 4I24I) or 72 I/O bits (4I24M). -
Page 5: Configuration
4I24M USER'S MANUAL CONFIGURATION GENERAL The 4I24M port address and I/O power connection options are set with jumpers. Each group of jumpers will be discussed separately by function. In the following discussions, when the words "up", "down", "right", and "left" are used it is assumed that the 4I24M I/O card is oriented with its bus connectors J1 and J2 at the bottom edge of the card (nearest the person doing the configuration). - Page 6 4I24M USER'S MANUAL CONFIGURATION DEFAULT JUMPER SETTINGS Page 6...
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Page 7: Base Address Selection
4I24M USER'S MANUAL CONFIGURATION BASE ADDRESS SELECTION The I/O addresses of the three 82C55's on the 4I24M are selected by placing shorting jumpers on jumper blocks W6 through W11. Jumper blocks W6 through W11 have three pins and two valid shorting jumper locations, up, and down. - Page 8 4I24M USER'S MANUAL CONFIGURATION BASE AND ALIASED ADDRESS JUMPERS Page 8...
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Page 9: I/O Power Options
4I24M USER'S MANUAL CONFIGURATION +5V ENABLE JUMPER Pin 49 on all of the 4I24M I/O connectors can either be grounded or connected to system +5V through a fuse. +5V is provided on pin 49 to supply power to I/O module racks. This option is selected by the position of the shorting jumper on jumper block W5. - Page 10 4I24M USER'S MANUAL CONFIGURATION POWER OPTION JUMPERS Page 10...
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Page 11: Installation
4I24M USER'S MANUAL INSTALLATION GENERAL When the 4I24M has been properly configured for its application, it can be inserted into a PC/104 stack. The standoffs should then be tightened to secure the 4I24M in its place. When the 4I24M is secured in the stack the 50 pin headers can be plugged in from the sides. -
Page 12: Operation
4I24M USER'S MANUAL OPERATION PORT MAPPING The 4I24M has three 82C55 chips. Each 82C55 chip occupies four contiguous locations in I/O space, for a total of twelve I/O locations, but the 4I24M decoding scheme actually uses sixteen I/O locations per 4I24M card, with the last four locations per card not used. In the following table and I/O connector pinout tables the letters A, B, and C refer to individual ports on a 8255 chip (the standard 8255 port names), while the numeric suffix 0,1, or 2 refers to the specific chip. -
Page 13: Connector Pinout
4I24M USER'S MANUAL OPERATION CONNECTOR PIN-OUT The 4I24M 50 pin I/O connector pinouts are as follows: P3 CONNECTOR SIGNAL A0 bit 0 or +5V fused power (W14 option) A0 bit 1 A0 bit 2 A0 bit 3 A0 bit 4 A0 bit 5 A0 bit 6 A0 bit 7... - Page 14 4I24M USER'S MANUAL OPERATION P1 CONNECTOR SIGNAL A1 bit 0 or +5V fused power (W3 option) A1 bit 1 A1 bit 2 A1 bit 3 A1 bit 4 A1 bit 5 A1 bit 6 A1 bit 7 B1 bit 0 B1 bit 1 B1 bit 2 B1 bit 3...
- Page 15 4I24M USER'S MANUAL OPERATION P2 CONNECTOR SIGNAL A2 bit 0 or +5V fused power (W2 option) A2 bit 1 A2 bit 2 A2 bit 3 A2 bit 4 A2 bit 5 A2 bit 6 A2 bit 7 B2 bit 0 B2 bit 1 B2 bit 2 B2 bit 3...
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Page 16: 8255Loop
4I24M USER'S MANUAL OPERATION 8255LOOP A simple test program is supplied with the 4I24M for functional testing and verification. This program is called 8255LOOP.EXE. 8255LOOP is what's called a loopback test program. It works by sending rotating bit patterns out on all 24 bits of a 8255 programmed for all outputs, then checking to see that the same pattern has been received on a second 8255 programmed for all inputs. -
Page 17: Reference Information
4I24M USER'S MANUAL REFERENCE INFORMATION SPECIFICATIONS UNIT POWER SUPPLY Voltage Supply current (no ext. load) BUS LOADING: Input capacitance Input leakage current Output drive capability Output sink current I/O PORT LOADING: Input logic low Input logic high Output low 2.5 mA sink Output high 2.5 mA source ENVIRONMENTAL:... -
Page 18: Warranty
4I24M USER'S MANUAL REFERENCE INFORMATION WARRANTY Mesa Electronics warrants the products it manufactures to be free effects in material and workmanship under normal use and service for the period of 2 years from date of purchase. This warranty shall not apply to products which have been subject to misuse, neglect, accident, or abnormal conditions of operation. -
Page 19: Schematic Diagrams
4I24M USER'S MANUAL REFERENCE INFORMATION SCHEMATICS Page 19...
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