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Terasic SDI-FMC User Manual

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  • Page 2: Table Of Contents

    TABLE OF CONTENTS Chapter 1 Introduction ........................3 1.1 The Package Contents ..........................3 1.2 Assemble SDI-FMC with FPGA Mainboard ....................4 1.3 Connectivity ............................... 6 1.4 Getting Help ............................... 7 Chapter 2 Architecture of SDI-FMC ....................8 2.1 Features............................... 8 2.2 Layout and Block Diagram.........................
  • Page 3 4.5 Demo on HAN Pilot Platform ........................43 4.6 Si5344 Configuration IP ........................... 48 4.7 LMH1983 Configuration IP ........................49 Chapter 5 Appendix ........................52 5.1 Revision History ............................52 5.2 Copyright Statement ..........................52 SDI-FMC User Manual www.terasic.com April 22, 2019...

  • Page 4: Chapter 1 Introduction

    Chapter 1 Introduction The Terasic SDI-FMC is a 12G SDI daughter card. It enables users to design and verify their 12G SDI product. The board includes 12G SDI, 3G SDI, AES, and Clock Generators. It uses an FMC expansion connector to interface to the FPGA boards which can support 12G SPI IP, e.g. Intel Arria 10 GX FPGA Development Kit (A10GFP) and Arria 10 SoC Development Kit (A10SoC).

  • Page 5: Assemble Sdi-Fmc With Fpga Mainboard

    In order to make the SDI-FMC daughter card and the FMC connector on the FMC card with more secure hookup, the FMC side of the SDI-FMC daughter card has reserved two screw holes, as shown in Figure 1-2. Users can use the screws, copper pillars, and nuts that come with the SDI-...
  • Page 6 In addition to the screws, the SDI-FMC Kit also provides copper pillars and silicon brackets. Users can reference Figure 1-4 for installation of the brackets for the SDI-FMC. Note: The height of these brackets is designed specifically for the Intel A10SoC and A10GFP. These brackets may not be suitable for other FPGA mainboards.

  • Page 7: Connectivity

    Figure 1-7 below show the connectivity of the SDI-FMC to the A10SoC and A10GFP FPGA boards. The SDI-FMC is powered from FPGA mainboard. It is not necessary to connect a power adapter to the SDI-FMC. Figure 1-6 SDI-FMC with A10SoC...

  • Page 8: Getting Help

    For Technical Support, Terasic’s Contact Information is listed below: ⚫ Office Hours: 9:00 a.m. to 6:00 p.m. (GMT +8) ⚫ Telephone: +886-3-575-0880 ⚫ support@terasic.com Email: SDI-FMC User Manual www.terasic.com April 22, 2019...

  • Page 9: Architecture Of Sdi-Fmc

    Chapter 2 Architecture of SDI-FMC This chapter lists the features and describes the architecture of SDI-FMC daughter card. The key features of this module are listed below: • Two 12G SDI inputs and outputs (Connected to 4 75 Ohm BNC connector) •...
  • Page 10 Figure 2-1 Top view of the SDI-FMC Daughter Card The bottom view of the SDI-FMC is shown in Figure 2-2. It depicts the layout and indicates the locations of connectors and key components. Figure 2-2 Bottom view of the SDI-FMC Daughter Card SDI-FMC User Manual www.terasic.com...
  • Page 11 Figure 2-3, Figure 2-4 Figure 2-5 show the block diagrams of the SDI-FMC. The diagrams contain SDI, AES and clock generators three parts. Figure 2-3 shows the SDI function. There are two independent 12G SDI channels in the boards. Each channel contains one transmitter port and one receiving port connected to the BNC connectors.
  • Page 12 The Si5344, LMH1981 and LMH1983 can provide required clock sources for SDI application. Please note, when users connect the SDI-FMC card to FPGA main board and power on it, the FPGA should reset the clock generator Si5344 first to output the correct frequency. The output frequency of Si5344 without reset action will be significantly different from the expected output frequency, which will cause the SDI signal synchronization failure.
  • Page 13 Figure 2-5 Clock Functions in the Block diagram SDI-FMC User Manual www.terasic.com April 22, 2019...

  • Page 14: Using The Sdi-Fmc

    Chapter 3 Using the SDI-FMC This chapter provides information on how to control the hardware of the SDI-FMC. It includes the definition of the FMC interface and how to use the 12G SDI, 3G SDI, AES and clock generator hardware in the board.
  • Page 15 Figure 3-2 Signal names of FMC connector part 2 Figure 3-3 Signal names of FMC connector part 3 SDI-FMC User Manual www.terasic.com April 22, 2019...
  • Page 16 Table 3-1 shows the SDI-FMC pin assignments for the SDI-FMC pins in Quartus Prime. Table 3-1 SDI-FMC Pin Assignments of FMC in Quartus Prime Signal Name Description Pin No. Direction Standard VCG_H LMH1983 Horizontal Output VCCADJ sync reference signal VCG_V...
  • Page 17 FMC_SI5344_I2C_SEL Serial interface select, Output VCCADJ FMC_SI5344_I2C_SEL = 0 is SPI Mode. FMC_SI5344_I2C_SEL = 1 is I2C mode. Please setting high for I2C Interface. FMC_SI5344_A1_SDO I2C Interface Address Input/ Output VCCADJ Select 1 SDI-FMC User Manual www.terasic.com April 22, 2019...
  • Page 18 FMC_SI5344_LOL_n Loss Of Lock Input VCCADJ This output pin indicates when the DSPLL is locked (high) or out-of-lock (low). FMC_SI5344_LOL_XTAL_n Loss Of Signal on Input VCCADJ XA/XB Pins. SDI-FMC User Manual www.terasic.com April 22, 2019...
  • Page 19 MUTEREF threshold L: Input signal is present and cable length is below the MUTEREF threshold FMC_SDI_12G_RX_ALARM_n0 G15 SDI 12G RX 0 Input VCCADJ ALARM signal, SDI-FMC User Manual www.terasic.com April 22, 2019...
  • Page 20 FMC_SDI_12G_RX_ALARM_n1 C19 SDI 12G RX 0 Input VCCADJ ALARM signal, Active low (open drain) H: Normal operation L: Alarm asserted FMC_SDI_12G_RX_SD_xHD1 SDI 12G RX 1 SD Data Input VCCADJ Rate H: SD data rate SDI-FMC User Manual www.terasic.com April 22, 2019...
  • Page 21 L: Alarm asserted FMC_SDI_12G_RC_LOS1 SDI 12G TX 1 Input VCCADJ Reclocker LOS signal, Signal Detect Complement H: No input signal is present or the cable length is above the MUTEREF threshold L: Input signal is SDI-FMC User Manual www.terasic.com April 22, 2019...
  • Page 22 Slave Select for device 0. Low active. FMC_SDI_3G_SPI_SS_n1 SDI 3G SPI Interface, Output VCCADJ Slave Select for device 1. Low active. FMC_SDI_3G_CD_n0 SDI 3G Channel 0 Input VCCADJ Carrier detect, H = No input signal SDI-FMC User Manual www.terasic.com April 22, 2019...
  • Page 23 H = output driver is enabled. L = output driver is powered off. FMC_SDI_3G_TX_RATE_SEL0 G24 SDI 3G Channel 0 Output VCCADJ output slew rate control. Internal pulldown. H = Output rise/fall time complies with SMPTE 259M (SD). SDI-FMC User Manual www.terasic.com April 22, 2019...
  • Page 24 AES Channel 0 output. Output VCCADJ FMC_AES_OUT1 AES Channel 0 output. Output VCCADJ CLK_M2C_p0 Reference Clock 0 for Input VCCADJ FPGA. CLK_M2C_n0 Reference Clock 0 for Input VCCADJ FPGA. CLK_M2C_p1 Reference Clock 1 for Input VCCADJ SDI-FMC User Manual www.terasic.com April 22, 2019...
  • Page 25 Channel 1 SDI_12G_RX_p0 SDI 12G Receiver Input VCCADJ Channel 0 SDI_12G_RX_n0 SDI 12G Receiver Input VCCADJ Channel 0 SDI_12G_RX_p1 SDI 12G Receiver Input VCCADJ Channel 1 SDI_12G_RX_n1 SDI 12G Receiver Input VCCADJ Channel 1 SDI-FMC User Manual www.terasic.com April 22, 2019...

  • Page 26: Using The 12G Sdi

    Developers can communicate with these chips through the SPI interface. Due to the NDA limitation (for detail information about how to control the 12G SDI chips) please contact the chip vender MACOM Company. SDI-FMC User Manual www.terasic.com April 22, 2019...

  • Page 27: Using The 3G Sdi

    Developers can configure the chips through the chips’ SPI interface. For detailed information about how to control the SDI chips, please refer to the chips’ datasheet included in the SDI-FMC CD-ROM.

  • Page 28: Using The Aes

    Figure 3-6 shows the system block diagram of the AES. There are two AES channels on the SDI-FMC Board. Each contains one TX channel and one RX Channel. Figure 3-6 AES System Blok Diagram The AES3 RX channel delivers a 75-Ω load termination with a return loss of 25 dB or more. The signal is inputted through a 75-Ω...
  • Page 29 24-kHz sample rates. The output is unbalanced with a source impedance of 75 Ω and a return loss of 25 dB or more. The peak-to-peak output voltage is 1.0V centered around the ground the transmitter. Figure 3-8 shows the AES3 TX Channel block diagram. SDI-FMC User Manual www.terasic.com April 22, 2019...

  • Page 30: Using The Clock Generators

    Please note, when users connect the SDI-FMC card to FPGA main board and power on it, the FPGA should reset the clock generator Si5344 first to output the correct frequency. The output frequency of Si5344 without reset action will be significantly different from the expected output frequency, which will cause the SDI signal synchronization failure.
  • Page 31 Figure 3-9 Clock Generator System Block Diagram SDI-FMC User Manual www.terasic.com April 22, 2019...

  • Page 32: Chapter 4 Sdi Demonstrations

    3G SDI chips, the triple rate video standard is selected in SD II IP to support SD-SDI, HD-SDI, and 3G-SDI. This demo requires the following hardwares: • A10SoC or A10GFP FPGA Mainboard • SDI-FMC Daughter Card • 12G SDI BNC to BNC Cable x2 • 3G SDI BNC to BNC Cable x1 Figure 4-1 shows the data path of the loopback test for the 12G SDI signals.
  • Page 33 CASE 2 loopback test. It is the complete reverse of CASE1 where the first 3G-SDI chip is configured as input mode and the second SDI chip is configured as output mode. Figure 4-2 Data path for 3G SDI loopback test -CASE1 SDI-FMC User Manual www.terasic.com April 22, 2019...

  • Page 34: System Block Diagram

    27MHz. The SPI_12G_2CH block is a SPI-Daisy Chain controller. It is used to access the six SDI chips on the SDI-FMC board. BUTTON1 can be used to toggle the mute function of 12G SDI Driver chips. When BUTTON1 is pressed, the SPI_12G_2CH block will mute SDI TX chips.
  • Page 35 The block requires a 148.5 MHz reference clock for the pattern generator and a 270 MHz reference clock for the pattern checker. Both of the clocks are coming from the SDI-FMC User Manual www.terasic.com April 22, 2019...

  • Page 36: Demo On A10Soc Fpga Mainboard

    FPGA mainboard. The SPI_3G_2CH block is a SPI controller. It is used to configure the SDI signal direction of the two 3G SDI chips on the SDI-FMC board. BUTTON2 can be used to adjust the video standard. When BUTTON2 is pressed, SD SDI video standard is used. When BUTTON2 is released, 3G SDI video standard is used.
  • Page 37 7. Copy the folder Demonstrations/A10SoC_12G_SDI/demo_batch from the SDI-FMC System CD to the host PC and execute “test.bat” to configure the FPGA. 8. Observe LED0 and LED1 as shown in Figure 4-7. If two LEDs are lit, it means the two channel 12G SDI loopback test passed.
  • Page 38 Lighten when 3G Channel 0 receives a valid SDI pattern LED2(D28) Case 2 When SWITCH0(SW2.5) is 1 (Down Position): Lighten when LMH1983 detects an expected video signal coming from the J7 Video-in BCN connector. LED3(D27) Case 1 SDI-FMC User Manual www.terasic.com April 22, 2019...
  • Page 39 Button Pressed: SD SDI BUTTON2(S6) Button Released: 12G SDI For 3G-SDI Loopback Test Button Pressed: SD SDI Button Released: 3G SDI 3G SDI Loopback direction control. SWITCH0(SW2.5) 1 (Down): CH0 TX / CH1 RX, SDI-FMC User Manual www.terasic.com April 22, 2019...

  • Page 40: Demo On A10Gfp Fpga Mainboard

    ◼ Hardware Setup Figure 4-9 shows the demo setup of SDI-FMC with A10GFP FPGA mainboard. The SDI-FMC should be installed on the FMC-A expansion header of A10GFP. Use one BNC to BNC 3G SDI Cable to connect BNC port J10 and the BNC port J13. Use one BNC to BNC 12G SDI Cable to connect the BNC port J11 and BNC port 15, and use another BNC to BNC 12G SDI Cable to connect the BNC port J14 and BNC port 8.
  • Page 41 2. Make sure the SDI-FMC is installed as shown in Figure 4-9. 3. Mount the SDI-FMC onto the FMC-A expansion header of the A10GFP board. 4. Connect the USB-Blaster USB port J3 of the A10GFP board to the USB port of the host PC with a Mini USB cable.
  • Page 42 Name Description Lighten when 12G Channel 0 receives a valid LED0(D10) SDI pattern Lighten when 12G Channel 1 receives a valid LED1(D9) SDI pattern Case 1 LED2(D8) When SWITCH0(SW2.5) is 0 (Down Position): SDI-FMC User Manual www.terasic.com April 22, 2019...
  • Page 43 Lighten when 3G Channel 1 receives a valid SDI pattern BUTTON0(PB0) SYSTEM reset 12G cable driver IC mute control BUTTON1(PB1) Button Pressed: MUTE Button Released: UNMUTE Video Standard Selection, BUTTON2(PB2) For 12G-SDI Loopback Test Button Pressed: SD SDI SDI-FMC User Manual www.terasic.com April 22, 2019...

  • Page 44: Demo On Han Pilot Platform

    “Demonstrations\A10GFP_12G_SDI” folder from the SDI-FMC System CD. This section will demonstrate connect the SDI-FMC daughter card to the HAN pilot platform and perform loopback test of 12G and 3G SDI image data. This demonstration has built-in 12G and 3G SDI pattern generator IP in the HAN pilot platform FPGA.
  • Page 45 ◼ Execute Demonstration Please follow the procedures below to setup the demonstration: 1. Power off the HAN pilot platform. 2. Make sure the SDI-FMC is installed on the HAN pilot platform as shown in Figure 4-12. 3. Set the VCCIO of the FMC connector to 1.8V by shorting J2.5 and J2.6 as shown in the Figure 4-13.
  • Page 46 5. Power on the HAN pilot platform. 6. Make sure the Quartus Prime and the USB-Blaster II driver has been installed on the host 7. Copy the folder Demonstrations/HAN_12G_SDI/demo_batch from the SDI-FMC System CD to the host PC and execute “test.bat”.
  • Page 47 Lighten when LMH1983 detects an expected video signal coming from the J7 Video-in BCN connector. HEX1_DP Case 2 When set SW0 to logic 1 (Up Position): Lighten when 3G Channel 1 receives a valid SDI pattern SDI-FMC User Manual www.terasic.com April 22, 2019...
  • Page 48 0 (Down): CH0 RX / CH1 TX Si5344 27Mhz Reference Clock Selection 1 (Up): From LMH1983 0 (Down): From FPGA LMH1983 Mode Selection Default 0 1 : Select Mode 0, AV-Sync Mode 0 : Select Mode 3, Free-Run Mode SDI-FMC User Manual www.terasic.com April 22, 2019...

  • Page 49: Si5344 Configuration Ip

    The source code of this Quartus project for the loopback demo with the HAN board is available in the “Demonstrations\HAN_12G_SDI” folder from the SDI-FMC System CD. The reference clock of SDI IP comes from the Si5344 clock generator chip on the SDI-FMC. Terasic provides a Si5344 configure IP for developers to configure Si5344 to generate the required reference clock.

  • Page 50: Lmh1983 Configuration Ip

    In MODE0, the FPGA would loopback the three H/V/F sync signals from LMH1981 to LMH1983. Users need to provide a video signal to the VIDEO-IN BNC connector J7 on the SDI-FMC board. For supported video formats, please refer to the datasheet of LMH1981.
  • Page 51 Figure 4-16 MODE1: Video Timing Generation for HD-SDI Up-Conversion Figure 4-17 MODE2: A/V Clock Generation with Recognized Clock-Base Input Reference Figure 4-18 MODE3: A/V Clock Generation Using Free-Run SDI-FMC User Manual www.terasic.com April 22, 2019...
  • Page 52 The IP named as LMH1983_CONFIG is defined below. In this demonstration, MODE0 and MODE3 are used. SDI-FMC User Manual www.terasic.com April 22, 2019...

  • Page 53: Chapter 5 Appendix

    04/11,2019 Add section 4.5 12G SDI demo for HAN Pilot Platform Copyright © Terasic Inc. All rights reserved. We will continue to provide examples and lab exercises on our SDI-FMC webpage. For more information, please visit http://sdi-fmc.terasic.com. SDI-FMC User Manual www.terasic.com...

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