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Summary of Contents for Concurrent Technologies PP 110/01 Series
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® ® CompactPCI Pentium III-M Single Board Computer Manual Order Code 560 0009 Rev 04 June 2003 Concurrent Technologies Inc Concurrent Technologies Plc 4 Gilberd Court 3840 Packard Road Newcomen Way Suite 130 Ann Arbor, MI 48108 Colchester, Essex CO4 9WN...
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Concurrent Technologies reserves the right to change specifications at any time without notice. Concurrent Technologies assumes no responsibility either for the use of this document or for any infringements of the patent or other rights of third parties which may result from its use. In particular, no license is either granted or implied under any patent or patent rights belonging to Concurrent Technologies.
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BMC · · · · · Baseboard Management Controller BSB· · · · · · Back Side Bus CCT· · · · · · Concurrent Technologies CPCI · · · · · CompactPCI CPU · · · · · Central Processing Unit CRT·...
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NOTATIONAL CONVENTIONS NOTE Notes provide general additional information. WARNING Warnings provide indication of board malfunction if they are not observed. CAUTION Cautions provide indications of board or system damage if they are not observed. PP 110/01x Artisan Technology Group - Quality Instrumentation ... Guaranteed | (888) 88-SOURCE | www.artisantg.com...
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Revision Revision History Date Preliminary Release June 2002 First Full Release July 2002 Changes to ISA Registers, added sections on RMI and CPCI Bridge programming, various minor corrections April 2003 Updated for Rev B board June 2003 PP 110/01x Artisan Technology Group - Quality Instrumentation ... Guaranteed | (888) 88-SOURCE | www.artisantg.com...
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This page has been left intentionally blank PP 110/01x Artisan Technology Group - Quality Instrumentation ... Guaranteed | (888) 88-SOURCE | www.artisantg.com...
General This manual is a guide and reference handbook for engineers and system integrators who wish to use the Concurrent Technologies’ PP 110/01x ultra high-performance Pentium III-M single board computer. The board has been designed for high-speed multiprocessing applications ™...
Introduction and Overview The PP 110/01x - Main Features The PP 110/01x is a member of the Concurrent Technologies range of single-board computers for the CompactPCI bus architecture. It has been designed as a powerful single board computer based upon the Pentium III-M processor, the 82546EB dual channel Gigabit Ethernet controller, and the 69030 Graphics Controller.
Introduction and Overview 1.2.5 PCI Busses There are two on-board PCI busses supported by the CNB30LE North Bridge. The secondary PCI bus is 64-bits wide and provides a high performance, up to 264 Mbytes/s, connection between the CNB30LE controller, Ethernet controller, PMC sites and the CompactPCI bridge. The Primary PCI bus is 32-bits wide and provides a lower performance, up to 132 Mbytes/s, connection between the CNB30LE, PC-AT peripherals and graphics controller.
Introduction and Overview 1.2.13 CompactPCI Interface The PP 110/01x is a CompactPCI compatible System Controller and Peripheral Board. It may also act as a Satellite board in any backplane slot. The board uses a 64-bit interface ® implemented with a HiNT Corporation (HINT) HB6 PCI to PCI bridge.
Introduction and Overview AD PP5/001 Peripheral Functions The AD PP5/001 Transition Module contains a Super I/O controller. This device provides the following interfaces: Floppy disk interface for up to two floppy disk drives Parallel port interface Two RS232 serial interfaces Two general purpose inputs Two general purpose outputs External Reset input...
Introduction and Overview Additional Board Options The PP 110/01x board may be ordered with one of several different configuration options, namely, Soldered-on SDRAM capacity 512 Mbytes 1 Gbyte Ethernet (on J3 connector) Configured for PICMG 2.16 backplane networking Configured for rear panel Ethernet via connectors (on Transition Module) CompactPCI Signaling Voltage 5V (33MHz only) 3.3V (33MHz or 66MHz automatic selection)
Hardware Installation General This chapter contains general information on unpacking and inspecting the PP 110/01x after shipment, and information on how to configure board options and install the board into a CompactPCI chassis. CAUTION It is strongly advised that, when handling the PP 110/01x and its associated components, the user should at all times wear an earthing strap to prevent damage to the board as a result of electrostatic discharge.
Once unpacked, the board should be inspected carefully for physical damage, loose components etc. In the event of the board arriving at the customer’s premises in an obviously damaged condition Concurrent Technologies or its authorized agent should be notified immediately.
Hardware Installation Default Jumper Settings Front Panel Factory Use 1 Factory Use 5 Console Mode Factory Use 6 CPCI Push Button Reset Switch VGA and Do Not Fit Keyboard Do Not Fit Enable Reset Section 2.10.3 Section 2.4.8 Section 6.1 CPCI Reset Input Enable Section 2.10.1...
Hardware Installation Front Panel Indicators and Controls When installing or removing the board for the first time, or when checking it’s operation, it can be very useful to note the behavior of the LEDs on the front panel. Figure 2-2 shows the location of the LEDs, and their purpose is outlined below.
Hardware Installation 2.4.8 Switch (SW) The reset or NMI function is selected by the setting of the Front Panel Reset and NMI Switch jumper shown in Figure 2-3. Front Panel Reset (Default) Figure 2-3 Front Panel Reset and NMI Switch Jumper Selecting the Reset jumper position setting will cause the board to be reset when the front panel switch is operated.
Hardware Installation Installation of On-Board Mass Storage If an on-board mass storage option has been ordered, it will be necessary to install the option at this time. The mass storage option plugs into connector P2 and is secured via screws and spacers using the four mounting holes as shown in Figure 2-4 below.
Hardware Installation 2.5.1 Hard Disk Storage Kit (AD CP1/DR1) The option kit comprises: A 2.5” EIDE disk drive A ribbon cable assembly Four M3 x 10mm screws Four M3 x 5mm spacers The ribbon cable assembly has a 50-way connector at one end and a 44-way connector at the other end.
Hardware Installation 2.5.2 CompactFlash Storage Kit (AD 200/001) The option kit comprises: A CompactFlash carrier module Four M3 panhead screws CompactFlash Carrier Module CompactFlash Sites Site 1 Site 2 Pillars Figure 2-6 CompactFlash Carrier Module Installation The M3 panhead screws may be loosely screwed into the end of the pillars, if so unscrew them.
Hardware Installation The DIL switch on the AD 200/001 should be set as shown in Figure 2-7. Figure 2-7 AD 200/001 DIL Switch Settings PP 110/01x Artisan Technology Group - Quality Instrumentation ... Guaranteed | (888) 88-SOURCE | www.artisantg.com...
Hardware Installation Adding or Replacing DRAM Modules The PP 110/01x accepts standard 144-pin SODIMM modules fitted with 3.3V PC133 DRAM. One socket is provided and will accommodate SODIMMs of 256 Mbytes or 512 Mbytes capacities. NOTE SODIMMs using 256Mbit DRAMs with 8K refresh are required. Figure 2-8 shows shows the way in which SODIMMs are fitted or removed.
Hardware Installation Battery Installation/Replacement The on-board Real-Time Clock and CMOS memory used by the PC BIOS firmware are powered by a 3.3V Lithium battery when the board is powered OFF. This battery also powers the static RAM device. It is advisable, though not essential, for the battery to be fitted prior to using the board.
Hardware Installation Installing or Removing a PMC Module Before installing a PMC module, check that the PP 110/01x board PMC V(I/O) voltage is configured to match the requirements of the PMC module. If two PMC modules are fitted, their V(I/O) requirements must be the same. CAUTION If the PP 110/01x is not correctly configured to match the PMC module V(I/O) requirements, it may result in damage to the module or the PP 110/01x.
Hardware Installation CompactPCI Operating Mode Selection This is normally automatic and depends only on what type of slot the board is installed into, as detailed below: Slot Mode System Controller System Controller Bussed Peripheral Peripheral Non-Bussed Peripheral Satellite A jumper is provided to force Satellite mode operation in any slot. The settings are shown in Figure 2-12.
Hardware Installation 2.10 Reset Sources In addition to the front panel switch described in Section 2.4.8, the board may be reset from several external sources, as described below. Table 2-1 outlines how board and system resets can be achieved using the available jumper options. Mode Board Level Reset Sources System Reset Sources...
Hardware Installation 2.10.1 CompactPCI Reset The CompactPCI Reset signal is generated by the System Controller and is routed to all bussed peripheral slots. If the board is in Peripheral mode it must respond to the CompactPCI Reset signal. However, if it is in Satellite mode, it may be preferable for it to ignore the Reset signal.
Hardware Installation 2.10.2 External Reset When the PP 110/01x board is used with an AD PP5/001 rear transition module, a local (board-level) reset may be generated from a connector on the AD PP5/001 (see that board’s Technical Reference Manual for details). The action of that connector input is controlled on the PP 110/01x by the External Reset jumper shown in Figure 2-14.
Hardware Installation 2.10.3 CompactPCI Push Button Reset The Push Button Reset signal available on the J2 connector (PRST#) will cause a board reset if the board is in the System Controller slot. This input can be driven from an open collector TTL output (or discrete transistor) or normally open switch/relay contacts.
If power-up does not follow the sequence described above this will indicate that the board is not operational. NOTE This sequence of events assumes the PP 110/01x has Concurrent Technologies standard BIOS firmware and that the board is configured to the factory setting described in Section 2.3.
Hardware Installation 2.11.3 Hot Swap Procedure - Installing The board is installed and powered up as follows: Slide the board into the designated slot, making sure that the board fits neatly into the runners. Push the board into the card-cage until the J1 ... J5 connectors are firmly located. Use the injector/ejector handles for the final push.
Software Installation In most cases, installing operating system software on the PP 110/01x board follows the same sequence as installing on a PC. However, there are some additional points to note. The sections below summarize the special actions required for a few common operating systems. Starting up for the first time Many operating systems running on the board will want to use the standard Real-Time Clock hardware.
Software Installation Bootloading from CD-ROM Operating systems which install on the target hardware will generally install from CD-ROM, or may require both a CD-ROM and floppy disk. Bootloading from floppy disk requires no special steps other than to connect the drive using an appropriate cable. To bootload from CD-ROM, use the following procedure: While the BIOS is running its memory test, press the <ESC>...
Software Installation ® Installing Windows NT To install Windows NT from CD-ROM, set up the board initially using the steps outlined in Sections 3.1 and 3.2 above, ensuring that all the necessary drives are connected. Then follow the procedure below. Obtain the Ethernet driver from the Intel web site, starting from the following address: http://www.intel.com Click “Support”, “resources for developers”, then follow the links for: “Networking Drivers”,...
Software Installation ® Installing Windows 2000 To install Windows 2000 from CD-ROM, set up the board initially using the steps outlined in Sections 3.1 and 3.2 above, ensuring that all the necessary drives are connected. Then follow the procedure below. Obtain the Ethernet driver from the Intel web site, starting from the following address: http://www.intel.com Click “Support”, “resources for developers”, then follow the links for: “Networking Drivers”,...
10) If the X11 window system will be used, there are some additional steps to take. The video driver included in RedHat 7.1 is not fully compatible with the Asiliant 69030 graphics controller. Concurrent Technologies can provide on request an updated driver which corrects this problem. The new driver must be placed in the /usr/X11R6/lib/modules/drivers directory.
Software Installation Using VxWorks 5.4 with Tornado 2 Applications using this operating system are not developed on the target hardware. Concurrent Technologies can supply on request a separate Board Support Package (BSP) for this board and many others. Read the “readme” file provided with this package for details of how to configure and run VxWorks on the PP 110/01x board.
Mass Storage Interfaces The PP 110/01x board has two interfaces which can be used to attach mass storage devices: a Primary EIDE (ATA100) interface is accessible via the CompactPCI J5 connector a Secondary EIDE (ATA100) interface supporting on-board Mass Storage option kits In addition, the AD PP5/001 Transition Module provides a floppy disk interface.
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Ethernet Interfaces The PP 110/01x board is fitted with two independent 1Gbit/s Ethernet interfaces, implemented with an Intel 82546EB controller. These interfaces can connect in different ways, depending primarily on the build configuration of the board. This configuration is indicated by the first digit of the board name suffix.
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Other Interfaces Many additional standard interfaces are provided on the PP 110/01x board. These interfaces consist primarily of those found in a regular desktop or mobile PC, and are outlined below. Serial Ports One RS232 serial interface is provided on the PP110/01x board, and connects via the front panel using a shared 26-way high density connector.
Other Interfaces Keyboard and Mouse Ports A shared 26-way high density PS/2 connector on the front panel of the board provides connections for a PC keyboard and a PS/2 mouse. The pin-out of the front panel connector is detailed in Section A.5.1. A splitter cable (part number CB 26D/124) is required to access the keyboard and mouse interfaces.
The remainder of this chapter outlines the functions provided by this board via IPMI, and details some ways in which these features can be used. For a more complete description of the IPMI protocols and implementation on Concurrent Technologies’ boards, refer to the document: “Intelligent Platform Management Interface for Concurrent Technologies Boards”, order code 555 0042.
Intelligent Platform Manager Interface IPMI Compatibility This board implements a version of IPMI compatible with revision 1.5 of the IPMI specifications. It includes the mandatory elements of the PCI Industrial Computer Manufacturer’s Group (PICMG) specification 2.9. The IPMI facilities supported by the PP 110/01x board are implemented using a microcontroller and its resident firmware with non-volatile operational data stored in EEPROM.
Intelligent Platform Manager Interface IPMI Overview The PP 110/01x board includes hardware and firmware which implements an IPMI as a separate resource to the main Pentium III-M processor. The processor communicates with the IPMI subsystem through a standardized hardware interface using multi-byte message sequences, transferring one byte at a time using a handshaking protocol.
Intelligent Platform Manager Interface 7.3.4 Sensors The PP 110/01x board is capable of monitoring the temperature of the board and the processor chip, the levels of the main power supply voltage rails, the status of a system fan and the board’s Geographic Address (effectively its CompactPCI bus slot number).
Intelligent Platform Manager Interface Supported Commands The PP 110/01x board supports a subset of the command messages as defined in the IPMI specification. All commands, unless explicitly stated, expect a response which is generally retrieved through the SMIC interface. Commands that are not supported receive a “Invalid Command”...
Intelligent Platform Manager Interface 7.4.1 Get Self Test Results Command On this board, no self test results are available via this command. The PC BIOS runs a Power On Self Test (POST) sequence, but the results of these tests are reported only via on-screen messages and flashes of the POST LED.
Intelligent Platform Manager Interface 7.4.4 Sensor Commands Table 7-1 lists the sensors fitted to this board, alongside the sensor number and type information found in their SDRs. These sensors are scanned by the IPMI subsystem at a rate of approximately 10Hz. The values returned by the Get Sensor Reading command are the values obtained in the most recent scan.
Intelligent Platform Manager Interface 7.4.4.1 Board Temperature Sensor This sensor is located in the position shown in Figure A-1. A Maxim 1617 or 1617A device is used to measure this reading, and the result is returned by the IPMI subsystem in degrees Celsius.
Intelligent Platform Manager Interface 7.4.4.10 CompactPCI SYSEN Signal This sensor reading indicates status of the SYSEN# pin on the CPCI backplane. The board is in the system controller slot if the value is 1. If the value is 0, the board is not in the system controller slot.
Intelligent Platform Manager Interface 7.4.5 FRU Inventory Data The FRU Inventory Area shares the non-volatile memory with the repository of Sensor Data Records and the System Event Log and contains information about the board, including, for example, the manufacturer’s name, part number and serial number. The FRU Inventory Area comprises, at most, six information areas.
This is defined as the number of minutes since 00:00 hours on the 1st January 1996. Manufacturer’s Name 7.4.5.2.5 This is a string of characters and is set to “Concurrent Technologies”. It is not zero terminated. PP 110/01x 7-11 Artisan Technology Group - Quality Instrumentation ... Guaranteed | (888) 88-SOURCE | www.artisantg.com...
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Intelligent Platform Manager Interface Board’s Name 7.4.5.2.6 This is a string of characters representing the board’s name and is set to “PP 110/01x”. It is not zero terminated. Board’s Part Number 7.4.5.2.7 This is a string of characters representing the board’s internal part number. It is not zero terminated.
Intelligent Platform Manager Interface Programming Examples 7.5.1 Using the SMIC Interface The PP 110/01x single board utilizes the Server Management Interface Controller (SMIC) as its interface with the I/O ports at the standard addresses (i.e. 0CA9h, 0CAAh and 0CABh). The IPMI specification has a complete description of the SMIC interface.
Intelligent Platform Manager Interface 7.5.2 Using the Watchdog Timer The IPMI provides a standardized watchdog facility which is fully described in the IPMI specification. The following C program fragment sets and resets the watchdog facility: /* network function codes */ #define NFC_APP_REQUEST 0x06 #define NFC_APP_RESPONSE...
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Intelligent Platform Manager Interface * RETURNS: E_OK if it is OK, or error code unsigned short int wSetWatchdog unsigned char bDontLog, /* FALSE to log event */ unsigned short int wTimeoutInterval, /* multiples of 100ms */ unsigned char bTimeoutAction, unsigned char bPreTimeoutInterval, /* multiples of 1s */ unsigned char bPreTimeoutInterrupt, unsigned char bTimerUse,...
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Intelligent Platform Manager Interface The following example shows how to set the watchdog to power cycle if the watchdog is not restarted within 20 seconds, generate an NMI if there is less than 10 seconds before the watchdog expires, define its use as an “operating system load” watchdog, clear any OEM expiration flags, log the watchdog failure in the event log: wSetWatchdog (FALSE, 200, TO_ACTION_POWER_CYCLE, 10, PRE_TO_INT_NMI,...
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Intelligent Platform Manager Interface 7.5.3 Reading Sensors The IPMI specification supports many commands to manage and interrogate sensors. The following program fragment illustrates how the current reading of a sensor can be obtained. /* network function codes */ #define NFC_SENSOR_EVENT_RQ 0x04 /* commands */ #define CMD_GET_SENS_RD 0x2D...
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Intelligent Platform Manager Interface abRequest [1] = CMD_GET_SENS_RD; /* command */ abRequest [2] = bSensorId; vBmcSmicSmsMessageWrite (abRequest, 3); vBmcSmicSmsMessageRead (abResponse, &bLength); if (abResponse [2] != COMPLETION_OK) wStatus = E_COMPLETION; else psSensorReading->bData = abResponse [3]; psSensorReading->bStatus = abResponse [4]; return wStatus; The following example shows how to read the CPU temperature sensor and voltage sensors: /* read CPU temperature, sensor ID = 01h */ wStatus = wGetSensorReadingCmd (0x01, &sSensorReading);...
Refer to Section 9.5 for details of this register. The top page of Application Flash device 2 is used by Concurrent Technologies for storage of factory test firmware. The user may overwrite this page if desired, but should be aware that it may be re-instated if the board is ever returned to Concurrent Technologies for repair or upgrading.
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Flash EPROM, SRAM and DRAM This page has been left intentionally blank PP 110/01x Artisan Technology Group - Quality Instrumentation ... Guaranteed | (888) 88-SOURCE | www.artisantg.com...
Additional Local I/O Functions The PP 110/01x supports a variety of I/O functions whose addresses are summarized in Table 9-1. NOTE A second LPC Super I/O controller (designated TM Super I/O in Table 9-1) is located on the AD PP5/001 Transition Module. This device provides some of the legacy peripheral functions.
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Additional Local I/O Functions Most of the addresses are standard PC-AT compatible values, but at addresses 0210h - 021Fh the board provides custom Status and Control registers for the board specific features. There are 17 byte wide status and control registers. They fall into four groups, namely, general-purpose registers, RMI interface registers, Long Duration Timer registers and IPMI SMIC interface registers.
Additional Local I/O Functions Status & Control Register 0 This register is at I/O address 210h. NOTE Bits 3 - 0 have different read and write functions. |________|________|_________|________|_________|_________|_________|_________| PMC2 PMC1 ENUM# FORCE CPCI PCI_P RFU/ INTERRUPT SATELLITE 66MHz/ 66MHz/ PRESENT/ DEVICE ENABLE DEVICE...
Additional Local I/O Functions Status & Control Register 1 This register is at I/O address 211h. |________|________|_________|________|_________|_________|_________|_________| FP NMI IPMI FAL# DEG# MODE CONSOLE USER SYSEN# Bit 0: CompactPCI SYSEN# Pin Status (Read Only) This bit indicates whether or not the board is plugged into a System Controller slot. 0 = not System Controller 1 = System Controller Bit 1: User Jumper (Read Only)
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Additional Local I/O Functions Status & Control Register 2 This register is at I/O address 212h. NOTE Bits 2 and 0 of this register are device locked. |________|________|_________|________|_________|_________|_________|_________| EREADY REV2 REV1 REV0 AUX V SPEED STEP REAR Bit 0: Ethernet Channel 0 Routing (Read/Write) 0 = Ethernet 0 routed to front panel RJ45 1 = Ethernet 0 routed to J3 connector Bit 1: Reserved...
Additional Local I/O Functions General Purpose I/O Register This register is at I/O address 213h. |________|________|_________|________|_________|_________|_________|_________| INPUT 1 INPUT 0 OUTPUT 1 OUTPUT 0 Bits 1 - 0: General Purpose Outputs to Transition Module (Read/Write) 0 = set output line to 0 1 = set output line to 1 Bits 3 - 2: Reserved Bits 5 - 4: General Purpose Inputs from Transition Module (Read Only)
Additional Local I/O Functions Application Flash Paging Register This register is at I/O address 214h. It controls the Application Flash devices. |________|________|_________|________|_________|_________|_________|_________| FLASH DEVICE PAGE 4 PAGE 3 PAGE 2 PAGE 1 PAGE 0 PROG/EN SELECT STATUS Bits 4 - 0: Application Flash Page (Read/Write) Pages are in the range 00h - 1Fh.
Additional Local I/O Functions Interrupt Control Register This register is at I/O address 215h. It provides control over interrupts from the IPMI. |________|________|_________|________|_________|_________|_________|_________| SMS_ATN SMIC SMS_ATN SMIC INT FLAG INT FLAG NOT BUSY INT ENA INT ENA NOT BUSY INT FLAG INT ENA Bit 0: SMIC Not Busy Interrupt Enable (Read/Write) This bit allows an interrupt to be generated when the P89C664 microcontroller clears the SMIC...
Additional Local I/O Functions RMI Registers The PP 110/01x board includes hardware which implements a Concurrent Technologies proprietary set of registers termed the Resource Manager Interface (RMI). These registers provide several diagnostic and other features used at the factory to test the boards.
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Additional Local I/O Functions * monitor the "rmiBusy" bit of "rmiStatus" to determine if the Resource * Manager Interface is busy and if so wait until it is no longer busy. while ((inbyte (rmiStatus) & rmiBusy) == rmiBusy) ; /* wait and do nothing ... */ outbyte (rmiAddress, Address);...
Additional Local I/O Functions Long Duration Timer / Periodic Interrupt Timer The Long Duration Timer (LDT) consists of a 32-bit free running counter with a 32-bit holding register and a status & control register. It may be used by user software to timestamp events to a resolution of 1 microsecond.
Additional Local I/O Functions 9.8.3 LDT Mid-high Byte Register This register is at I/O address 21Ah. |________|________|_________|________|_________|_________|_________|_________| LDT23 LDT22 LDT21 LDT20 LDT19 LDT18 LDT17 LDT16 Bits 7 - 0: Mid-High Byte of LDT (Read/Write) Reading this register returns the mid-high byte of the holding register. Writing to this register loads a value into the mid-high byte of the LDT counter.
Additional Local I/O Functions 9.8.5 LDT / PIT Status & Control Register This register is at I/O address 21Ch. It controls the operation of the LDT. The LDT clock frequency is selectable from two sources, namely the Local Super I/O HF Clock output or LF Clock output.
Additional Local I/O Functions 9.8.6 Programming the LDT/PIT The following code fragments illustrate how the system software, by using the on-board hardware, can create accurate time delays and measure elapsed times, accurate to 1m s, irrespective of the CPU’s operating frequency. The LDT and PIT control registers and operational modes are defined thus: #define TIMER_BYTE_0 (0x0218U)
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Additional Local I/O Functions It is possible to implement delays of 5ms, 2ms, 1ms, 500m s, 200m s and 100m s by utilizing other PIT modes. The PIT can generate an interrupt whenever the PIT rolls over. The system programmer must initialize the interrupt vector, enable PIC interrupts, etc.
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Additional Local I/O Functions outbyte (CONTROL_STATUS, MODE_STOP); dElapsedTime (UINT32) inbyte (TIMER_BYTE_0); dElapsedTime |= ((UINT32) inbyte (TIMER_BYTE_1)) << 8; dElapsedTime |= ((UINT32) inbyte (TIMER_BYTE_2)) << 16; dElapsedTime |= ((UINT32) inbyte (TIMER_BYTE_3)) << 24; printf ("Elapsed time = %u.%06u seconds\n", dElapsedTime / 1000000U, dElapsedTime % 1000000U); The TIMER_BYTE_0, TIMER_BYTE_1, TIMER_BYTE_2 and TIMER_BYTE_3 control registers are at successive addresses and form a 32-bit register in “little endian”...
Additional Local I/O Functions 9.8.7 Interrupt Configuration Register This register is at I/O address 21Dh. NOTE This register is not present in early versions of the board. Software can toggle bit 0 and read it back to test if this register is present. On early versions of the board this register will read as all 1’s.
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Additional Local I/O Functions Bits 5, 4 Mode 0 0 Normal 0 1 Ethernet interrupts for channels 0 and 1 to PMC1 INTB and INTD respectively (PMC2 INTB and INTD are not available) 1 0 Ethernet interrupts for channel 0 and 1 to PMC2 INTB and INTD respectively (PMC1 INTB and INTD are not available) 1 1 Ethernet interrupt for channel 0 to PMC1 INTB and Ethernet interrupt for channel 1 to PMC2 INTB (PMC1 INTD and PMC2 INTD are not available)
Additional Local I/O Functions IPMI SMIC Interface The IPMI hardware on this board is accessed by the local CPU using the SMIC interface (see Chapter 7 for an explanation of these terms and of the purpose of IPMI). The following sections outline the register contents, and example code for using this interface is provided in Section 7.5.
Additional Local I/O Functions 9.10 P.O.S.T. LED / SPEAKER The P.O.S.T. LED is controlled via the speaker port. The P.O.S.T. LED replaces a PC speaker and is programmed in the same way a speaker would be programmed. The board also outputs the speaker port via a high current open collector driver on the CompactPCI J5 connector for connection to an external speaker if required.
Additional Local I/O Functions 9.11 PORT 80 A header has been provided for monitoring data written to I/O Port 80. The PC BIOS writes status bytes to Port 80 that indicate a boot progress status and/or highlight any faults found. Data written to this port can be monitored using a Logic State Analyzer (LSA) or seven segment hexadecimal displays.
PC BIOS The PP 110/01x board is fitted with PC BIOS firmware that performs many of the functions of a standard desktop PC. It also includes additional features specifically tailored for the CompactPCI bus environment. In addition to the core BIOS firmware, the board is fitted with BIOS Extensions for remote bootload capability via either of the on-board Ethernet channels.
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PC BIOS To allow correct operation of the BIOS Setup menus via the serial interface, the terminal or emulator program should be configured to automatically wrap long lines. 10-2 PP 110/01x Artisan Technology Group - Quality Instrumentation ... Guaranteed | (888) 88-SOURCE | www.artisantg.com...
PC BIOS 10.2 The PC BIOS Startup Sequence When the board starts up without operator intervention, it will run a basic Power-On Self-Test (POST) sequence, including ECC DRAM initialization and a DRAM test. The full DRAM test will be omitted on subsequent restarts if the BIOS configuration settings have not been changed. Once the DRAM test has completed, the board will try to bootload application software from any attached mass storage medium or through one or both of the Ethernet interfaces.
PC BIOS 10.3 Boot device selection The order in which the PC BIOS searches for a bootable medium is pre-configured but may be altered by the operator using the Boot setup menu. When the order is changed using this menu it will be retained in non-volatile memory so that the order is maintained after a restart.
PC BIOS 10.4 PCI Bus Resource Management The bus structure of the PP 110/01x is quite complex. There are two on-board PCI busses: a 64-bit bus which connects to the Ethernet controller, the PMC sites and the CompactPCI bridge chip, and a second 32-bit bus which connects to the remaining on-board peripherals (CSB5, graphics).
PC BIOS Table 10-1 lists the configurable interrupts for this board. The actual allocation of PCI bus interrupts to available interrupt controller inputs will depend on both the default “Plug-and-play” settings programmed by the PC BIOS, and the way in which the user has overridden them using the Setup screens.
PC BIOS 10.4.2 PCI Device IDs Each PCI bus, and each device on an individual PCI bus, has a unique ID. For the PP 110/01x, the bus and device IDs are listed in Table 10-2. The ServerWorks chipset includes two PCI bus bridges to interface to the 64-bit and 32-bit on-board PCI busses, and these bridges are identified by the same PCI device ID but with different function codes.
PC BIOS 10.5 CompactPCI Bridge Configuration ® The BIOS provides Setup menus that allow configuration of certain features of the HiNT CompactPCI Bridge, these can be found under the CompactPCI top level menu. The fields available via Setup depend on the board’s operating mode. 10.5.1 System Controller Mode In System controller mode only one Setup option is provided.
PC BIOS 10.5.4 Peripheral Mode Window-Size Limitations The HB6 Bridge forms PCI addresses by concatenating the least significant bits from the CPU generated address and the most significant bits from the translation base address; the contribution from each part is fixed and depends on the window type. However, the BIOS always aligns base addresses according to their resource size, to achieve optimal packing.
PC BIOS 10.6 User Selectable NVRAM Defaults The BIOS provides a facility through which the user can save preferred setup option settings to Flash memory (NVRAM). Then, if the BIOS detects that the contents of NVRAM is corrupt, the user can elect to restore the contents from the saved settings, rather than loading factory configured defaults.
Specifications Environmental Specification A.2.1 Temperature Range Operating . . 0 to +55ºC @ 400LFM air flow Storage . . -40 to +70ºC NOTE If the on-board disk drive option is fitted, the operating temperature range will be restricted to +5 to +55ºC and the storage temperature range will be restricted to -40 to +65ºC.
Specifications A.5.1 Shared Front Panel Connector Pin-outs This connector provides access to the keyboard, mouse, VGA, CRT and COM1 serial port interfaces. It is a female 26-way high density D-type connector. The pin-out is as follows. Figure A-3 Shared I/O Connector (Front View) Signal Name Signal Name Signal Name...
Specifications A.5.7 PMC Site Connectors (J11 - J14 and J21 - J24) Pin-outs Signal assignments on the PMC connectors are shown in Tables A-9, A-10 and A-11. Pin No. Signal Name Pin No. Signal Name -12V INTA# INTB# INTC# BUSMODE#1 INTD# +3.3V††...
Specifications A.5.9 Processor Debug Port (J6) Pin-outs The processor debug port, which is supported by a number of emulator devices, is accessible via an Intel specified 30-way receptacle connector with the following pin-out. Pin No. Signal Name CPU Reset Debug Reset CPU TCK CPU TDI CPU TMS...
Specifications A.5.10 Port 80 (J10) Pin-outs Figure A-5 Port 80 Connector Pin No. Signal Name Port 80 Write # +5 Volts # Denotes active low Table A-13 Port 80 Connector Pin-outs A-16 PP 110/01x Artisan Technology Group - Quality Instrumentation ... Guaranteed | (888) 88-SOURCE | www.artisantg.com...
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