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System Configuration
Clock for M14+
MAIN Clock(24Mhz)
10pF
XTAL_IN
C101
R180
560
10pF
XTAL_OUT
C102
System Clock for Analog block(24Mhz)
PLL SET[1:0] : internal pull up
"00" : CPU(1200Mhz),M0 / M1 DDR(792,792 Mhz)
"01" : CPU(1056Mhz),M0 / M1 DDR(672,672 Mhz)
"10" : CPU(1056Mhz),M0 / M1 DDR(792,792 Mhz)
"11" : CPU( 960Mhz),M0 / M1 DDR(792,792 Mhz)
Extenal test only
OPT
R103
3.3K
PLLSET1
R104
3.3K
PLLSET0
OPT
+3.3V_NORMAL
OP MODE[1:0]
"00" : Normal Mode
INSTANT boot MODE
"01/10/11" : Internal Test mode
"1 : Instant boot
"0 : normal
+3.3V_NORMAL
(internal pull down)
OPT
R101
3.3K
INSTANT_BOOT
OPM1
R102
3.3K
OPM0
OPT
Extenal test only
INSTANT_MODE0
+3.3V_NORMAL
+3.3V_NORMAL
+3.3V_NORMAL
+3.3V_NORMAL
I2C PULL UP
THE
SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES
SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION.
FIRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS
ESSENTIAL THAT ONLY MANUFACTURES SPECIFIED PARTS BE USED FOR
THE CRITICAL COMPONENTS IN THE
SYMBOL MARK OF THE SCHEMETIC.
M14-Peripheral
Copyright ⓒ 2015 LG Electronics. Inc. All right reserved.
Only for training and service purposes
IC103-*2
BR24G256FJ-3
NVRAM
A0
VCC
1
8
A1
WP
2
7
+3.3V_NORMAL
A2
SCL
3
6
GND
SDA
IC103
4
5
C107
AT24C256C-SSHL-T
0.1uF
16V
NVRAM_ROHM
Write Protection
A0
VCC
1
8
- Low
: Normal Operation
A1
WP
- High : Write Protection
2
7
AR105
A2
SCL
33
3
6
I2C_SCL5
GND
SDA
I2C_SDA5
4
5
NVRAM_ATMEL
+3.3V_NORMAL
BOOT MODE
"0 : EMMC
"1 : TEST MODE
BOOT_MODE
BOOT_MODE0
I2C
I2C_1 : AMP
I2C_2 : T-CON,L/DIMING
I2C_3 : MICOM
I2C_4 : S/Demod,T2/Demod, LNB
I2C_5 : NVRAM
I2C_6 : TUNER_MOPLL(T/C,ATV)
I2C_SDA1
I2C_SCL1
I2C_SDA_MICOM_SOC
I2C_SCL_MICOM_SOC
I2C_SDA2
I2C_SCL2
I2C_SDA4
I2C_SCL4
I2C_SDA5
I2C_SCL5
I2C_SDA6
I2C_SCL6
IC103-*1
M24256-BRMN6TP
+3.3V_NORMAL
E0
VCC
1
8
E1
WC
2
7
E2
SCL
3
6
R163
VSS
SDA
4
5
10K
OPT
NVRAM_ST
SOC_RESET
C104
0.1uF
16V
L/DIM0_VS
L/DIM0_SCLK
TCK0
TDI0
L/DIM0_MOSI
FORCED_JTAG_0
M_REMOTE_RX
M_REMOTE_TX
1/16W
33
AR100
I2C_SCL_MICOM_SOC
I2C_SDA_MICOM_SOC
I2C_SCL4
I2C_SDA4
I2C_SCL6
I2C_SDA6
R107
PWM_DIM2
R108
PWM_DIM
EMMC_CLK
EMMC_CMD
EMMC_RST
EMMC_DATA[0-7]
LOCAL DIMMING I2C CONTROL
+3.3V_NORMAL
P102
OPT
12507WS-04L
1
LED_SCL
2
LED_SDA
3
4
5
IC101
LG1311-C1
B23
AN9
XTAL_IN
XIN_MAIN
USB2_0_DP0
A23
AM9
XTAL_OUT
XO_MAIN
USB2_0_DM0
AN8
USB2_0_TXRTUNE
R169
AG21
1%
200
R171
PORES_N
H32
33
USB2_1_DP0
AJ18
J31
BOOT_MODE
BOOT_MODE
USB2_1_DM0
H33
USB2_1_TXRTUNE
AB8
1%
200
R172
PLLSET0
PLLSET0
AC8
N31
PLLSET1
PLLSET1
USB3_DP0
N32
USB3_DM0
AD8
P33
OPM0
OPM0
USB3_TXP0
AE8
P32
OPM1
USB3_TXM0
OPM1
M32
AR101
USB3_RXP0
33
Y7
M33
USB3_RXM0
L_VSOUT_LD/TRST0_N
Y6
P31
USB3_RESREF0
DIM0_SCLK/TMS0
W7
1%
200
R173
DIM1_SCLK/TCK0
W6
K33
USB3_DP1
DIM1_MOSI/TDI0
R178
33
W5
K32
USB3_DM1
DIM0_MOSI/TDO0
L32
USB3_TXP1
AG30
L31
USB3_TXM1
SPI_CS0
AG28
K31
SPI_SCLK0
USB3_RXP1
AG29
J32
SPI_DO0
USB3_RXM1
AH29
M31
USB3_RESREF1
SPI_DI0/TRST1_N
AJ27
1%
200
R174
SPI_CS1/TMS1
AH27
W28
HUB_PORT_OVER0
/USB_OCD1
SPI_SCLK1/TCK1
AG26
W29
HUB_VBUS_CTRL0
SPI_DO1/TDO1
AH26
SPI_DI1/TDI1
H28
EB_CS3
/USB_OCD2
OPT
R182
10K
AJ12
J30
EXT_INTR0
EB_CS2
R183
10K
AJ13
J28
EXT_INTR1
EB_CS1
/USB_OCD3
R184
10K
AH12
J29
EB_CS0
EXT_INTR2
R185
10K
AG12
EXT_INTR3
G30
EB_WE_N
AH23
F30
SOC_RX
UART0_RXD
EB_OE_N
AG22
H29
SOC_TX
UART0_TXD
EB_WAIT
AH7
G29
EB_BE_N1
UART1_RXD
EB_BE_N1
AJ7
G28
EB_BE_N0
UART1_TXD
EB_BE_N0
AG8
P28
UART1_RTS_N
CAM_CD1_N
AH8
P27
UART1_CTS_N
CAM_CD2_N
U28
CAM_CE1_N
AH11
R29
I2C_SCL1
SCL0
CAM_CE2_N
AG11
V27
I2C_SDA1
SDA0
CAM_IREQ_N
CAM_IREQ_N
AH9
T28
SCL1
CAM_RESET
AG9
T29
CAM_INPACK_N
SDA1
CAM_INPACK_N
AG10
R28
I2C_SCL2
SCL2
CAM_VCCEN_N
AJ9
U27
I2C_SDA2
CAM_WAIT_N
SDA2
CAM_WAIT_N
AH22
N29
SCL3
CAM_REG_N
AJ22
SDA3
AH10
I2C_SCL5
SCL4
AJ10
K30
EB_ADDR[0]
I2C_SDA5
SDA4
EB_ADDR0
AG23
E30
EB_ADDR[1]
SCL5
EB_ADDR1
AH24
EB_ADDR[2]
M30
SDA5
EB_ADDR2
N28
EB_ADDR[3]
EB_ADDR3
AC6
M28
EB_ADDR[4]
PWM0
EB_ADDR4
33
EB_ADDR[5]
AC7
M29
PWM1
EB_ADDR5
33
AD7
L29
EB_ADDR[6]
R179
PWM2
EB_ADDR6
10K
AB7
K29
EB_ADDR[7]
PWM_IN
EB_ADDR7
EB_ADDR[8]
K28
1/16W
EB_ADDR8
5%
L28
EB_ADDR[9]
EB_ADDR9
G32
D30
EB_ADDR[10]
EMMC_CLK
EB_ADDR10
G33
F29
EB_ADDR[11]
EMMC_CMD
EB_ADDR11
G31
C32
EB_ADDR[12]
EMMC_RESETN
EB_ADDR12
EMMC_DATA[7]
EB_ADDR[13]
D31
C33
EMMC_DATA7
EB_ADDR13
EMMC_DATA[6]
F33
C31
EB_ADDR[14]
EMMC_DATA6
EB_ADDR14
EMMC_DATA[5]
F32
B33
EMMC_DATA5
EB_ADDR15
EMMC_DATA[4]
E32
EMMC_DATA4
EMMC_DATA[3]
F31
EMMC_DATA3
EMMC_DATA[2]
D33
B32
EB_DATA[0]
EMMC_DATA2
EB_DATA0
EB_DATA[1]
EMMC_DATA[1]
D32
A32
EMMC_DATA1
EB_DATA1
EMMC_DATA[0]
E31
B31
EB_DATA[2]
EMMC_DATA0
EB_DATA2
EB_DATA[3]
A31
EB_DATA3
A30
EB_DATA[4]
EB_DATA4
B30
EB_DATA[5]
EB_DATA5
EB_DATA[6]
C30
EB_DATA6
C29
EB_DATA[7]
EB_DATA7
Jtag-0 I/F
+3.3V_NORMAL
P103
12505WS-10A00
JTAG_CPU
1
L/DIM0_VS (TRST0_N)
2
TDI0
3
L/DIM0_MOSI(TDO0)
4
L/DIM0_SCLK (TMS0)
5
TCK0
6
SOC_RESET
7
FORCED_JTAG_0
8
9
10
11
MID_LG1311
M14 Symbol A
PAGE 1
WIFI_DP
WIFI_DM
USB_DP3
USB_DM3
USB_DP1
USB_DM1
USB_DP2
USB_DM2
USB_CTL1
USB_CTL2
USB_CTL3
TP104
EB_WE_N
EB_WE_N
+5V_NORMAL
EB_OE_N
EB_OE_N
TP105
TP106
EB_BE_N1
EB_BE_N0
TP107
CAM_CD1_N
TP108
CAM_CD1_N
CAM_CD2_N
TP109
CAM_CD2_N
TP110
/PCM_CE1
/PCM_CE1
/PCM_CE2
/PCM_CE2
TP111
TP112
CAM_IREQ_N
PCM_RESET
PCM_RESET
TP113
CAM_INPACK_N
TP114
TP115
PCM_5V_CTL
PCM_5V_CTL
CAM_WAIT_N
TP116
CAM_REG_N
CAM_REG_N
TP117
EB_ADDR[0-14]
TP102
EB_ADDR[0-14]
EB_DATA[0-7]
EB_DATA[0-7]
TP103
2013.04.04
1
31
LGE Internal Use Only
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