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Pentek 4284 Operating Manual

Tms320c40 digital signal processor mix baseboard for vmebus systems
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Pentek 4284 Operating Manual

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Summary of Contents for Pentek 4284

  • Page 1 Artisan Technology Group is your source for quality new and certified-used/pre-owned equipment SERVICE CENTER REPAIRS WE BUY USED EQUIPMENT • FAST SHIPPING AND DELIVERY Experienced engineers and technicians on staff Sell your excess, underutilized, and idle used equipment at our full-service, in-house repair center We also offer credit for buy-backs and trade-ins •...
  • Page 2 P e n t ek M o d el 4 2 8 4 O p e ra t in g M a n u a l P ag e 1 OPERATING MANUAL MODEL 4284 TMS320C40 Digital Signal Processor MIX Baseboard for VMEbus Systems 姱∑§™g[Ö±¢i...
  • Page 3 The obligation of Pentek arising from a warranty claim shall be limited to repairing or at its option, replacing without charge, any product which in Pentek’s sole opinion proves to be defective within the scope of the warranty.
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  • Page 10 Chapter 1: Overview General Description The Model 4284 MIX Baseboard for VMEbus systems is based on the Texas Instruments TMS320C40 Floating Point Digital Signal Processor. The 4284’s ‘C40 acts as both a VMEbus Master and a MIX bus Master. It serves as a powerful 40 or 50 MFlop Digital Signal Processor, as well as a complete DMA controller.
  • Page 11 Flash EEPROM Option The Model 4284 may optionally be equipped with a 128 kByte (Option 002) or 512 kByte (Option 003) in−circuit programmable Flash EEPROM. The Flash EEPROM is mapped as a 'C40 Local Bus resource, and code programmed into it may be executed at boot time.
  • Page 12 Pe nt e k Mo del 4284 Oper ating Manual P age 11 Software Development Support (continued) Macro The assembler translates assembly language source code into machine language object files in common object file format (COFF). The linker section Assembler/ Linker combines the COFF object files into an executable object module.
  • Page 13 The VME Subsystem Bus (VSB) is a secondary bus utilizing the outer rows of pins (rows A and C) on the VME P2 connector, which are unused in the standard VMEbus implementation. The Model 4284 operates as a VSB master and interrupt handler using the VSB1400A/B chip set from PLX Technologies.
  • Page 14 Pe nt e k Mo del 4284 Oper ating Manual P age 13 1.12 Specifications Processor Type: Texas Instruments TMS320C40 Clock Speed Standard: 40 MHz Option 015: 50 MHz Address Bus: 32 Bits Data Bus: 32 Bits Dual−Access DRAM Size...
  • Page 15 Page 1 4 Pe n te k Mo del 4284 Ope rat ing Manual 1.12 Specifications (continued) Flash EEPROM (optional) Size Option 002: 128 kBytes Option 003: 512 kBytes ‘C40 Access: Memory mapped on Local Bus, 1 wait state VMEbus Compliance Bus Master: D32 A32 I(1−7) IH(1−7)
  • Page 16 2−1, below, shows the pin numbering for double−row jumper blocks used in the Model 4284. Pin 1 of the jumper blocks is indicated by the line extending from the box that surrounds the header. All of the jumper blocks on the 4284 are right−angle head−...
  • Page 17 Page 1 6 Pe n te k Mo del 4284 Ope rat ing Manual Figure 2−2: Model 4284 Circuit Board Showing Jumper Block Locations, Option −012 (VSB) shown. Rev.: F.2 Artisan Technology Group - Quality Instrumentation ... Guaranteed | (888) 88-SOURCE | www.artisantg.com...
  • Page 18 JB6. If there is more than one Model 4284 in a card cage, these jumpers can be set to uniquely configure the addresses for each board. The address set by this jumper block is referred to as the A16_base address.
  • Page 19 (4 MByte) DRAM size, only four A24 base addresses (0x00 0000, 0x40 0000, 0x80 0000 and 0xC0 0000) are valid. If you have 16 Mbytes of DRAM in your Model 4284 (Option 009), and are restricted to the use of A24 address space (i. e., your card cage or cage con−...
  • Page 20 2−3, below, tells which of JB7's jumper positions corresponds to which address bit, and summarizes the settings of the DRAM window size jumper block. Table 2−3: Model 4284 − VMEbus DRAM Window Size − Jumper Block JB7 DRAM Pins 7 − 8 Pins 5 −...
  • Page 21 The Base Address used by VMEbus Masters when accessing the DRAM on the Model 4284 is determined by the settings of jumper blocks SW1 and SW2. SW2 sets the upper four bits (A20 − A23) of the A24 Base address. The upper eight bits of the A32 base address (A24 −...
  • Page 22 Table 2−8, below, lists the bits and weights set by jumper block SW1, which set the A32 base address for the 4284’s DRAM. All jumpers are installed on this block at the factory, configuring it for an A32 base address of 0x0000 0000.
  • Page 23 Another important point to keep in mind is that, in A32 space as well as in A24 space, the Model 4284’s DRAM MUST be mapped on an address boundary that is a multiple of the memory size (see the first paragraph Section 2.4.2,...
  • Page 24 This is accomplished by placing shorting jumpers between pins 2 & 3 of JB14, JB15, and JB16 on the Model 4284’s VSB Mezzanine board. If you would rather have another device in your card cage handle VSBus arbitration, then the Model 4284’s VSB arbiter functions should be diabled.
  • Page 25 Pe n te k Mo del 4284 Ope rat ing Manual Bus Request and Bus Grant Jumpers In the Model 4284, jumper blocks JB8, JB9 and JB10 are used for the selection of the device’s VME Bus Request level, and to receive and pass on Bus Grant signals. The sections below describe the functions of these blocks.
  • Page 26 Bus Grant Jumpers (continued) If the 4284 receives a Bus Grant In signal on the appropriate level, but it did not request the bus, VMEbus Master Interface will generate a Bus Grant Out signal, which is delivered to the even numbered pins (2, 4, 6 and 8) on jumper block JB10.
  • Page 27 Pe n te k Mo del 4284 Ope rat ing Manual Slot 1 System Controller Jumpers The 4284 can be configured as a VME slot 1 System Controller by placing jumpers in certain locations. A VMEbus System Controller drives the System Clock and System Reset lines, and performs arbitration when the bus is requested by more than one mas−...
  • Page 28 Model 4284 is not the slot 1 VME System Controller. If the Model 4284 is the slot 1 VME System Controller, and you do not want the 4284’s internally generated System Reset signal to reset the ‘C40, remove the jumper between pins 1 and 2 of jumper block JB11.
  • Page 29 ‘C40 Boot Code Address − Jumper Block JB4 The address of the code you want to use to boot the ‘C40 processor on your 4284 is par− tially determined by the setting of this jumper block. When the ‘C40 is reset, it can jump to one of four addresses, called Reset Vectors.
  • Page 30 ROM. However, you would then need to plant your own reset vector in a region of memory that is not installed on the 4284. (The essential point of all the above is . . . don't install the jumper on JB3 − instead, fetch the reset vector from the 'C40's ROM.)
  • Page 31 Page 3 0 Pe n te k Mo del 4284 Ope rat ing Manual 2.12 The Model 4284 Front Panel Available to the user on the front panel of the Model 4284 are the six buffered Comm Ports from the ‘C40, a JTAG connector for the Texas Instruments XDS−510...
  • Page 32 Pe nt e k Mo del 4284 Oper ating Manual P age 31 2.12 The Model 4284 Front Panel (continued) 2.12.1 Comm Port Connectors (continued) Figure 2−4: Comm Port Cable All twelve signal lines on the Comm Ports are equipped with a series 24τ...
  • Page 33 2.12.3 Serial Port Connector Although there is no UART on the Model 4284, the ‘C40 can synthesize asynchronous serial communications in software using its TCLK0 and TCLK1 I/O pins. These pins may be brought to the front panel directly or...
  • Page 34 4.3.3.2. 2.12.5 LED Indicator The LED on the front panel of the Model 4284 is driven by bit 6 of the ‘C40 VMEbus Modifier Register at ‘C40 address 0x9000 0000 (See Section 3.8 more details about this register). Writing a ‘1’ to this bit turns the LED on, and writing a ‘0’...
  • Page 35 EPROM. If no problems are encountered during this procedure, the LED on the 4284's front panel blinks about five times a second (the 'C40's Timer 0 is used as a counter). If the factory boot code was executed and the LED only blinks approximately once per sec−...
  • Page 36 Chapter 3: Memory Maps and Register Descriptions TMS320C40 Local Bus Memory Map The Model 4284’s TMS320C40 has two 32−bit data buses, called the Local and Global busses. The map for the resources assigned to Local Memory, as seen by the ‘C40 pro−...
  • Page 37 0x0010 00FF ‘C40 MIX Bus Control Register − Read/Write at 0x1000 0000 This 16−bit register is the means by which the ‘C40 on the Model 4284 monitors and controls the activities of the expansion modules on the MIX bus. Table 3−3, below,...
  • Page 38 − Bits D3 − D5 During a MIX bus reset (when the MXRST line, D15 of this register, is high), a MIX baseboard (e. g., the Model 4284) determines how many expansion modules are present in its MIX stack by reading the states of these three bits.
  • Page 39 (2) X = no byte, m = most significant byte, n = next more significant byte, k = next less significant byte, l = least significant byte (3) For Pentek MIX modules, use the 32−bit single cycle setting, which is the default. 3.2.4 MIX Bus Status Bits −...
  • Page 40 (201) 818−5900 for the latest list of MIX modules supporting Turbo−MIX. Turbo−MIX mode is enabled on 50 MHz 4284 boards by setting bit D14 to the ‘1’ state. When this bit is cleared to the ‘0’ state, Turbo−MIX mode is disabled, and normal MIX bus timing specifications are met.
  • Page 41 (i. e., the module in MIX slot 1 generates MXINT1, etc.). Table 3−5: Model 4284 − ‘C40 Interrupt Status and Control Register − R/W @ 0x1000 0002 Bit #...
  • Page 42 Pe nt e k Mo del 4284 Oper ating Manual P age 41 ‘C40 Interrupt Status and Control Register (continued) Table 3−6: Model 4284 − ‘C40 Interrupt Routing Register − R/W @ 0x1000 0003 Bit # Bit Name TimeOutInt HostInt...
  • Page 43 Besides the Address Modifier and Transfer Select bits, the ‘C40 VMEbus Modifier Register contains bits to fire the VMEbus System Reset (if the 4284 is configured as a slot 1 System Controller), to lock the VMEbus and to control the front panel LED Indicator. There are also two VMEbus Page Address bits, and a status bit indicating that the ‘C40 has issued an inter−...
  • Page 44 VMEbus System Reset − Bit D0 This bit is used to fire a VME System Reset pulse, if the 4284 is configured as the slot 1 System Controller. While reading the description of this reset, on the following page, it may help to refer to Figure 3−1, below.
  • Page 45 LWORD (longword) bus line is also asserted. The TRSEL(3−0) bits determine the memory cycle operation of the Bus Mas− ter Interface of the Model 4284. This interface allows the unit to access the VMEbus for read, write, and interrupt acknowledge (IACK) cycles. Data transfers for reads and writes may be 8, 16, or 32−bits wide, thus supporting...
  • Page 46 Pe nt e k Mo del 4284 Oper ating Manual P age 45 The ‘C40 VMEbus Modifier Register (continued) 3.8.2 VMEbus Transfer Mode Select (continued) Table 3−9: Model 4284 − VMEbus Transfer Select (TRSEL) Bit Functions TRSEL BITS VMEbus ‘C40 Description Comments Strobes...
  • Page 47 3.8.4 LED Indicator Driver − Bit D6 The LED Indicator on the Model 4284’s front panel is turned on when this bit is in the ‘1’ state. To turn the LED off, clear this bit to the ‘0’ state. 3.8.5 ‘C40 Interrupt to VMEbus Status...
  • Page 48 User Defined All Others Reserved * − The Model 4284 can generate this AM code as a VMEbus Master, but does not respond to it as a Slave. † − The Model 4284 cannot master VMEbus block transfers. Rev.: F.2...
  • Page 49 Model 4284, these seven locations contain the IACK codes. These codes are actually the lower 3 bits of their addresses, i. e., the code at location 0xA000 0005 is 101 For example, if the 4284 is interrupted on level 5, it (after gaining bus control) asserts IACK and places 101 on the 3 lowest VME address bus lines.
  • Page 50 The Model 4284 responds as a VMEbus slave device for accesses to its Dual−Ported DRAM and to the IACK Vector and Host Control Registers. The IACK Vector that the 4284 responds with when participating in an IACK cycle may be programmed by the host computer. The vector is contained in the IACK Vector Register (at the A16_base address), which is mapped into A16 space.
  • Page 51 VMEbus Reset Vector Select − Bits D2 and D3 Bits D3 and D2 of the Model 4284’s VMEbus Host Control Regis− ter drive the RESETLOC(1,0) pins on the ‘C40 Processor. These pins tell the processor where to look to find the address of the initialization code to be run when the RESET input is driven low.
  • Page 52 The Model 4284 operates as a VSB master and interrupt handler using the VSB1400A/B chip set from PLX Technologies. The 4284 cannot be accessed as a VSB slave, nor can it issue VSB interrupts. Mastership of the VSBus by an external VME device accessing the 4284 as a slave is not supported.
  • Page 53 Page 5 2 Pe n te k Mo del 4284 Ope rat ing Manual 3.12 Model 4284 VSB Interface (Option 012) (continued) 3.12.1 The VSB Control Register (continued) Table 3−14: Model 4284, Option 012 − VSB Control Register − R/W @ ‘C40 Global Address 0x9000 0001...
  • Page 54 When the Indivisible−Access cycle is complete, this bit should be set to logic ‘1’ state to allow other processors access to the VSBus. If the Model 4284 is the only VSBus master in your system, this bit may be left in the default logic ‘0’ state.
  • Page 55 Page 5 4 Pe n te k Mo del 4284 Ope rat ing Manual 3.12 Model 4284 VSB Interface (Option 012) (continued) 3.12.1 The VSB Control Register (continued) 3.12.1.6 VSB Address Space Select Bits − D11 (Space_1) & D10 (Space 0) These two bits drive the Space1 and Space 0 Address Lines on the VSB Backplane, through inverting buffers.
  • Page 56 (VSA_0)) in this register, and the ‘C40 Global Address bus map into VSB Address bits. Table 3−17: Model 4284, Option 012 − VSB Address Bit Mapping V S B A d d r e s s / D a t a B i t s VSBCR ’C 4 0...
  • Page 57 Page 5 6 Pe n te k Mo del 4284 Ope rat ing Manual T h is p ag e i s i n te nt io n a ll y b l a nk Rev.: F.2 Artisan Technology Group - Quality Instrumentation ... Guaranteed | (888) 88-SOURCE | www.artisantg.com...
  • Page 58 Resetting and Booting the Model 4284 There are three distinct paths by which the 'C40 processor on the Model 4284 may be reset. These are the Power−up/Push−button Reset, the VME System Reset, and the Host Control Reset.
  • Page 59 Page 5 8 Pe n te k Mo del 4284 Ope rat ing Manual Figure 4−1: Model 4284 − Detailed Block Diagram Rev.: F.2 Artisan Technology Group - Quality Instrumentation ... Guaranteed | (888) 88-SOURCE | www.artisantg.com...
  • Page 60 JB4 (installed jumper = 0, absent jumper = 1) to the IIOF pins. The factory setting of JB4 sets the jump location to 0x0030 0000, which is the beginning of the 4284's EPROM. The code provided in the EPROM, after it is boot loaded, initializes some of the 'C40's internal registers, among them the Local and Global Bus Interface Control Registers.
  • Page 61 Pe n te k Mo del 4284 Ope rat ing Manual Resetting and Booting the Model 4284 (continued) 4.2.1 The Power−Up or Push−Button Reset (continued) Table 4−3: Model 4284 − Register States After Boot from Factory EPROM Register Address Condition Comments IACK Vector Register A16_base+0x00...
  • Page 62 EPROM boot, the LED on the 4284’s front panel will blink about five times a second (the blink rate is dependent upon the speed of the processor −...
  • Page 63 Host Control Register is not cleared, so its contents will be unchanged by this reset. If the 4284 is to be your Slot 1 VME System Controller, it must be configured to drive the VME System Reset line by installing a jumper between pins 1 and 2 of Jumper Block JB8.
  • Page 64 EPROM boot. See Section 4.2.1, above, for further details To boot the 4284 from a Comm Port, set the jumpers on JB4 as shown in the top line of Table 4−1, install the 4284 in the VME card cage, and apply power.
  • Page 65 Flash EEPROM Operations (continued) In most cases, when this option is included on the Model 4284, the user's goal is to have the processor boot load the code in the Flash EEPROM immediately upon power−up or warm reset. The procedures involved in accomplishing that goal will involve all of the operations one might want to perform using the Flash memory.
  • Page 66 4284’s Flash EEPROM. The Flash EEPROM on the Model 4284 resides on the ‘C40's Local bus, and can be accessesed ONLY by the ‘C40. Therefore, the HEX file must be written into the 4284’s shared memory area (i.
  • Page 67 (see Figure 4−3, below), and then push the Reset button. When the 4284 is reset in this manner, the LED indicator will remain lit until the Flash EEPROM is completely erased, and then blink normally. Figure 4−3: TCLK I/O Connector 4.3.3.2...
  • Page 68 3) Write a '0' to the Host Read y Flag L ocation, DRAM_ base+0x000 0 081 0. 4) Set the Host Interrupt Bit in the 4284's Host Control Register to the '1' state, by writing a '2' to A16_base+0x0004. 5) The firmware will now begin to erase the Flash EEPROM sector at the address given in step (2), on the previous page.
  • Page 69 Length location, DRAM_base+0x0000 080C. 5) Write a ‘0’ to the Host Ready Flag Location, DRAM_base+0x0810. 6) Set the Host Interrupt Bit in the 4284’s Host Control Register to the ‘1’ state, by writing a ‘2’ to A16_base+0x0004. 7) The firmware will now begin to move 32−bit longwords from the DRAM address given in step (2) of this procedure to the Flash EEPROM sector at the address given in step (3) (see previous page).
  • Page 70 2) Write the Flash EEPROM address of the code you wish to boot to the Flash Boot Address location, DRAM_base+0x0804. 3) Set the Host Interrupt Bit in the 4284's Host Control Register to the '1' state, by writing a '2' to A16_base+0x04.
  • Page 71 Pe n te k Mo del 4284 Ope rat ing Manual Downloading Programs to the Model 4284 ‘C40 programs in Common Object File Format (COFF) can be transferred into the 4284’s shared DRAM over the VMEbus. One recommended method for achieving this file transfer is via Pentek’s SwiftNet Communications Protocols.
  • Page 72 P age 71 Handling Interrupts on the Model 4284 Interrupts targeted for the four interrupt inputs of the ‘C40 processor on the Model 4284 can come from any three of the seven VMEbus IRQs , from the three MIX module inter−...
  • Page 73 VME_IRQ_C is routed to the ‘C40 by means of the third bit in each byte of the register (D2, D10, D18, and D26). By default, the only interrupt that this reg− ister enables (when the 4284 is booted with the code Pentek supplies in the EPROM), is the Host Control Interrupt, which gets connected to INT_1.
  • Page 74 P age 73 Handling Interrupts on the Model 4284 (continued) 4.5.1 Handling VMEbus Interrupts (continued) Table 4−8: Model 4284 − ‘C40 Interrupt Status and Control Register − R/W @ 0x1000 0002 Bit # Bit Name TimeOutInt HosInt MXINT2 MXINT1 MXINT0 VME_IRQ_C VME_IRQ_B VME_IRQ_A 4.5.1.1...
  • Page 75 ‘C40 INT_0. D14 routes this interrupt to INT_1, D22 sends it to INT_2, and a ‘1’ in D30 will pass this interrupt to INT_3. The Pentek boot code in the EPROM supplied with the 4284 connects the Host interrupt to INT_1.
  • Page 76 The Model 4284 can issue interrupts over the VMEbus, and participate as an interrupter in the VME IACK cycle. As a MIX bus Baseboard, the 4284 cannot use the MIX bus interrupt lines to interrupt co−processor modules which may be connected to its MIX bus, but can interrupt these devices using the “mailbox”...
  • Page 77 User Defined All Others Reserved * − The Model 4284 can generate this AM code as a VMEbus Master, but does not respond to it as a Slave. † − The Model 4284 cannot master VMEbus block transfers. Rev.: F.2...
  • Page 78 Page Address Bits (D14 and D15) of the ‘C40 VMEbus Modifier Register, as described in Section 3.8.7. Table 4−10: Model 4284 − VMEbus Transfer Select (TRSEL) Bit Functions TRSEL BITS VMEbus ‘C40...
  • Page 79 VMEbus memory page. When a memory cycle is initiated by the ‘C40, the Bus Master Interface on the Model 4284 requests bus ownership by asserting one of the Bus Request lines (BREQ0 through BREQ3). The bus request level is determined by the set−...
  • Page 80 VSB block transfers on the Model 4284 are enabled by bit D15 in the VSB Control Register (‘C40 Global Address 0x9000 0001).
  • Page 81 Mastering MIX transactions from the 4284 is simply a matter of reading from or writing to the proper area of the ‘C40 MIX bus window. The 4284 also supports mastering of the MIX bus by processor modules in the MIX stack, called Upper MIX Bus Masters, or UMBMs.
  • Page 82 Using the Model 4284's Memories (continued) The ‘C40 processor on the 4284 was the master device for all data tranactions. In block repeat mode, the data transfers are mastered by the ‘C40’s CPU, in a loop using the RPTB instruction. See Example 12−10 (Use of Block Repeat to Find a Maximum or a Minimum), in Section 12.2.5 (Repeat Modes) of the Texas Instruments TMS320C4x...
  • Page 83 4.10 Using the Model 4284's Memories (continued) Table 4−11: Model 4284 − Transfer Times for One Longword (Block Repeat Mode) − 50 MHz ‘C40 To: è ‘C40 Int. RAM Local SRAM Global SRAM Global DRAM* MIX (no wait) From:ê MIX (wait) VMEbus* ‘C40 Int.
  • Page 84 4.10 Using the Model 4284's Memories (continued) Table 4−14: Model 4284 − Transfer Times for One Longword (Block Repeat Mode) − 40 MHz ‘C40 To: è ‘C40 Int. RAM Local SRAM Global SRAM Global DRAM* MIX (no wait) From:ê MIX (wait) VMEbus* ‘C40 Int.
  • Page 85 Page 8 4 Pe n te k Mo del 4284 Ope rat ing Manual T h is p ag e i s i n te nt io n a ll y b l a nk Rev.: F.2 Artisan Technology Group - Quality Instrumentation ... Guaranteed | (888) 88-SOURCE | www.artisantg.com...
  • Page 86 å§ ± ∑§™ [ â≤£§Ø[ omso[ ã≥§ µ †∑®± ¶[ ↠± ∏† Ø å † ¶§ [|hl |≥≥§±£®Ω[|u[åµ≤¶µ†∞∞®±¶[ÅΩ†∞≥ا∂ è§∑∑®±¶[∏≥[∑ߧ[â≤£§Ø[omso êߧ[•≤ØØ≤∫®±¶[~[≥µ≤¶µ†∞[∏∂§∂[†[}®∑n[â≤£§Ø[qkn[å~j|êhíâÅ°∏∂[†£†≥∑≤µg[®±[∑ߧ[èØ≤∑[l[ èæ∂∑§∞[~≤±∑µ≤Øاµ[≥≤∂®∑®≤±g[†∂[∑ߧ[íâÅ°∏∂[â†∂∑§µ[∑≤[¢≤±∑µ≤Ø[∑ߧ[®±®∑®†Ø[∂§∑∏≥[≤•[†[ â≤£§Ø[omsoi[[êß®∂[¢≤£§[†Ø∂≤[§Ω§µ¢®∂§∂[∑ߧ[•®µ∞∫†µ§[à≤≤™[†±£[è§∑[•∏±¢∑®≤±∂i #include "io84.h" #include "def84v.h" #include "iocom.h" extern unsigned int a16_addr; extern int a24_addr; extern int page; extern int access_mode; extern int processor;...
  • Page 87 (tout != 0) look84_func = peek_long (LOOK); set84_func = peek_long (SET); ready = peek_long (RDY); printf ("4284 look = %lx\n",look84_func); printf ("4284 set = %lx\n",set84_func); printf ("4284 rdy = %lx\n",ready); printf ("4284/C40 ready\n"); é§πiu[[Çim Artisan Technology Group - Quality Instrumentation ... Guaranteed | (888) 88-SOURCE | www.artisantg.com...
  • Page 88 å§ ± ∑§™ [ â≤£§Ø[ omso[ ã≥§ µ †∑®± ¶[ ↠± ∏† Ø å † ¶§ [|hn è§∑∑®±¶[∏≥[∑ߧ[â≤£§Ø[omso[ c¢≤±∑®±∏§£d else ready = peek_long (RDY); printf ("4284 rdy = %lx\n",ready); printf ("4284/C40 not here !!!!!!!!!!\n"); getch (); run84 (entry_point) unsigned long entry_point; unsigned hi,low;...
  • Page 89 冶§ [ |ho 姱∑§™ [â ≤ £§Ø[omso[ã≥§µ† ∑® ±¶[↠±∏† Ø è§∑∑®±¶[∏≥[∑ߧ[â≤£§Ø[omso[ c¢≤±∑®±∏§£d unsigned long look84 (unsigned long addr) unsigned long data; outportb (0x20d,A24); poke_long (CMD,look84_func); poke_long (ARG1,addr); poke_long (RDY,0); /* Zero Ready Flag */ outportb (0x20d,A16); /* Short Address AM Code */ poke (SEG,CONTROL_REG + a16_addr,INT84_A);...
  • Page 90 å§ ± ∑§™ [ â≤£§Ø[ omso[ ã≥§ µ †∑®± ¶[ ↠± ∏† Ø å † ¶§ [|hp è§∑∑®±¶[∏≥[∑ߧ[â≤£§Ø[omso[ c¢≤±∑®±∏§£d if (kbhit()!=0) tout=0; break; set84 (0x100042 + comm_offset,data); printf ("%08lx ",data); ++counter; if (counter == 8) counter = 0; printf ("\n"); /****************************** io84.h *******************************/ void init84 (void);...
  • Page 91 冶§ [ |hq 姱∑§™ [â ≤ £§Ø[omso[ã≥§µ† ∑® ±¶[↠±∏† Ø è§∑∑®±¶[∏≥[∑ߧ[â≤£§Ø[omso[ c¢≤±∑®±∏§£d /* C40 Handshake LOOK / SET Pointers */ #define CMD 0x800 /* Command - Jump Address */ #define ARG1 0x804 /* Argument #1 L/S Address */ #define ARG2 0x808 /* Argument #2 Set Data */ #define ARG3...
  • Page 92 å§ ± ∑§™ [ â≤£§Ø[ omso[ ã≥§ µ †∑®± ¶[ ↠± ∏† Ø å † ¶§ [|hr è§∑∑®±¶[∏≥[∑ߧ[â≤£§Ø[omso[ c¢≤±∑®±∏§£d /****************************** iocom.h ******************************/ #define SEG 0xd000 /* segment correponding to VMEbus */ void set_processor_page (unsigned int proc); void set_page84 (int proc); void set_page70 (int proc);...
  • Page 93 冶§ [ |hs 姱∑§™ [â ≤ £§Ø[omso[ã≥§µ† ∑® ±¶[↠±∏† Ø Ö∂∂∏®±¶[†±£[ц±£Ø®±¶[íâÅ°∏∂[Ö±∑§µµ∏≥∑∂[ c¢≤±∑®±∏§£d for(i=0; i<0x100; i++) outportb (0x20d,A16); /* Short Address AM Code */ poke (SEG,VME_IACK_REG + a16_addr,i); /* Set IACK vector and Clr int */ stat = peek (SEG,VME_IACK_REG + a16_addr); /* Read IACK vector */ if ((stat &...
  • Page 94 å§ ± ∑§™ [ â≤£§Ø[ omso[ ã≥§ µ †∑®± ¶[ ↠± ∏† Ø å † ¶§ [|ht Ö∂∂∏®±¶[†±£[ц±£Ø®±¶[íâÅ°∏∂[Ö±∑§µµ∏≥∑∂[ c¢≤±∑®±∏§£d printf ("\n\nTesting IRQ Handler - %x\n",irq_level); err_flag = 0; outportb (0x20d,A16); /* Short Address AM Code */ set84 (0x10000002, (unsigned long)(irq_level << 8)); lstat = look84(0x10000002);...
  • Page 95 冶§ [ |hl k 姱 ∑§™ [â ≤ £ §Ø[om so[ã≥§µ† ∑®±¶[↠±∏† Ø Ö∂∂∏®±¶[†±£[ц±£Ø®±¶[íâÅ°∏∂[Ö±∑§µµ∏≥∑∂[ c¢≤±∑®±∏§£d poke (SEG,CONTROL_REG + a16_addr,1); /* C40 reset*/ poke (SEG,CONTROL_REG + a16_addr,0); test_timeout84 () int r0, r1, count=100, i, err_flag=0; long lstat; system ("cls"); printf ("\n4284 Bus timeout test"); set84 (0x90000000,0x2d00);...
  • Page 96 /* VMEbus address modifiers */ #define A16 0x2D #define A24 0x3D #define A32 0x0D /* 4265 VME base address and 4284 VME access constants #define A24BASE 0x800000/4 /* 4265 base address */ #define A24ACCESS 0xB0000000 /*4284 VME Master Access region */...
  • Page 97 /* Initialize 4284 */ init_ptrs (); init_84 (); /* call initialization functions specific to your VMEbus board here */ void init_ptrs(void) /* Function to create 4284 pointers */ /* 4284 pointers */ datain = (vuint *)0x80000300; dataout = (vuint *)0x80000301;...
  • Page 98 å§ ± ∑§™ [ â≤£§Ø[ omso[ ã≥§ µ †∑®± ¶[ ↠± ∏† Ø å† ¶ §[|hl n ë∂®±¶[∑ߧ[íâÅ°∏∂[â†∂∑§µ[Ö±∑§µ•†¢§[†±£[~≤∞∞[å≤µ∑∂[ c¢≤±∑®±∏§£d void init_84(void) /* Function to initialize 4284 pointers and buffers */ uint i, j; *datain = 0; *dataout = 0;...
  • Page 99 冶§ [ |hl o 姱 ∑§™ [â ≤ £ §Ø[om so[ã≥§µ† ∑®±¶[↠±∏† Ø ë∂®±¶[∑ߧ[íâÅ°∏∂[â†∂∑§µ[Ö±∑§µ•†¢§[†±£[~≤∞∞[å≤µ∑∂[ c¢≤±∑®±∏§£d if (((*comm_port_address) & 0x1e00u) != 0) *data = *(comm_port_address + 1); if (((*data) & 0xff) != 0x60) trigger (); else trigger (); return (1); else return (0);...
  • Page 100 å§ ± ∑§™ [ â≤£§Ø[ omso[ ã≥§ µ †∑®± ¶[ ↠± ∏† Ø å† ¶ §[|hl p ì≤µ™®±¶[∫®∑ß[âÖî[â≤£∏ا∂[†±£[âÖî[Ö±∑§µµ∏≥∑∂ êߧ[•≤ØØ≤∫®±¶[~[≥µ≤¶µ†∞[∏∂§∂[∑ߧ[omso[∑≤[¢≤±∑µ≤Ø[∑ߧ[≤≥§µ†∑®≤±[≤•[†[â≤£§Ø[omon[£∏†Ø[ ¢ß†±±§Ø[|jÄhÄj|[~≤±π§µ∑§µ[âÖî[∞≤£∏اi[[|[∂∫®∑¢ß[†∑[∑ߧ[∑≤≥[≤•[∑ߧ[≥µ≤¶µ†∞[†ØØ≤∫∂[ ∑ߧ[£†∑†[®±∑§µ•†¢§[°§∑∫§§±[∑ߧ[∑∫≤[£§π®¢§∂[∑≤[≤¢¢∏µ[π®†[§®∑ߧµ[≥≤ØØ®±¶[≤µ[®±∑§µµ∏≥∑i #define POLLING /* Set these variables to opposite states */ #define INTERRUPTS 1 #define MOD0 0x20000000 /* Address to access MIX Position 0 */ #define MOD1 0x24000000 /* Address to access MIX Position 1 */...
  • Page 101 冶§ [ |hl q 姱 ∑§™ [â ≤ £ §Ø[om so[ã≥§µ† ∑®±¶[↠±∏† Ø ì≤µ™®±¶[∫®∑ß[âÖî[â≤£∏ا∂[†±£[âÖî[Ö±∑§µµ∏≥∑∂[ c¢≤±∑®±∏§£d /* Initialize Pointers to 4243 registers */ StatusControl = (unsigned int *) (MOD | 0x0); CtcMode = (unsigned int *) (MOD | 0x80); = (unsigned int *) (MOD | 0x83); = (unsigned int *) (MOD | 0x82);...
  • Page 102 å§ ± ∑§™ [ â≤£§Ø[ omso[ ã≥§ µ †∑®± ¶[ ↠± ∏† Ø å† ¶ §[|hl r ë∂®±¶[ê∏µ°≤hâ®Ω êߧ[•≤ØØ≤∫®±¶[~[≥µ≤¶µ†∞[•µ†¶∞§±∑[£§∞≤±∂∑µ†∑§∂[ß≤∫[≤±§[∫≤∏Ø£[∂§∑[∏≥[†[pkhâÑø[ â≤£§Ø[omso[}†∂§°≤†µ£[∑≤[¢≤±£∏¢∑[ê∏µ°≤hâÖî[∑µ†±∂†¢∑®≤±∂[∫®∑ß[†[âÖî[â≤£∏ا[cê∏µ°≤h âÖî[∞≤£§[®∂[±≤∑[∂∏≥≥≤µ∑§£[≤±[omsob∂[∫®∑ß[ok[âÑø[≥µ≤¢§∂∂≤µ∂id[[êߧ[ê∏µ°≤hâÖî[°®∑[®∂[ ∂§∑[®±[∑ߧ[b~okb∂[âÖî[}∏∂[~≤±∑µ≤Ø[駶®∂∑§µg[†±£[†[∫≤µ£[®∂[∫µ®∑∑§±[∑≤[∑ߧ[à≤¢†Ø[â§∞≤µæ[ Ö±∑§µ•†¢§[~≤±∑µ≤Ø[駶®∂∑§µ[c®±∑§µ±†Ø[∑≤[∑ߧ[b~okd[∑߆∑[£§∑§µ∞®±§∂[∑ߧ[µ†∑§[†∑[∫ß®¢ß[âÖî[ †¢¢§∂∂§∂[¢†±[≤¢¢∏µi Ö∑[®∂[®∞≥≤µ∑†±∑[∑≤[°§[†∫†µ§[∑߆∑[•≤µ[ê∏µ°≤hâÖî[∞≤£§[∑≤[°§[§±†°Ø§£g[∑ߧ[≥µ≤¶µ†∞[¢≤£§[ âëèê[µ§∂®£§[®±[ÉØ≤°†Ø[â§∞≤µæ[≤µ[®±[Ö±∑§µ±†Ø[é|âi[[êß®∂[®∂[°§¢†∏∂§[∑ߧ[âÖî[°∏∂[∑µ†±h ¢§®π§µ∂[†µ§[†Ø∫†æ∂[§±†°Ø§£[®±[∑ß®∂[∞≤£§g[∞†™®±¶[∑ߧ[b~ok[∏±†°Ø§[∑≤[†¢¢§∂∂[®∑∂[à≤¢†Ø[ èé|âg[Ååéãâg[≤µ[∑ߧ[µ§¶®∂∑§µ∂[†∑[†££µ§∂∂§∂[kΩlkkk[kkkk[h[kΩlkkk[kkkoi unsigned int c40_reg_save c40_control = (unsigned int *) 0x100000u; c40_reg = (unsigned int *) 0x10000000u; /* NOTE: When Turbo-MIX mode is set, program code MUST reside in Global SRAM or 'C40 Internal RAM.
  • Page 103 /* TV pointer /**********************************************/ Ç≤µ[•∏µ∑ߧµ[®±•≤µ∞†∑®≤±[†°≤∏∑[∑ߧ[∏∂§[≤•[∑ß®∂[Ø®±™§µ[¢≤∞∞†±£[•®Ø§g[∂§§[觢∑®≤±[oinil[≤•[∑ß®∂[ ∞†±∏†Øi ѧΩ[Ǯا[à≤†£§µ[†±£[è∑†µ∑§µ /*********************************************************************/ 4284 Standalone HEX loader and Program Starter /*********************************************************************/ /* General: This program loads and executes a TMS320C40 Hex output file on a Pentek Model 4284 DSP Board. It also has the capability of...
  • Page 104 å§ ± ∑§™ [ â≤£§Ø[ omso[ ã≥§ µ †∑®± ¶[ ↠± ∏† Ø å† ¶ §[|hl t ѧΩ[Ǯا[à≤†£§µ[†±£[è∑†µ∑§µ[ c¢≤±∑®±∏§£d #include <ctype.h> #include <string.h> #include <stdio.h> #include <stdlib.h> #include <time.h> #include "def84.h" /*-------------------------------------------------------------------*/ /* LOADER DEFINITIONS /*-------------------------------------------------------------------*/ long load_hex_file(); void boot_global(); void boot_flash();...
  • Page 105 冶§ [ |hm k 姱 ∑§™ [â ≤ £ §Ø[om so[ã≥§µ† ∑®±¶[↠±∏† Ø Ñ§Ω[Ǯا[à≤†£§µ[†±£[è∑†µ∑§µ[c¢≤±∑®±∏§£d /*----------------------------------------------------------------*/ PROCESS COMMAND LINE ARGUMENTS /*----------------------------------------------------------------*/ for (i = 1; i < argc; ++i) char *argp = argv[i]; if (*argp == '-') while (*++argp) switch(*argp) case 'L': case 'l': load_only = 1;...
  • Page 106 å§ ± ∑§™ [ â≤£§Ø[ omso[ ã≥§ µ †∑®± ¶[ ↠± ∏† Ø å† ¶ §[|hm l ѧΩ[Ǯا[à≤†£§µ[†±£[è∑†µ∑§µ[ c¢≤±∑®±∏§£d case 'B': case 'b': sscanf(++argp,"%x",&a16_base); if (a16_base > 0xffff) printf ("\nInvalid a16 address selected!"); printf (" %x\n",a16_base); exit (0); printf ("a16 Base = %x\n",a16_base); break;...
  • Page 107 冶§ [ |hm m 姱 ∑§™ [â ≤ £ §Ø[om so[ã≥§µ† ∑®±¶[↠±∏† Ø Ñ§Ω[Ǯا[à≤†£§µ[†±£[è∑†µ∑§µ[ c¢≤±∑®±∏§£d if (!run_only && !erase_flash) /* Load program into Global Memory */ if (files == 0) printf ("\nEnter HEX file name -> "); scanf ("%s", file_name); strcat (file_name,".hex");...
  • Page 108 å§ ± ∑§™ [ â≤£§Ø[ omso[ ã≥§ µ †∑®± ¶[ ↠± ∏† Ø å† ¶ §[|hm n ѧΩ[Ǯا[à≤†£§µ[†±£[è∑†µ∑§µ[ c¢≤±∑®±∏§£d if (( fp = fopen(file_name, "rb" )) == NULL ) printf ( "Could not open file - %s ! ",file_name ); exit (0);...
  • Page 109 /* Skip over cksum and CR/LF */ fgets (string,80,fp); return (word_count); void boot_processor (a16_base) unsigned int a16_base; poke_word(CONTROL_REG + a16_base, RESET84_A); /* Reset 4284 */ poke_word(CONTROL_REG + a16_base, 0); /* Release 4284 */ void boot_global (a16_base, offset) unsigned int a16_base; unsigned long offset;...
  • Page 110 /* Read function table within 4284 memory to locate pointer to c40 loader function */ boot84_func = peek_long (FBOOT); printf ("boot 84 func = %lx\n", boot84_func); /* Load Boot function address as the command */ poke_long (CMD, boot84_func);...
  • Page 111 姱 ∑§™ [â ≤ £ §Ø[om so[ã≥§µ† ∑®±¶[↠±∏† Ø Ñ§Ω[Ǯا[à≤†£§µ[†±£[è∑†µ∑§µ[ c¢≤±∑®±∏§£d /* Read function table within 4284 memory to locate pointer to ‘C40 load flash memory function */ /* Load Program into Flash Memory */ func = peek_long (FLDW);...
  • Page 112 (0, 0xc33c3cc3L); poke_long (RDY,0); /* Clear out Command Complete Indicator */ poke_word (CONTROL_REG + a16_base, RESET84_A); /* Reset 4284 */ poke_word (CONTROL_REG + a16_base, 0); /* Wait for Command to Complete */ while (peek_long(RDY) != 1); /* Reset the boot override command */ poke_long (0, 0x0L);...
  • Page 113 冶§ [ |hm s 姱 ∑§™ [â ≤ £ §Ø[om so[ã≥§µ† ∑®±¶[↠±∏† Ø ë±®Ω[â†≥≥®±¶[Ǯا[ c¢≤±∑®±∏§£d /* map physical memory to virtual memory - NOTE: parameters in Init_Memory are NOT used in a virtual memory system. */ void setup(a16_base, dpr_base) unsigned int a16_base;...
  • Page 114 å§ ± ∑§™ [ â≤£§Ø[ omso[ ã≥§ µ †∑®± ¶[ ↠± ∏† Ø å† ¶ §[|hm t ë±®Ω[â†≥≥®±¶[Ǯا[c¢≤±∑®±∏§£d /* low level memory access routines */ void poke_long (Addr, Data) unsigned long Addr; unsigned long Data; unsigned int B1,B2,B3,B4; unsigned short *addrP, data; B2 = (unsigned int) (Data &...
  • Page 115 冶§ [ |hn k 姱 ∑§™ [â ≤ £ §Ø[om so[ã≥§µ† ∑®±¶[↠±∏† Ø ë±®Ω[â†≥≥®±¶[Ǯا[ c¢≤±∑®±∏§£d Status[12] = A16; *(unsigned short *) (Ctladdr + Addr ) = Data; Status[12] = A32; unsigned int peek_word (Addr) unsigned int Addr; unsigned int data; Status[12] = A16;...
  • Page 116 #define NULL 0 volatile unsigned int *timer0_address, *timer1_address, *c40_reg; volatile unsigned int clock, clockd2; unsigned char string[100]; static char header_a[] = "Pentek 4284/C40 Processor Ready"; static char tmsg[] = "Enter string to echo -->"; static char crlf[] = { 0xd,0xa,0x0 };...
  • Page 117 冶§ [ |hn m 姱 ∑§™ [â ≤ £ §Ø[om so[ã≥§µ† ∑®±¶[↠±∏† Ø |ilk ë∂®±¶[∑ߧ[ê~àá[讶±†Ø∂[•≤µ[觵®†Ø[Öjã[ c¢≤±∑®±∏§£d main() unsigned int i, op=1, ip=1, data; c40_reg = (unsigned int *) 0x340000u; init_uart (); prints (crlf); prints (header_a); prints (crlf); prints (crlf); while (1) prints (crlf);...
  • Page 118 å§ ± ∑§™ [ â≤£§Ø[ omso[ ã≥§ µ †∑®± ¶[ ↠± ∏† Ø å† ¶ §[|hn n |ilk ë∂®±¶[∑ߧ[ê~àá[讶±†Ø∂[•≤µ[觵®†Ø[Öjã[ c¢≤±∑®±∏§£d /* Look for end of start bit */ tmp = *timer0_address & 0x8u; } while (tmp == 0); /* Get timer value for use as clock */ clock = *(timer0_address+4)/2;...
  • Page 119 冶§ [ |hn o 姱 ∑§™ [â ≤ £ §Ø[om so[ã≥§µ† ∑®±¶[↠±∏† Ø |ilk ë∂®±¶[∑ߧ[ê~àá[讶±†Ø∂[•≤µ[觵®†Ø[Öjã[ c¢≤±∑®±∏§£d tmp = *timer1_address & 0x800u; } while (tmp != 0); /* Set stop bit */ *timer1_address = 0x3c6u; tmp = *timer1_address & 0x800u; } while (tmp == 0);...
  • Page 120 å§ ± ∑§™ [ â≤£§Ø[ omso[ ã≥§ µ †∑®± ¶[ ↠± ∏† Ø å† ¶ §[|hn p |ilk ë∂®±¶[∑ߧ[ê~àá[讶±†Ø∂[•≤µ[觵®†Ø[Öjã[ c¢≤±∑®±∏§£d /* Look for next low clock transition */ tmp = *timer0_address & 0x800u; } while (tmp != 0); /* Look for next high clock transition */ tmp = *timer0_address &...
  • Page 121 冶§ [ |hn q 姱 ∑§™ [â ≤ £ §Ø[om so[ã≥§µ† ∑®±¶[↠±∏† Ø |ilk ë∂®±¶[∑ߧ[ê~àá[讶±†Ø∂[•≤µ[觵®†Ø[Öjã[ c¢≤±∑®±∏§£d #undef gets char *gets (line) char *line; char *cp; unsigned int i; cp = line; while ((i = getchar()) != EOF && i != 0x0a) *cp++ = i;...
  • Page 122 å§ ± ∑§™ [ â≤£§Ø[ omso[ ã≥§ µ †∑®± ¶[ ↠± ∏† Ø å† ¶ §[|hn r |ilk ë∂®±¶[∑ߧ[ê~àá[讶±†Ø∂[•≤µ[觵®†Ø[Öjã[ c¢≤±∑®±∏§£d prints(s) unsigned int *s; int i; i=0; while (*(s+i) != 0) putchar(*(s+i)); i++; format (putsub, fmt, argp) register int (*putsub)(); register char *fmt; char *argp; register int c;...
  • Page 123 冶§ [ |hn s 姱 ∑§™ [â ≤ £ §Ø[om so[ã≥§µ† ∑®±¶[↠±∏† Ø |ilk ë∂®±¶[∑ߧ[ê~àá[讶±†Ø∂[•≤µ[觵®†Ø[Öjã[ c¢≤±∑®±∏§£d if (c == '*') width = *args.ip++; c = *fmt++; else for (width = 0 ; isdigit(c); c = *fmt++) width = width*10 + c - '0'; if ( c == '.' ) if ((c = *fmt++) == '*') maxwidth = *args.ip++;...
  • Page 124 å§ ± ∑§™ [ â≤£§Ø[ omso[ ã≥§ µ †∑®± ¶[ ↠± ∏† Ø å† ¶ §[|hn t |ilk ë∂®±¶[∑ߧ[ê~àá[讶±†Ø∂[•≤µ[觵®†Ø[Öjã[ c¢≤±∑®±∏§£d case 's': i = strlen(cp = *args.cpp++); goto havelen; #ifdef FLOAT case 'e': case 'f': case 'g': ftoa (*args.dp++, s, maxwidth==10000?6:maxwidth, c-'e'); i = strlen (cp = s);...
  • Page 125 冶§ [ |ho k 姱 ∑§™ [â ≤ £ §Ø[om so[ã≥§µ† ∑®±¶[↠±∏† Ø |ilk ë∂®±¶[∑ߧ[ê~àá[讶±†Ø∂[•≤µ[觵®†Ø[Öjã[ c¢≤±∑®±∏§£d else if ((*putsub)(c) == -1) return -1; ++charcount; return charcount; static char *scnstr; static char quit; sscanf (string, fmt, arg) char *string, *fmt; *arg;...
  • Page 126 å§ ± ∑§™ [ â≤£§Ø[ omso[ ã≥§ µ †∑®± ¶[ ↠± ∏† Ø å† ¶ §[|ho l |ilk ë∂®±¶[∑ߧ[ê~àá[讶±†Ø∂[•≤µ[觵®†Ø[Öjã [c¢≤±∑®±∏§£d int (*getsub) (); register char *fmt; register int **args; #ifdef FLOAT double atof (); #endif long register int c, count, base, cc; char suppress, lflag, widflg;...
  • Page 127 冶§ [ |ho m 姱 ∑§™ [â ≤ £ §Ø[om so[ã≥§µ† ∑®±¶[↠±∏† Ø |ilk ë∂®±¶[∑ߧ[ê~àá[讶±†Ø∂[•≤µ[觵®†Ø[Öjã[ c¢≤±∑®±∏§£d switch (cc = *fmt++) case '%': c = '%'; goto matchit; case 'h': /* specify short (for compatibility) */ lflag = 0; goto decimal; case 'D': lflag = 1;...
  • Page 128 å§ ± ∑§™ [ â≤£§Ø[ omso[ ã≥§ µ †∑®± ¶[ ↠± ∏† Ø å† ¶ §[|ho n |ilk ë∂®±¶[∑ߧ[ê~àá[讶±†Ø∂[•≤µ[觵®†Ø[Öjã[ c¢≤±∑®±∏§£d case 'e': case 'f': if (skipblank ()) goto stopscan; if (getflt (tlist)) goto stopscan; if (!suppress) if (lflag) *(double *) (*args++) = atof (tlist); else *(float *) (*args++) = atof (tlist);...
  • Page 129 冶§ [ |ho o 姱 ∑§™ [â ≤ £ §Ø[om so[ã≥§µ† ∑®±¶[↠±∏† Ø |ilk ë∂®±¶[∑ߧ[ê~àá[讶±†Ø∂[•≤µ[觵®†Ø[Öjã[ c¢≤±∑®±∏§£d if (lflag ? (strchr (tlist, c) != 0) : (strchr (tlist, c) == 0)) (*gsub) (1); /* unget last character */ break; if (!suppress) *cp++ = c;...
  • Page 130 å§ ± ∑§™ [ â≤£§Ø[ omso[ ã≥§ µ †∑®± ¶[ ↠± ∏† Ø å† ¶ §[|ho p |ilk ë∂®±¶[∑ߧ[ê~àá[讶±†Ø∂[•≤µ[觵®†Ø[Öjã[c¢≤±∑®±∏§£d stopscan: if (count == 0 if ((*gsub) (0) == EOF) return EOF; (*gsub) (1); return count; skipblank () while (isspace ((*gsub) (0))); if ((*gsub) (1) == EOF) return EOF;...
  • Page 131 冶§ [ |ho q 姱 ∑§™ [â ≤ £ §Ø[om so[ã≥§µ† ∑®±¶[↠±∏† Ø |ilk ë∂®±¶[∑ߧ[ê~àá[讶±†Ø∂[•≤µ[觵®†Ø[Öjã[c¢≤±∑®±∏§£d sign = 1; *cp = 0; return cp == buffer; #endif getnum (list, values, base, valp) char *list; char *values; long *valp; register char *cp;...
  • Page 132 å§ ± ∑§™ [ â≤£§Ø[ omso[ ã≥§ µ †∑®± ¶[ ↠± ∏† Ø å† ¶ §[|ho r |ilk ë∂®±¶[∑ߧ[ê~àá[讶±†Ø∂[•≤µ[觵®†Ø[Öjã[c¢≤±∑®±∏§£d ftoa(number, buffer, maxwidth, flag) double number; register char *buffer; register int i; int exp, digit, decpos, ndig; static double round[] = 1.0e+0, 0.5e+0, 0.5e-1,...
  • Page 133 冶§ [ |ho s 姱 ∑§™ [â ≤ £ §Ø[om so[ã≥§µ† ∑®±¶[↠±∏† Ø |ilk ë∂®±¶[∑ߧ[ê~àá[讶±†Ø∂[•≤µ[觵®†Ø[Öjã[ c¢≤±∑®±∏§£d if (flag == 2) /* 'g' format */ ndig = maxwidth; if (exp < -4 || exp >= maxwidth) flag = 0; /* switch to 'e' format */ else if (flag == 1) /* 'f' format */ ndig += exp;...
  • Page 134 å§ ± ∑§™ [ â≤£§Ø[ omso[ ã≥§ µ †∑®± ¶[ ↠± ∏† Ø å† ¶ §[|ho t |ilk ë∂®±¶[∑ߧ[ê~àá[讶±†Ø∂[•≤µ[觵®†Ø[Öjã[c¢≤±∑®±∏§£d if (ndig > 0) for (i = 0 ; ; ++i) if (i < 16) digit = (int)number; *buffer++ = digit+'0'; number = (number - digit) * 10.0;...
  • Page 135 冶§ [ |hp k 姱 ∑§™ [â ≤ £ §Ø[om so[ã≥§µ† ∑®±¶[↠±∏† Ø |ilk ë∂®±¶[∑ߧ[ê~àá[讶±†Ø∂[•≤µ[觵®†Ø[Öjã[c¢≤±∑®±∏§£d delay(unsigned int val) int tmp; /* Delay for 100 bit times before starting */ for (val=0; val<100; val++ ) /* Look for low clock transition */ tmp = *timer1_address &...
  • Page 136 å§ ± ∑§™ [ â≤£§Ø[ omso[ ã≥§ µ †∑®± ¶[ ↠± ∏† Ø å †¶ §[} hl |≥≥§±£®Ω[}u[}≤≤∑[Ååéãâ[è≤∏µ¢§[~≤£§[à®∂∑®±¶ }≤≤∑[Ååéãâ[è≤∏µ¢§[~≤£§[à®∂∑®±¶ }§Ø≤∫[®∂[†[b~ok[|∂∂§∞°Øæ[à†±¶∏†¶§[Ø®∂∑®±¶[≤•[∑ߧ[°≤≤∑[¢≤£§[†±£[Ø≤≤™j∂§∑[•∏±¢∑®≤±∂[¢≤±h ∑†®±§£[®±[∑ߧ[•†¢∑≤µæh®±∂∑†Øا£[Ååéãâ[≥µ≤𮣧£[°æ[姱∑§™[∫®∑ß[â≤£§Ø[omsoi .list TITLE 'PROCESSOR INITIALIZATION' .global RESET,INIT,BEGIN .global NMI,INT0,INT1,INT2,INT3,TINT0 .global NON_MASK,ISR0,ISR1,ISR2,ISR3,TIME0 .global LOOK,SET *********************************************************************** LOOK/SET memory usage HOST -------- ---------- 0x000200 0x80000200 = Function address from Host...
  • Page 137 冶§ [ } hm 姱∑§™[â ≤ £§Ø[omso [ã≥§µ† ∑® ±¶ [↠±∏† Ø }≤≤∑[Ååéãâ[è≤∏µ¢§[~≤£§[à®∂∑®±¶[ c¢≤±∑®±∏§£d PROCESSOR INITIALIZATION FOR THE TMS320C40. IN THIS SECTION, CONSTANTS THAT CANNOT BE REPRESENTED IN THE SHORT FORMAT ARE INITIALIZED. .text RESET .word INIT ; RS-load address INIT to HOST .word NON_MASK ;...
  • Page 138 å§ ± ∑§™ [ â≤£§Ø[ omso[ ã≥§ µ †∑®± ¶[ ↠± ∏† Ø å †¶ §[} hn }≤≤∑[Ååéãâ[è≤∏µ¢§[~≤£§[à®∂∑®±¶[ c¢≤±∑®±∏§£d PROC_ADDR .word 80000200H PROC_TEST .word 80000209H ; test address FBASE .word 00b00000H FBOOTL .word 00b00000H ; Points to boot flash flag GBOOTL .word 80000000H ;...
  • Page 139 冶§ [ } ho 姱∑§™[â ≤ £§Ø[omso [ã≥§µ† ∑® ±¶ [↠±∏† Ø }≤≤∑[Ååéãâ[è≤∏µ¢§[~≤£§[à®∂∑®±¶[ c¢≤±∑®±∏§£d * Setup pointers for HOST to use @PROC_ADDR,AR2 ; Processor base address @NOPFUNC,R0 ; Init GO address R0,*+AR2(0) @LOOKADR,R0 ; Init LOOK address R0,*+AR2(5) @SETADR,R0 ;...
  • Page 140 å§ ± ∑§™ [ â≤£§Ø[ omso[ ã≥§ µ †∑®± ¶[ ↠± ∏† Ø å †¶ §[} hp }≤≤∑[Ååéãâ[è≤∏µ¢§[~≤£§[à®∂∑®±¶[ c¢≤±∑®±∏§£d CKEND READGD @BOOTP,R0 ; Timer period Pass SETTMR READBD @BOOTF,R0 ; Timer period Fail SETTMR R0,*+AR0(028H) 03C0H,R0 ; Start timer R0,*+AR0(020H) * Set proccessor ready 1,R0...
  • Page 141 冶§ [ } hq 姱∑§™[â ≤ £§Ø[omso [ã≥§µ† ∑® ±¶ [↠±∏† Ø }≤≤∑[Ååéãâ[è≤∏µ¢§[~≤£§[à®∂∑®±¶[ c¢≤±∑®±∏§£d TIME0 ; Timer 0 interrupt processing PUSH PUSH PUSHF PUSH PUSHF PUSH PUSH LDPK 02Fh ; Point the DP register to page 2Fh * Toggle front panel LED @VMEREG,AR0 040H,R0 ;...
  • Page 142 å§ ± ∑§™ [ â≤£§Ø[ omso[ ã≥§ µ †∑®± ¶[ ↠± ∏† Ø å †¶ §[} hr }≤≤∑[Ååéãâ[è≤∏µ¢§[~≤£§[à®∂∑®±¶[ c¢≤±∑®±∏§£d RETURN 1,R0 R0,*+AR2(4) ; Set ready flag to Host IACK *+AR2(0) ; Clear VME interrupt POPF POPF RETI LOOK *+AR2(1),AR0 ;...
  • Page 143 冶§ [ } hs 姱∑§™[â ≤ £§Ø[omso [ã≥§µ† ∑® ±¶ [↠±∏† Ø }≤≤∑[Ååéãâ[è≤∏µ¢§[~≤£§[à®∂∑®±¶[ c¢≤±∑®±∏§£d LOAD0 CALLU AR2,*AR0 ; Store gbus control reg CALLU AR2,*+AR0(4) ; Store lbus control reg LOAD2 CALLU SUBI3 1,AR2,RC ; Set block size CMPI -1,RC ;...
  • Page 144 å§ ± ∑§™ [ â≤£§Ø[ omso[ ã≥§ µ †∑®± ¶[ ↠± ∏† Ø å †¶ §[} ht }≤≤∑[Ååéãâ[è≤∏µ¢§[~≤£§[à®∂∑®±¶[ c¢≤±∑®±∏§£d LOAD_W AR2,*AR0++(1) ; Store word to destination W_END RETSU CALL FLASHU RETSU FLOOK ; FLASH LOOK function CALL FLASHI *+AR2(1),AR0 ;...
  • Page 145 冶§ [ } hlk 姱 ∑§™ [â ≤ £ §Ø[om so[ã≥§µ† ∑®±¶[↠±∏† Ø }≤≤∑[Ååéãâ[è≤∏µ¢§[~≤£§[à®∂∑®±¶[ c¢≤±∑®±∏§£d FUNLDB ; FLASH UNLOAD BYTE function CALL FLASHI *+AR2(1),AR0 ; Get src address from 0x201 *+AR2(2),AR1 ; Get destination address *+AR2(3),RC ; Get count RPTB FUNLDBL *AR0++,R0...
  • Page 146 å§ ± ∑§™ [ â≤£§Ø[ omso[ ã≥§ µ †∑®± ¶[ ↠± ∏† Ø å† ¶§ [}hl l }≤≤∑[Ååéãâ[è≤∏µ¢§[~≤£§[à®∂∑®±¶[ c¢≤±∑®±∏§£d FUNLDWL R0,*AR1++ CALL FLASHU RETSU ERASE ; FLASH ERASE function CALL FLASHI @FSEQ55,AR3 ; Erase Chip command 0aaH,R0 R0,*AR3 @FSEQAA,AR3 055H,R0 R0,*AR3 @FSEQ55,AR3...
  • Page 147 冶§ [ } hlm 姱 ∑§™ [â ≤ £ §Ø[om so[ã≥§µ† ∑®±¶[↠±∏† Ø }≤≤∑[Ååéãâ[è≤∏µ¢§[~≤£§[à®∂∑®±¶[ c¢≤±∑®±∏§£d SERASEL *AR3,R1 ; Wait till ERASE complete TSTB 080H,R1 SERASEL CALL FLASHU RETSU FLASHI @CTRL,AR0 ; Point to control register @FLASHINT,R0 ; Init local memory interface control R0,*+AR0(4) CALL RFLASH...
  • Page 148 å§ ± ∑§™ [ â≤£§Ø[ omso[ ã≥§ µ †∑®± ¶[ ↠± ∏† Ø å† ¶§ [}hl n }≤≤∑[Ååéãâ[è≤∏µ¢§[~≤£§[à®∂∑®±¶[ c¢≤±∑®±∏§£d WRITEFLASH ; Enter with address in AR1 and data in R0 PUSH @FSEQ55,AR3 ; Write command 0aaH,R1 R1,*AR3 @FSEQAA,AR3 055H,R1 R1,*AR3 @FSEQ55,AR3 @FSEQWRT,R1...
  • Page 149 冶§ [ } hlo 姱 ∑§™ [â ≤ £ §Ø[om so[ã≥§µ† ∑®±¶[↠±∏† Ø }≤≤∑[Ååéãâ[è≤∏µ¢§[~≤£§[à®∂∑®±¶[ c¢≤±∑®±∏§£d CKERASE 0,R0 R0,*AR3 *AR3,R1 CKERASX 5,R0 R0,*AR3 *AR3,R1 CMPI R0,R1 CKERASX 0,R0 R0,*AR3 *AR3,R1 CKERASX CALL ERASE CKERASX RETSU ISR2 ; INT2- RETI ISR3 ;...
  • Page 150 Artisan Technology Group is your source for quality new and certified-used/pre-owned equipment SERVICE CENTER REPAIRS WE BUY USED EQUIPMENT • FAST SHIPPING AND DELIVERY Experienced engineers and technicians on staff Sell your excess, underutilized, and idle used equipment at our full-service, in-house repair center We also offer credit for buy-backs and trade-ins •...