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Summary of Contents for Concurrent Technologies RCIM Series
- Page 1 Artisan Technology Group is your source for quality new and certified-used/pre-owned equipment SERVICE CENTER REPAIRS WE BUY USED EQUIPMENT • FAST SHIPPING AND DELIVERY Experienced engineers and technicians on staff Sell your excess, underutilized, and idle used equipment at our full-service, in-house repair center We also offer credit for buy-backs and trade-ins •...
- Page 2 Real-Time Clock and Interrupt Module (RCIM) Userís Guide 0898007-600 December 2011 Artisan Technology Group - Quality Instrumentation ... Guaranteed | (888) 88-SOURCE | www.artisantg.com...
- Page 3 Copyright 2011 by Concurrent Computer Corporation. All rights reserved. This publication or any part thereof is intended for use with Concurrent Computer Corporation products by Concurrent Computer Corporation personnel, customers, and end–users. It may not be reproduced in any form without the written permission of the publisher. The information contained in this document is believed to be correct at the time of publication.
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Page 4: Preface
Preface Scope of Manual This manual is intended for users responsible for the installation and use of the Real-Time Clock and Interrupt Module (RCIM) on Concurrent Computer Corporation’s iHawk ® systems under the RedHawk Linux operating system. NOTE Three RCIM models are described in this guide: RCIM I, RCIM II and RCIM III. - Page 5 RCIM User’s Guide Operating system and program output such as prompts, messages and list listings of files and programs appears in list type. Brackets enclose command options and arguments that are optional. You do not type the brackets if you choose to specify these options or arguments.
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Page 6: Table Of Contents
Contents Preface ................Chapter 1 Introduction Overview . - Page 7 RCIM User’s Guide General Considerations ........2-22 MSI Interrupt Configuration .
- Page 8 Contents RCIM I Address Map ..........A-36 RCIM I Registers .
- Page 9 RCIM User’s Guide Figure A-27 RCIM III GPS Transmit Pointers (GTXP) ..... A-18 Figure A-28 RCIM III GPS Debug Control Register (GDCR) ....A-18 Figure A-29 RCIM III GPS Communication Error Register (GCER) .
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Page 10: Chapter 1 Introduction
Introduction Chapter 1 This chapter provides an overview and specifications for the Real-Time Clock and Interrupt Module (RCIM). NOTE Three RCIM models are described in this guide: RCIM I, RCIM II and RCIM III. The use of the term “RCIM” refers to functionality common to all three boards. -
Page 11: Specifications
RCIM User’s Guide Specifications Feature RCIM III RCIM II RCIM I Clocks POSIX Length 64 bits (two 32-bit words) 64 bits (two 32-bit words) 64 bits (two 32-bit words) Resolution High-order 32 bits–1 second High-order 32 bits–1 second High-order 32 bits–1 second Low-order 32 bits–400 nsec Low-order 32 bits–400 nsec Low-order 32 bits–400 nsec... -
Page 12: Chapter 2 Hardware, Installation And Configuration
Hardware, Installation and Configuration Chapter 1 This chapter provides a description of the RCIM PCI-based boards as well as installation and configuration information. Board Descriptions This section provides illustrations and descriptions of the RCIM III, RCIM II and RCIM I boards. -
Page 13: Rcim Iii
RCIM User’s Guide RCIM III Board Illustration Figure 2-1 shows the RCIM III board with optional high stability OCXO (Oven Controlled Crystal Oscillator) and GPS modules installed. Figure 2-1 RCIM III Board Connectors GPS Module Oven Controlled Crystal Oscillator Artisan Technology Group - Quality Instrumentation ... Guaranteed | (888) 88-SOURCE | www.artisantg.com... -
Page 14: Connectors And Leds
Hardware, Installation and Configuration Connectors and LEDs Figure 2-2 shows the input/output connectors and LEDs on the RCIM III board. Detailed information on the LEDs and each of the connectors is provided in the following sections. Figure 2-2 RCIM III Connectors and LED Locations Output Input Status LED... -
Page 15: Input And Output Cables And Connectors
RCIM User’s Guide followed by brief intervals of bright RED and GREEN as a test. During normal operation of the board the LEDs function as follows: description Function O u t p u t RED solid 10 MHz clock failure S t a t u s RED 2/sec flash cable option installed but not synchronized or miss-... -
Page 16: Gps Antenna
Hardware, Installation and Configuration GPS Antenna The GPS option on the RCIM III includes an active GPS antenna and coaxial cable. The antenna receives the GPS satellite signals and passes them to the receiver. The GPS signals are spread spectrum signals in the 1575 MHz range and do not penetrate conductive or opaque surfaces. -
Page 17: Figure 2-3 Rcim Iii External Interrupt I/O Connector Pin-Outs
RCIM User’s Guide Figure 2-3 RCIM III External Interrupt I/O Connector Pin-outs The external interrupt input signals are 5 volt ttl levels. The external interrupt outputs (labeled [0-11]) are driven using a line driver. The external interrupt EXT_PIG 74ABT16240 inputs are terminated with 180 ohms to +5 volts, 330 ohms and 0.1 uf to ground. To drive this input requires a line driver that can sink at least 30 ma. -
Page 18: System Identification
Hardware, Installation and Configuration The signals , and are RS-232 level signals. EXT_RXD1 EXT_TXD1 EXT_RXD2 EXT_TXD2 They are currently used for debug purposes. System Identification The following output to lspci(8) shows the PCI class, vendor and device IDs for the RCIM III (0e:04.0 (bus:slot.function) will differ on your system): # lspci -v | grep -i rcim... -
Page 19: Board Illustration
RCIM User’s Guide The last two messages indicate transient errors such as cable parity errors or temporary loss of cable synchronization. If a transient error occurs, it may require a link in the cable to resynchronize. If a distributed interrupt is being broadcast on the cable, it may be lost. Transient errors also affect the synchronization of the tick timers since the cable clock will not reach all of the systems. -
Page 20: Led Functions
Hardware, Installation and Configuration Detailed information on the LEDs and each of the connectors is provided in the following sections. Figure 2-5 RCIM II Connectors and LED Locations RJ45 Cable Connector LEDs 1-4 RJ45 Output RJ45 Input GPS Antenna External interrupt Cable Connector Cable Connector Connector... -
Page 21: Input And Output Cable Connectors
RCIM User’s Guide Input and Output Cable Connectors The output cable connector is used when the RCIM II is either the master, or a slave in the middle of an RCIM chain (see page 2-18 for a description of RCIM modes). The input cable connector is used when the RCIM is acting in slave mode. -
Page 22: Figure 2-6 Rcim Ii External Interrupt I/O Connector Pin-Outs
Hardware, Installation and Configuration Figure 2-6 RCIM II External Interrupt I/O Connector Pin-outs The external interrupt input signals are 5 volt ttl levels. The external interrupt outputs (labeled [0-11]) are driven using a line driver. The external interrupt EXT_PIG 74ABT16240 inputs are terminated with 180 ohms to +5 volts, 330 ohms and 0.1 uf to ground. -
Page 23: System Identification
RCIM User’s Guide The signals , and are RS-232 level signals. EXT_RXD1 EXT_TXD1 EXT_RXD2 EXT_TXD2 They are currently used for debug purposes. System Identification The following output to lspci(8) shows the PCI class, vendor and device IDs for the RCIM II (0d:06.0 (bus:slot.function) will differ on your system): # lspci -v | grep -i rcim 0d:06.0 System peripheral: Concurrent Computer Corp RCIM II... -
Page 24: Rcim I
Hardware, Installation and Configuration RCIM I This section provides illustrations and descriptions of the RCIM I board. Board Illustration Figure 2-7 shows the RCIM I board. Figure 2-7 RCIM I Board Connectors 2-13 Artisan Technology Group - Quality Instrumentation ... Guaranteed | (888) 88-SOURCE | www.artisantg.com... -
Page 25: Connectors And Leds
RCIM User’s Guide Connectors and LEDs Figure 2-8 shows the input/output connectors and LEDs on the RCIM I board. Detailed information on the LEDs and each of the connectors is provided in the following sections. Figure 2-8 RCIM I Connectors and LED Locations External Interrupts Connector (P4) Input Cable Connector (P3) Output Cable Connector (P2) -
Page 26: Output Cable Connector (P2)
Hardware, Installation and Configuration Output Cable Connector (P2) The output cable connector is used when the RCIM I is either the master, or a slave in the middle of an RCIM chain (see page 2-18 for a description of RCIM modes). The cable attached to the output cable connector is called a synchronization cable (part no. -
Page 27: Input Cable Connector (P3)
RCIM User’s Guide Input Cable Connector (P3) The input cable connector is used when the RCIM I is acting in slave mode (see page 2-18 for a description of RCIM modes). The cable attached to the input cable connector is called a synchronization cable (part no. -
Page 28: Debug Visibility Connector (P5)
Hardware, Installation and Configuration Pin-outs for the external interrupts connector are shown in Figure 2-11. Figure 2-11 RCIM I External Interrupts Connector (P4) Pin-outs Debug Visibility Connector (P5) The debug visibility connector is intended for use on the Concurrent Computer Corporation manufacturing floor and should not be used outside of that environment. -
Page 29: Connection Modes
RCIM User’s Guide Connection Modes When RCIM boards of various systems are chained together, an interrupt can be simultaneously distributed to all connected RCIMs, and from the RCIMs to all the associated host systems. NOTE All RCIMs in a chain must be the same model; for example, all RCIM IIs. -
Page 30: Installation
Hardware, Installation and Configuration Installation Normally, installation and configuration of the card is done by Concurrent Computer Corporation. This information is provided for those cases where an RCIM is added to a system in a post-manufacturing environment. In order to successfully install the RCIM, you must know if you will be using the RCIM to accept or deliver external interrupts and the mode in which the RCIM will run (isolated, master, pass-through slave or final slave). -
Page 31: Configuration
RCIM User’s Guide Configuration Kernel Configuration The following RedHawk Linux kernel parameters are associated with the RCIM. All are accessible through the Character Devices selection of the Kernel Configuration GUI and are enabled by default in all the pre-built RedHawk Linux kernels. This parameter configures the RCIM driver in the kernel. -
Page 32: Dynamic Configuration
Hardware, Installation and Configuration • the manner in which various interrupts will be triggered: rising or falling edge, high or low level • associations between interrupts, output lines and distributed interrupt lines • the name of the system in an RCIM chain that has the master RCIM •... -
Page 33: General Considerations
RCIM User’s Guide General Considerations When configuring the RCIM systems, keep the following in mind: • For a chain of RCIMs, the tick clock and POSIX clock in all slave RCIMs will be synchronized with the master because the clock signal incrementing time in the master is broadcast to all slaves. -
Page 34: Ntp Configuration For Gps Support
Hardware, Installation and Configuration ntp Configuration for GPS Support If your system contains the optional GPS module, ntp must be installed and configured to use the GPS receiver to synchronize the RCIM’s POSIX clock to GPS time. Follow these steps: 1. - Page 35 RCIM User’s Guide -216.56.81.86 193.131.101.50 49.388 -0.579 2.710 +new.localdomain .GPS. 0.182 0.010 0.020 *GENERIC(0) .GPS. 0.000 0.000 0.001 The output shows how the system time compares to other time sources. This includes the GPS receiver and other time servers. The column labeled remote is the hostname of the timeserver. The system new.localdomain is a local network time server;...
- Page 36 Hardware, Installation and Configuration azimuth= 49.55, collecting data", trimble_tracking_status[29]="ch=3, acq=ACQ, eph=19, signal_level= 15.80, elevation= 52.49, azimuth= 48.45, collecting data", trimble_receiver_health="doing position fixes, Battery backup failed", trimble_status="machine id 0x5a, Battery Powered Time Clock Fault, Superpackets supported", gps_position_ext(XYZ)="x= 1445085.4m, y= -4476862.4m, z= 4277122.9m", gps_position_ext(LLA)="lat 42.379423 N, lon 71.531318 W, alt 88.35m", trimble_tracking_status[15]="ch=7, acq=ACQ, eph=3, signal_level= 3.00, elevation= 28.28, azimuth= 311.83, collecting data",...
- Page 37 RCIM User’s Guide Artisan Technology Group - Quality Instrumentation ... Guaranteed | (888) 88-SOURCE | www.artisantg.com...
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Page 38: Chapter 3 Functional Description
Functional Description Chapter 1 This chapter describes the clocks and interrupt capabilities provided by the RCIM and the user interfaces for each. Overview The Real-Time Clock and Interrupt Module (RCIM) provides two non-interrupting clocks. One of these clocks can be synchronized with all the RCIMs in an RCIM chain to provide a common time stamp across systems. -
Page 39: The Tick Clock
RCIM User’s Guide The Tick Clock The tick clock is a 64-bit non-interrupting counter that increments by one on each tick of the common clock signal. Although it cannot be set to a specific time, it can be incremented or set to zero. Hence the tick clock cannot be adjusted on the fly to approximate the current time of day as would be required of a true time-of-day clock. -
Page 40: Direct Access To The Clocks
Functional Description section “Using GPS for System Timekeeping” for details. Generally, only the master RCIM needs a GPS; slaves use one of the software methods available for syncronizing their POSIX clock to the master. Direct Access to the Clocks The device file /dev/rcimN/sclk (where N is the RCIM card number starting from zero) can be used to access the RCIM clocks directly using mmap(2). - Page 41 RCIM User’s Guide rcim_clocksync takes the following options: interactive mode (see below) prints the configured hostname where the RCIM master is located (see “Con- figuration” in Chapter 2). prints the RCIM connection state devname The device name desired RCIM board. Defaults /dev/rcim0/rcim which is the first RCIM board that was found on boot.
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Page 42: Synchronizing The Tick Clock
Functional Description Status: is one of the following: tick timer CABLE_SYNC – indicates that the RCIM slave clock is being driven by RCIM master cable clock signal, if posix clock available CABLE_ENABLE – indicates that the RCIM clock resets when RCIM master does a synchronization LOCAL_ENABLE –... -
Page 43: Automatic Synchronization
RCIM User’s Guide POSIX clocks in the RCIM chain so that they are consistent, if desired. For the RCIM III, run rcimdate on each slave; on return the slave’s RCIM POSIX clocks will be synchronized with the master. For RCIM I and II use the following rcim_clocksync interactive mode procedure defined below. - Page 44 Functional Description treats the GPS receiver as a time server. For information about how to configure NTP for this support, see the section “ntp Configuration for GPS Support” in Chapter 2. RedHawk Linux includes the RFC-2783 pulse per second (PPS) interface that synchronizes the system time to the GPS PPS interface.
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Page 45: Interrupt Processing
RCIM User’s Guide Interrupt Processing One or more of the following modules is used for interrupt processing on the RCIM: • Edge-Triggered Interrupts (ETIs) – An ETI allows you to use an external event to trigger an interrupt. Documentation for ETIs begins on page 3-12. •... -
Page 46: Arming And Enabling Dis And Etis
Functional Description DIs and ETIs must be armed and enabled for an interrupt to occur. Each interrupt can be armed/disarmed and enabled/disabled individually. After power up initialization, all interrupts are disarmed and disabled. When the interrupt is armed, interrupt requests set a request bit. When an interrupt is disarmed, any outstanding requests are turned off and ignored. -
Page 47: Setting Up Distributed Interrupts
RCIM User’s Guide Setting up Distributed Interrupts The RCIM provides the ability to share interrupts across interconnected systems using an RCIM chain. Although distributed interrupts are covered in detail starting on page 3-17, the figures below provide an illustration of how they operate. Guidelines for setting up distributed interrupts based on the illustration follow. -
Page 48: Obtaining Rcim Values
Functional Description and on OUT . It is possible to configure another signal processing module (say RTC ) to drive the interrupts on DI and OUT at the same time. In this case, the signal that drives the line will be the one with the strongest amplifier. -
Page 49: Edge-Triggered Interrupts
RCIM User’s Guide Edge-Triggered Interrupts Each RCIM board has incoming external interrupt lines, called ETIs or edge-triggered interrupts, so-named after their most common mode of operation. These lines permit users to provide their own interrupt sources. The RCIM processes and delivers these interrupts to the host system and, if they are distributed, routes and delivers them to all other RCIMs in the chain as distributed interrupts. -
Page 50: Eti Device Files
Functional Description ETI Device Files Each ETI is accessed through its own special device file: /dev/rcimN/etiM where N is the RCIM card number (starting from zero) and M is the ID of the ETI. These files are created automatically on system boot by the /etc/init.d/rcim initialization script. -
Page 51: Distributed Etis
RCIM User’s Guide Distributed ETIs Any or all of the ETIs on an RCIM can be distributed to all systems connected by an RCIM chain. The source of a distributed ETI can be located on any of the RCIMs in the chain. -
Page 52: User Interface To Rtcs
Functional Description User Interface to RTCs A real-time clock timer is controlled by open(2), close(2), and ioctl(2) system calls. The close system call, if it closes the last open to the device, stops the RTC and clears its settings unless the ioctl command was issued to the RTC IOCTLKEEPALIVE before the close. -
Page 53: Configuration
RCIM User’s Guide Configuration Each external output line can be configured to be driven by a specified source using the following configuration option: <source> | outN The value specified for the source can be one of the following: rtcN real-time clock timers pigN programmable interrupt generators etiN... -
Page 54: Distributed Pigs
Functional Description external output, depending on how the PIGs are connected. The required length of the signal depends upon the requirements of the attached device. If the signal is being fed into another RCIM, it must hold any low or high value for at least 1.5 microseconds before changing to the next state. -
Page 55: Di Configuration
RCIM User’s Guide DI Configuration It is important that all RCIM-connected systems have a compatible configuration for the distributed interrupt lines of the RCIM. By default, no distributed interrupts are configured. Distributed interrupts must first have a source, and then can be configured to trigger on the rising or falling edge of a signal, or on a high or low signal value. -
Page 56: Di Device Files
Functional Description DI Device Files Each distributed interrupt is accessed through its own special device file: /dev/rcimN/diM where N is the RCIM card number (starting from zero) and M is the ID of the distributed interrupt. These files are created automatically on system boot by the /etc/init.d/rcim initialization script. - Page 57 RCIM User’s Guide 3-20 Artisan Technology Group - Quality Instrumentation ... Guaranteed | (888) 88-SOURCE | www.artisantg.com...
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Page 58: Rcim Iii Registers
Registers Appendix A This appendix describes the registers on the RCIM boards. RCIM III Registers This section contains the address map and registers on the RCIM III board. RCIM III Address Map Address Function 0xXXXX0000 Board Status/Control Register (BSCR) 0xXXXX0004 Firmware Rev/Options Present Register (FWOP) 0xXXXX0010... - Page 59 RCIM User’s Guide Address Function 0xXXXX1010 Tick Clock Status/Control (TCSC) 0xXXXX1100 POSIX Clock Seconds (PCS) 0xXXXX1108 POSIX Clock Nanoseconds (PCN) 0xXXXX1110 POSIX Clock Status/Control (PCSC) 0xXXXX1114 POSIX Clock Skip/Add Time (PCSAT) (Write Only) 0xXXXX1120 Clock Frequency Adjust Register (CFAR) 0xXXXX2000 RTC #0 Control (RTC0C) 0xXXXX2010...
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Page 60: Rcim Iii Registers
Registers RCIM III Registers RCIM III registers are illustrated in this section. NOTE: Unless otherwise stated, a bit value of 1=on; 0=off Figure A-1 RCIM III Board Status/Control Register (BSCR) This register provides status and control of certain features of the RCIM III board. Offset: 0000 Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0... -
Page 61: Figure A-2 Rcim Iii Firmware Revision/Options Present Register (Fwop)
RCIM User’s Guide Figure A-2 RCIM III Firmware Revision/Options Present Register (FWOP) This register provides information on what options are present on this RCIM board and the firmware revision. Offset: 00004 Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 Reserved Reserved External Oscillator Present (R) -
Page 62: Figure A-3 Rcim Iii Interrupt Enable/Request/Pending/Clear/Arm/Level/Polarity Registers (Ier, Irr, Ipr, Icr, Iar, Islr, Ispr
Registers Figure A-3 RCIM III Interrupt Enable/Request/Pending/Clear/Arm/Level/Polarity Registers (IER, IRR, IPR, ICR, IAR, ISLR, ISPR) The enable registers (IER) enable the selected interrupts. The request registers (IRR) are software driven requests of the selected interrupts. The pending registers (IPR) are pending requests. The clear registers (ICR) clear the selected interrupts. -
Page 63: Figure A-4 Rcim Iii External Interrupt Routing Registers (Eirr)
RCIM User’s Guide Figure A-4 RCIM III External Interrupt Routing Registers (EIRR) The external interrupt routing registers route selected interrupts to the external interrupt connector. Offset: EIRR1: 0070, EIRR2: 0074, EIRR3: 0078 External Interrupt Number Register Number Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res. -
Page 64: Figure A-5 Rcim Iii Cable Interrupt Routing Registers (Cirr)
Registers Figure A-5 RCIM III Cable Interrupt Routing Registers (CIRR) The cable interrupt routing registers route selected interrupts to the RCIM interconnecting cable. Offsets: CIRR1: 0080, CIRR2: 0084, CIRR3: 0088 Cable Interrupt Number Cable Interrupt Register 1 Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 Cable Interrupt Register 2 Bits... -
Page 65: Figure A-6 Rcim Iii Pps Snapshot Register (Pps)
RCIM User’s Guide Figure A-6 RCIM III PPS Snapshot Register (PPS) The PPS Snapshot register contains a snapshot of the nanoseconds field and two bits of the seconds field of the POSIX clock. The snapshot is taken every time the GPS PPS signal occurs. Offset: 0200 Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0... -
Page 66: Figure A-9 Rcim Iii Clear Cable Errors Register (Ccerr)
Registers Figure A-9 RCIM III Clear Cable Errors Register (CCERR) This is a Write Only register that clears any reported cable errors. The data field is don’t care. Offset: 0400 Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Clear Cable Errors Figure A-10 RCIM III Output Cable Status Register (OCSR) This register provides detailed hardware status information pertaining to the output cable. -
Page 67: Figure A-11 Rcim Iii Input Cable Status Register (Icsr
RCIM User’s Guide Figure A-11 RCIM III Input Cable Status Register (ICSR) This register provides detailed hardware status information pertaining to the input cable. Offset: 0420 Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 Reserved Reserved Transmit Loss of Lock... -
Page 68: Figure A-13 Rcim Iii Tick Clock Lower Register (Tcl
Registers Figure A-13 RCIM III Tick Clock Lower Register (TCL) This register contains the lower 32 bits of the tick clock. Offset: 1008 Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Tick Clock lower 32 bits Figure A-14 RCIM III Tick Clock Status/Control Register (TCSC) This register provides status and control of the tick clock. -
Page 69: Figure A-15 Rcim Iii Posix Clock Seconds Register (Pcs
RCIM User’s Guide Figure A-15 RCIM III POSIX Clock Seconds Register (PCS) This register contains the POSIX clock seconds. Offset: 1100 Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 POSIX Clock seconds Figure A-16 RCIM III POSIX Clock Nanoseconds Register (PCN) This register contains the POSIX clock nanoseconds. -
Page 70: Figure A-17 Rcim Iii Posix Clock Status/Control Register (Pcsc
Registers Figure A-17 RCIM III POSIX Clock Status/Control Register (PCSC) This register provides status and control of the POSIX clock. Offset: 1110 Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved Reserved Cable Enable (R) -
Page 71: Figure A-19 Rcim Iii Clock Frequency Adjust Register (Cfar
RCIM User’s Guide Figure A-19 RCIM III Clock Frequency Adjust Register (CFAR) The clock frequency adjust register is used to control the frequency of the 10 Mhz master clock. Offset: 1120 Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Clock Frequency Adjust Figure A-20 RCIM III RTC Timer Registers (RTCT) The initial RTC timer value is loaded in the RTC timer registers. -
Page 72: Figure A-22 Rcim Iii Rtc Control Registers (Rtcc
Registers Figure A-22 RCIM III RTC Control Registers (RTCC) This register provides control of the RTCs. Offsets: RTC0C: 2000, RTC1C: 2020, RTC2C: 2040, RTC3C: 2060, RTC4C: 2080, RTC5C: 20A0, RTC6C: 20C0, RTC7C: 20E0 Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res. -
Page 73: Figure A-23 Rcim Iii Programmable Interrupt Generator Register (Pig
RCIM User’s Guide Figure A-23 RCIM III Programmable Interrupt Generator Register (PIG) This register identifies the programmable interrupts. Offset: 3000 Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved Figure A-24 RCIM III Programmable Interrupt Set/Clear Registers (PIGS, PIGC) Writing to these registers sets/clears the unitary bits in the Programmable Interrupt Register without... -
Page 74: Figure A-25 Rcim Iii Spi Count Register (Scr
Registers Figure A-25 RCIM III SPI Count Register (SCR) The SPI (serial peripheral interface) count register contains the count for SPI transfers. The SPI interface is used to program the FPGA serial prom. Offset: 3100 Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 Reserved Count (R) Figure A-26 RCIM III GPS Receive Pointers (GRXP) -
Page 75: Figure A-27 Rcim Iii Gps Transmit Pointers (Gtxp
RCIM User’s Guide Figure A-27 RCIM III GPS Transmit Pointers (GTXP) The GPS transmit pointers are used for communication with the optional GPS module. Offset: 3204 Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 Reserved Reserved Transmit Head Pointer... -
Page 76: Figure A-29 Rcim Iii Gps Communication Error Register (Gcer
Registers Figure A-29 RCIM III GPS Communication Error Register (GCER) The GPS communication error register contains information regarding communication errors with the GPS module. Any write to this register will reset the communication interface to the GPS module. Offset: 320C Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 Reserved... -
Page 77: Figure A-32 Rcim Iii Gps Transmit Data Buffer (Grdb
RCIM User’s Guide Figure A-32 RCIM III GPS Transmit Data Buffer (GRDB) This is the GPS trasmit data buffer. Offset: 4800 to 4FFF Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 GPS Transmit Data Buffer A-20 Artisan Technology Group - Quality Instrumentation ... -
Page 78: Rcim Ii Address Map
Registers RCIM II Registers This section contains the address map and registers on the RCIM II board. RCIM II Address Map Address Function 0xXXXX0000 Board Status/Control Register (BSCR) 0xXXXX0004 Firmware Rev/Options Present Register (FWOP) 0xXXXX0010 Interrupt Enable Register #1 (IER1) 0xXXXX0014 Interrupt Enable Register #2 (IER2) - Page 79 RCIM User’s Guide Address Function 0xXXXX1100 POSIX Clock Seconds (PCS) 0xXXXX1108 POSIX Clock Nanoseconds (PCN) 0xXXXX1110 POSIX Clock Status/Control (PCSC) 0xXXXX1114 POSIX Clock Skip/Add Time (PCSAT) (Write Only) 0xXXXX2000 RTC #0 Control (RTC0C) 0xXXXX2010 RTC #0 Timer (RTC0T) 0xXXXX2014 RTC #0 Repeat (RTC0R) 0xXXXX2020 RTC #1 Control...
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Page 80: Rcim Ii Registers
Registers RCIM II Registers RCIM II registers are illustrated in this section. NOTE: Unless otherwise stated, a bit value of 1=on; 0=off. Figure A-33 RCIM II Board Status/Control Register (BSCR) This register provides status and control of certain features of the RCIM II board. Offset: 0000 Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0... -
Page 81: Figure A-34 Rcim Ii Firmware Revision/Options Present Register (Fwop
RCIM User’s Guide Figure A-34 RCIM II Firmware Revision/Options Present Register (FWOP) This register provides information on what options are present on this RCIM board and the firmware revision. Offset: 00004 Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 Reserved Reserved External Oscillator Present (R) -
Page 82: Figure A-35 Rcim Ii Interrupt Enable/Request/Pending/Clear/Arm/Level/Polarity
Registers Figure A-35 RCIM II Interrupt Enable/Request/Pending/Clear/Arm/Level/Polarity Registers (IER, IRR, IPR, ICR, IAR, ISLR, ISPR) The enable registers (IER) enable the selected interrupts. The request registers (IRR) are software driven requests of the selected interrupts. The pending registers (IPR) are pending requests. The clear registers (ICR) clear the selected interrupts. -
Page 83: Figure A-36 Rcim Ii External Interrupt Routing Registers (Eirr
RCIM User’s Guide Figure A-36 RCIM II External Interrupt Routing Registers (EIRR) The external interrupt routing registers route selected interrupts to the external interrupt connector. Offset: EIRR1: 0070, EIRR2: 0074, EIRR3: 0078 External Interrupt Number Register Number Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res. -
Page 84: Figure A-37 Rcim Ii Cable Interrupt Routing Registers (Cirr
Registers Figure A-37 RCIM II Cable Interrupt Routing Registers (CIRR) The cable interrupt routing registers route selected interrupts to the RCIM interconnecting cable. Offsets: CIRR1: 0080, CIRR2: 0084, CIRR3: 0088 Cable Interrupt Number Cable Interrupt Register 1 Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 Cable Interrupt Register 2 Bits... -
Page 85: Figure A-38 Rcim Ii Pci Interrupt Routing Registers (Parr, Pbrr, Pcrr, Pdrr)
RCIM User’s Guide Figure A-38 RCIM II PCI Interrupt Routing Registers (PARR, PBRR, PCRR, PDRR) Setting a bit in a PCI interrupt routing register routes selected interrupts to the designated PCI interrupt. The default power-up value is everything routed to PCI A. Setting bits in multiple registers will drive multiple PCI interrupt lines. -
Page 86: Figure A-40 Rcim Ii Pps Snapshot Register (Pps
Registers Figure A-40 RCIM II PPS Snapshot Register (PPS) The PPS Snapshot register contains a snapshot of the nanoseconds field and two bits of the seconds field of the POSIX clock. The snapshot is taken every time the GPS PPS signal occurs. Offset: 0200 Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0... -
Page 87: Figure A-43 Rcim Ii Tick Clock Upper Register (Tcu
RCIM User’s Guide Figure A-43 RCIM II Tick Clock Upper Register (TCU) This register contains the upper 32 bits of the tick clock. Offset: 1000 Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Tick Clock upper 32 bits Figure A-44 RCIM II Tick Clock Lower Register (TCL) This register contains the lower 32 bits of the tick clock. -
Page 88: Figure A-46 Rcim Ii Posix Clock Seconds Register (Pcs
Registers Figure A-46 RCIM II POSIX Clock Seconds Register (PCS) This register contains the POSIX clock seconds. Offset: 1100 Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 POSIX Clock seconds Figure A-47 RCIM II POSIX Clock Nanoseconds Register (PCN) This register contains the POSIX clock nanoseconds. -
Page 89: Figure A-48 Rcim Ii Posix Clock Status/Control Register (Pcsc
RCIM User’s Guide Figure A-48 RCIM II POSIX Clock Status/Control Register (PCSC) This register provides status and control of the POSIX clock. Offset: 1110 Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved Reserved Cable Enable (R) -
Page 90: Figure A-50 Rcim Ii Rtc Timer Registers (Rtct
Registers Figure A-50 RCIM II RTC Timer Registers (RTCT) The initial RTC timer value is loaded in the RTC timer registers. The current value of the timer is read from this register. NOTE: Loading this register also loads the RTC Repeat Register for compatibility with RCIM. Offsets: RTC0T: 2010, RTC1T: 2030, RTC2T: 2050, RTC3T: 2070, RTC4T: 2090, RTC5T: 20B0, RTC6T: 20D0, RTC7T: 20F0 Bits... -
Page 91: Figure A-52 Rcim Ii Rtc Control Registers (Rtcc
RCIM User’s Guide Figure A-52 RCIM II RTC Control Registers (RTCC) This register provides control of the RTCs. Offsets: RTC0C: 2000, RTC1C: 2020, RTC2C: 2040, RTC3C: 2060, RTC4C: 2080, RTC5C: 20A0, RTC6C: 20C0, RTC7C: 20E0 Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res. -
Page 92: Figure A-53 Rcim Ii Programmable Interrupt Generator Register (Pig
Registers Figure A-53 RCIM II Programmable Interrupt Generator Register (PIG) This register identifies the programmable interrupts. Offset: 3000 Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved Figure A-54 RCIM II Programmable Interrupt Set/Clear Registers (PIGS, PIGC) Writing to these registers sets/clears the unitary bits in the Programmable Interrupt Register without... -
Page 93: Rcim I Registers
RCIM User’s Guide RCIM I Registers This section contains the address map and registers on the RCIM I board. RCIM I Address Map Address Function 0xXXXX0000 Board Status/Control Register (BSCR) 0xXXXX0010 Interrupt Enable Register (IER) 0xXXXX0020 Interrupt Request Register (IRR) (Write Only) 0xXXXX0020 Interrupt Pending Register... -
Page 94: Figure A-55 Rcim I Board Status/Control Register (Bscr
Registers RCIM I Registers RCIM Iregisters are illustrated in this section. NOTE: Unless otherwise stated, a bit value of 1=on; 0=off. Figure A-55 RCIM I Board Status/Control Register (BSCR) This register provides status and control of certain features of the RCIM I board. Offset: 0000 Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0... -
Page 95: Figure A-56 Rcim I Interrupt Enable/Request/Pending/Clear/Arm/Level/Polarity
RCIM User’s Guide Figure A-56 RCIM I Interrupt Enable/Request/Pending/Clear/ARM/Level/Polarity Registers (IER, IRR, IPR, ICR, IAR, ISLR, ISPR) The enable register (IER) enables the selected interrupt. The request register (IRR) is a software driven request of the selected interrupt. The pending register (IPR) is a pending request. The clear register (ICR) clears the selected interrupt. -
Page 96: Registers (Ier, Irr, Ipr, Icr, Iar, Islr, Ispr
Registers Figure A-57 RCIM I External Interrupt Routing Register (EIRR) The external interrupt routing register routes selected interrupts to the external interrupt connector. Offset: 0070 External Interrupt Number Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 Value Description... -
Page 97: Figure A-58 Rcim I Cable Interrupt Routing Register (Cirr
RCIM User’s Guide Figure A-58 RCIM I Cable Interrupt Routing Register (CIRR) The cable interrupt routing register routes selected interrupts to the RCIM I interconnecting cable. Offset: 0080 Cable Interrupt Number Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 3 2 1 0 3 2 1 0 3 2 1 0 3 2 1 0 3 2 1 0 3 2 1 0 3 2 1 0 3 2 1 0 Value Description... -
Page 98: Registers (Ier, Irr, Ipr, Icr, Iar, Islr, Ispr
Registers Figure A-59 RCIM I Tick Clock Upper Register (TCU) This register contains the upper 32 bits of the tick clock. Offset: 1000 Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Tick Clock upper 32 bits Figure A-60 RCIM I Tick Clock Lower Register (TCL) This register contains the lower 32 bits of the tick clock. -
Page 99: Figure A-62 Rcim I Posix Clock Seconds Register (Pcs
RCIM User’s Guide Figure A-62 RCIM I POSIX Clock Seconds Register (PCS) This register contains the POSIX clock seconds. Offset: 1100 Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 POSIX Clock seconds Figure A-63 RCIM I POSIX Clock Nanoseconds Register (PCN) This register contains the POSIX clock nanoseconds. -
Page 100: Figure A-65 Rcim I Rtc Control Registers
Registers Figure A-65 RCIM I RTC Control Registers This register provides control of the RTCs. Offsets: RTC #0: 2000, RTC #1: 2020, RTC #2: 2040, RTC #3: 2060 Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res. -
Page 101: Figure A-67 Rcim I Programmable Interrupt Generator Register (Pig
RCIM User’s Guide Figure A-67 RCIM I Programmable Interrupt Generator Register (PIG) The PIG register identifies the programmable interrupts. Offset: 3000 Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved A-44 Artisan Technology Group - Quality Instrumentation ... - Page 102 Calculating RCIM Cable Propagation Delays Appendix B This appendix provides calculations to determine if your cable connections introduce signal delays. RCIM III The maximum cable length between each interconnected RCIM III board is 30 meters (~100 feet). The clock runs at 400ns per tick. If the clock signal takes more than 400ns to make it to any given slave in the chain, clock skew will occur from that point on.
- Page 103 RCIM User’s Guide Note that if a pass-through slave system is powered off, the cable clock will not be propagated to the slaves downstream from it. In this case, the downstream slaves will use their local oscillator instead of the cable clock. If chaining is to be done through different locations using different grounds, talk to your Concurrent representative about the risk of ground loops.
- Page 104 Calculating RCIM Cable Propagation Delays It is recommended that systems be placed as close together as practical in order to minimize propagation delays. Extremely long runs through high RF noise or high temperature environments should be avoided when planning RCIM cable routes. Note that if a pass-through slave system is powered off, the cable clock will not be propagated to the slaves downstream from it.
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Page 106: Index
Index Paths clock registers A-11, A-30, A-41 clock synchronization 2-21, 3-3 clocks /dev/rcim_uart 3-7 description 3-1 /etc/init.d/rcim 2-20 direct access 3-3 /etc/init.d/rcim_clocksync 3-6 /etc/sysconfig/rcim_clocksync 3-6 GPS 2-23, 3-6 /proc/driver/rcim0 3-11 clocksource 2-20–2-21 /usr/include/linux/rcim_ctl.h 3-11 close system call 3-1 /usr/include/linux/rcim.h 3-3 configuration information 3-11 configuration requirements 2-20 connection modes 2-18... - Page 107 RCIM User’s Guide RCIM III 2-4 installation instructions 2-19 In-System Programming Interface Connector P6 (RCIM edge-triggered interrupts, see ETIs I) 2-17 ETIs interrupt arming 3-13 handling 3-8 configuration 3-12 registers A-5, A-25, A-38 device files 3-13 introduction 1-1 disarming 3-13 ioctl system call 3-1, 3-11 distributed 3-14 isolated mode 2-18...
- Page 108 Index overview 3-16 registers A-16, A-35, A-44 POSIX clock TCXO (Temperature Compensated Crystal Oscillator) GPS 2-20 tick clock overview 3-2 GPS 2-20 registers A-13, A-32, A-42 overview 3-2 set time 3-3 registers A-11, A-30, A-41 synchronizing 3-5 synchronizing 3-5 POSIX Clock Status/Control Register Tick Clock Status/Control Registers RCIM I A-42 RCIM I A-41...
- Page 109 RCIM User’s Guide Index-4 Artisan Technology Group - Quality Instrumentation ... Guaranteed | (888) 88-SOURCE | www.artisantg.com...
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