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Sundance Technology ST201 Specification Sheet

Fast ethernet mac
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Sundance Technology
FEATURES
•
Single chip 10/100BASE, half or full duplex
Ethernet Media Access Controller
•
IEEE 802.3u compliant MII
•
IEEE 802.3x full duplex flow control
•
PCI Bus master scatter/gather DMA on any
byte boundary
•
On-chip transmit and receive FIFO buffers
•
On-chip LED drivers
•
Power management capabilities for ACPI
1.0 compliant systems
•
WakeOnLAN support
•
Management statistics gathering
•
IP multicast receive and filter support using
64 bit hash table
•
Receive early interrupt
•
Transmit polling
•
Auto pad insertion for short packets
•
Programmable minimum Inter Packet Gap
•
Programmable transmit and receive FIFO
watermarks
•
On-chip crystal oscillator
•
3.3V CMOS with 5V tolerant I/O
•
0.35 m technology
•
128-pin PQFP
See Sundance Technology' s website at www.sundanceti.com for the latest information.
Fast Ethernet MAC

GENERAL DESCRIPTION

The ST201 is a single-chip, full duplex, 10/
100Mbps Ethernet MAC incorporating a 32-bit PCI
including bus master support. The ST201 is
designed for use in a variety of applications rang-
ing from workstation NICs, networking equipment
such as switches or routers, and other systems uti-
lizing a PCI bus which require network connectivity
to an Ethernet or Fast Ethernet LAN.
The ST201 includes a PCI bus interface unit, IEEE
802.3 compliant MAC, transmit and receive FIFO
buffers, IEEE 802.3u compliant MII, serial Electri-
cally EEPROM interface, expansion ROM inter-
face, and LED drivers.
The ST201 implements a rich set of control and
status registers. Accessible via the PCI interface,
these registers provide a host system visibility into
the features and operating state of the ST201. Net-
work management statistics are also recorded, and
host access to registers of the PHY device are
facilitated through the ST201' s PCI interface.
The ST201 supports several features for use in
" Green PCs" or systems where control over system
power consumption is desired. The ST201 sup-
ports several power down states, and the ability to
issue a system " wake event" via reception of
unique, user defined Ethernet frames. In addition,
the ST201 can assert a wake event in response to
changes in the Ethernet link status.
PRELIMINARY draft 2
ST201
Publication:
2
Rev: A
Date:
November 1998

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Summary of Contents for Sundance Technology ST201

  • Page 1: General Description

    “ wake event” via reception of unique, user defined Ethernet frames. In addition, the ST201 can assert a wake event in response to changes in the Ethernet link status. Publication:...

  • Page 2: Block Diagram

    SERRN VDET MISCELLANEOUS GPIO0 GPIO1 RSTOUT X25I X25O CLK25 POWER ST201 Status/Control Registers FIFO FIFO Statistic Registers FIGURE 1: ST201 Block Diagram PRELIMINARY draft 2 TXD[3..0] TXEN TXCLK RXD[3..0] RXCLK RXER RXDV MDIO EEPROM EEDO EEDI EESK EECS EXPANSION ROM ED[7..0]...

  • Page 3: Ordering Information

    Sundance Technology ORDERING INFORMATION Sundance products are available in several combinations of packages and operating temperature ranges. The order number is formed by a combination of the elements below ST201 ST201 TEMPERATURE RANGE C=Commercial (0 to +70C) PACKAGE TYPE K=Plastic Quad Flat Pack...

  • Page 4: Pin Diagram

    Sundance Technology ST201 PRELIMINARY draft 2 PIN DIAGRAM...

  • Page 5: Pin Designations

    PHYDPLXN ED6/GPIO0 CLK25 GND (5V) VCC (3.3V) TXD3 TXD2 TXD1 TXD0 TXEN GND (5V) TXCLK RXER TABLE 1: ST201 Pin Designations PRELIMINARY draft 2 PIN NAME RXCLK RXDV RXD0 RXD1 RXD2 RXD3 GND (5V) GND (3.3V) MDIO PHYLNKN VCC (3.3V)

  • Page 6: Pin Descriptions

    ST201 PIN DESCRIPTION PCI INTERFACE Reset, asserted LOW. RSTN will cause the ST201 to reset all of its functional blocks. RSTN must be asserted for a minimum duration of 10 PCICLK cycles. PCI Bus Clock. This clock is used to drive the PCI bus interfaces and the internal DMA logic.
  • Page 7 A bus master will monitor TRDYN. Device Select, asserted LOW. The ST201 asserts DEVSELN when it is selected as a target during a bus transaction. It monitors DEVSELN for any target to acknowledge a bus transaction initiated by the ST201.
  • Page 8 EEPROM data access with EEDI and EEDO. It is connected directly to the clock input of the EEPROM device. (This pin is shared with EA15) EEPROM Chip Select. EECS is asserted by the ST201 to access the EEPROM. It is connected directly to the chip select input of the EEPROM device.
  • Page 9 General Purpose Input/Output. (This pin is shared with ED7) Reset Output, assertion level is programmable (see I/O Registers, AsicCtrl bit 15). The ST201 will assert RSTOUT when it is being reset. RSTOUT is intended to be used to reset other circuitry on the adapter.

  • Page 10: Acronyms And Glossary

    The MAC is responsible for generation of hardware signals to update the internal statistics counters. MEDIA INDEPENDENT INTERFACE The ST201 can support a variety of physical signal- ing schemes via the IEEE 802.3u defined MII. Through the MII, the ST201 supports Fast Ethernet (such as 100BASE-TX) as well as the legacy 10BASE-T standard.
  • Page 11 The PCI Bus Interface (PBI) implements the proce- dures and algorithms needed to link the ST201 to a PCI bus. The ST201 can be either a PCI bus mas- ter or slave. The PBI is also responsible for manag- ing the DMA interfaces and the host processors access to the ST201 registers.
  • Page 12 ROM, if any. • CacheLineSize indicates the system’ s cache line size. This value is used by the ST201 to opti- mize bus master data transfers. • LatencyTimer sets the length of time the ST201 can hold the PCI bus as a bus master.
  • Page 13 The MACCtrl register is used to configure parame- ters including full duplex, flow control, and statistics gathering. The ST201 can operate in either half duplex or full duplex mode. In half duplex mode, the ST201 implements the CSMA/CD algorithm. CSMA/CD requires that only one node transmit at a time.
  • Page 14 TXDMA AND FRAME TRANSMISSION The TxDMA block transfers frame data from a host system to the ST201 based on a linked list of frame descriptors called TFDs. The frame to be transmit- ted is divided into data fragments (or buffers) within the host system’...
  • Page 15 TxDMAList. TxDMAListPtr must point to addresses which are on 8-byte boundaries. A value of zero in the TxDMAListPtr register implies there are no pending TFD’ s for the ST201 to pro- cess. Generally, it is desirable for the host system to queue multiple frames.
  • Page 16 TxDMA mechanism. RxDMA is structured around a linked list of frame descriptors, called RFDs. RFDs ST201 PRELIMINARY draft 2 contain pointers to the fragment buffers into which the ST201 is to place receive data, as shown in Figure 4. HOST SYSTEM MEMORY Next RFD Ptr. RxFrameStatus...
  • Page 17 RxDMACom- plete bit within the ReceiveFrameStatus field of the next RFD in the ring. If the ST201 fetches a RxD- MAListPtr for a RFD that has already been used (a RFD in which the RxDMAComplete bit is set in...
  • Page 18 The host system can program any value greater than or equal to 0x08 into RxEar- lyThresh. The ST201 needs a minimum of 8 frame bytes to perform destination address filtering before generating an RxEarly interrupt. The value...
  • Page 19 The list of PCI memory commands is shown below. For all commands, “ read” and “ write” are with respect to the ST201 (i.e. read implies the ST201 obtains information from an off-chip loca- tion, write implies the ST201 sends information to an off-chip location).

  • Page 20: Power Management

    In D1 the ST201 does not respond to any PCI I/O or memory accesses. The ST201’ s function in the D1 state is to rec- ognize wake events and link state events and pass them on to the system by asserting the PMEN signal on the PCI bus.
  • Page 21 Sundance Technology D1, D2, or D3. When the ST201 detects a Wake Packet, it signals a wake event on PMEN (if PMEN assertion is enabled), and sets the WakePktEvent bit in the WakeEvent register. The ST201 can sig- nal that a wake event has occurred when it receives a pre-defined frame from another station.
  • Page 22 D1, D2, or D3 states, and MagicPktEnable has no effect when the ST201 is in the D0 power state. The Magic Packet must also pass the address matching crite- ria set in ReceiveMode. A Magic Packet may also be a broadcast frame.

  • Page 23: Eeprom Commands

    9. Execute a Z cycle to terminate the frame. EEPROM COMMANDS The EepromCtrl register provides the host with a method for issuing commands to the ST201’ s serial EEPROM controller. Individual 16-bit word locations within the EEPROM may be written, read or erased.
  • Page 24 If the value fetched from TxD- MANextPtr is non-zero, then the value is loaded into TxDMAListPtr, advancing the ST201 to the new TFD. 10. With a new TFD to process, the ST201 returns to step 2. ADDING TFD’ S TO THE END OF THE TXDMALIST The following sequence describes the process for adding TFD’...
  • Page 25 RxDMAResume has been issued. 11. Fetches RxDMANextPtr from the RFD. If RxD- MANextPtr is zero and polling is enabled, the ST201 begins a polling loop. If polling is dis- abled, the ST201 loads the fetched value into RxDMAListPtr. 12. Writes ReceiveFrameStatus to the RFD in host memory.
  • Page 26 Wake/ Magic packets). The operating system eventu- ally writes to the PowerMgmtCtrl register, plac- ing the ST201 in one of the power down states, and enabling PMEN assertion, while the ST201 monitors for the occurrence of enabled wake events.
  • Page 27 A TFD is used to move data, which is to be transmitted onto a LAN, from host system memory to the TxFIFO within the ST201. A TFD is 16 to 512 bytes in length, and it’ s location in host system memory is indicated by the value in the TxDMAListPtr register.

  • Page 28: Bit Description

    31..0 TxDMAFragAddr ST201 BIT DESCRIPTION Transmit Fragment Address contains the physical address of a contig- uous block of data to be transferred by TxDMA into the ST201 and transmitted. A fragment can start on any byte boundary. PRELIMINARY draft 2...
  • Page 29 FragAddr. The maximum fragment length is 8192 bytes. Reserved for future use. Should be set to 0. Set by the host system to indicate the last fragment of the transmit frame and that the ST201 should proceed to the next TFD. PRELIMINARY draft 2...
  • Page 30 Width ...32 bits BIT NAME 31..0 TxDMANextPtr ST201 BIT DESCRIPTION Transmit Next Pointer, the first double word in the TFD contains the physical address of the next TFD in the TxDMAList. The value of zero accompanies the last frame of the list and it indicates there are no more TFD’...
  • Page 31 Reserved for future use. Should be set to 0. Set if the host system desires a TxDMAComplete interrupt upon com- pletion of TxDMA of this frame. The TFC is read twice by the ST201; the first time to write the TFC to the TxFIFO before frame data transfer, and again after the TxDMA operation is complete to test TxDMAIndi- cate in order to determine whether to generate an interrupt.
  • Page 32 Width ...32 bits BIT NAME 31..0 RxDMANextPtr ST201 BIT DESCRIPTION The first dword in the RFD contains the physical address of the next RFD in the RxDMAList. If this is the last RFD in the RxDMAList, then this value must be zero. RFDs must be aligned on 8-byte physical address boundaries.
  • Page 33 Access Mode ...Read/Write Width ...32 bits The second dword in the RFD is ReceiveFrameStatus. At the end of a RxDMA frame transfer, the ST201 writes the value of the RxDMAStatus register into this location in the RFD. The bit definitions for TxFrameStatus for bits[31..29] and [27..0] are identical to the corresponding bits of the I/O Register RxDM-...
  • Page 34 Indicates that the RFD had insufficient buffer space for the frame data and there were still data left to be transferred by RxDMA when the ST201 ran out of fragment space. The ST201 will transfer what it can into the buffers provided, discard the remainder of the frame and set this bit.
  • Page 35 Width ...32 bits BIT NAME 31..0 RxDMAFragAddr ST201 BIT DESCRIPTION The third and all subsequent odd dwords in the RFD contains the phys- ical address of a contiguous block of system memory to which receive data is to be transferred by RxDMA. A fragment can start on any byte boundary.
  • Page 36 12..0 FragLen 30..13 Reserved RxDMALastFrag ST201 BIT DESCRIPTION The length of the contiguous block of data pointed to by the previous RxDMAFragAddr. Reserved for future use. Should be set to 0. Set by the host system to indicate the last fragment of the receive frame.
  • Page 37 The second Wake Event Data Structure is the Magic Packet. Magic Packets are uniquely formatted frames, which upon reception invoke a Wake Event by the ST201. Once the ST201 has been placed in Magic Packet mode and put to sleep, it scans all incoming frames addressed to it for a data sequence con- sisting of a synchronization stream followed immediately by 16 consecutive repetitions of the station’...
  • Page 38 3..0 ByteCount 7..4 ByteOffset ST201 BIT DESCRIPTION ByteCount can take on a value of 0x0 to 0xe. A value of 0xf indicates an extended value. The extended value will occupy 8 bits and is con- tained in the next PseudoPattern. If both the ByteOffset and the Byte-...
  • Page 39 Sundance Technology ST201 PRELIMINARY draft 2 TERMINATOR Class...Wake Event Data Structures, Pseudo Packet Base Address ...Start of Pseudo Packet Address Offset ...0x00+n for n PseudoPattern Access Mode ...Write only Width ...8 bits BIT NAME BIT DESCRIPTION 7..0 Terminator A value of 0x00 indicates the end of the PseudoPattern.
  • Page 40 15..8 PsuedoCRCbyte1 23..16 PsuedoCRCbyte2 31..24 PsuedoCRCbyte3 ST201 BIT DESCRIPTION The least significant byte of the PseudoCRC. The second lest significant byte of the PseudoCRC. The second most significant byte of the PseudoCRC. The most significant byte of the PseudoCRC. PRELIMINARY draft 2...
  • Page 41 Base Address ...Start of Magic Packet Address Offset ...0x00 Access Mode ...Read only Width ...48 bits BIT NAME 47..0 MagicSyncStream ST201 BIT DESCRIPTION A stream of 6 bytes with the value 0xff indicates the start of the Magic- Sequence. PRELIMINARY draft 2...
  • Page 42 Access Mode ...Read only Width ...768 bits BIT NAME 767..0 MagicSequence ST201 BIT DESCRIPTION A sequence of 96 bytes, consisting of 16 consecutive, identical 6 bytes sequences, where each 6 byte sequence equals the station address of the station receiving the Magic Packet.
  • Page 43 PRELIMINARY draft 2 I/O REGISTERS The host interacts with the ST201 mainly through slave registers, which occupy 128 bytes in the host sys- tem’ s I/O space, memory space, or both. Generally, registers are referred to as “ I/O registers” , implying that the registers may in fact be mapped and accessed by the host system in memory space.
  • Page 44 OctetsReceivedOk(1) HashTable(3) HashTable(1) MaxFrameSize StationAddress(1) MACCtrl(1) IntStatus IntStatusAck TxFrameId TxStatus RxEarlyThresh FIFOCtrl EepromCtrl DebugCtrl RxDMAPollPeriod TxDMAPollPeriod FIGURE 11: ST201 I/O Register Layout ST201 byte 2 byte 1 BcstFramesRcvdOk FramesLostRxErrors LateCollisions FramesTransmittedOk OctetsTransmittedOk(0) OctetsReceivedOk(0) PhyCtrl TxReleaseThresh StationAddress(2) StationAddress(0) WakeEvent ExpRomAddr AsicCtrl...
  • Page 45 1 = 64 kB This read/write bit, when set, enables transmission of frames that are larger than the TxFIFO. Since ST201’ s TxFIFO size is 2KB, this bit can be left clear (the reset default). This read/write bit, when set, enables reception of frames that are larger than the RxFIFO.
  • Page 46 When set, RSTOUT is asserted high. When cleared, RSTOUT is asserted low. This is a self-clearing global reset bit for the entire ST201. This bit con- trols reset to various logic blocks depending on the values of the selec- tion bits [24..19]. The ST201 should be re-initialized after a GlobalReset.
  • Page 47 RSTOUT. This bit is self-clearing. Setting this bit has no meaning if the corresponding GlobalReset bit is not set. When set, the ST201 will assert IntRequested bit in the IntStatus regis- ter. This bit is self-clearing. When set, this bit indicates the reset is in progress. As the adapter’ s serial EEPROM may need to be read as part of the reset process, this operation can take as long as 1 ms to complete.
  • Page 48 GPIO0 GPIO1 15..4 Reserved ST201 BIT DESCRIPTION This bit controls the GPIO0 pin. When cleared, GPIO0 pin is an input. When set, GPIO0 pin is an output. This bit is cleared on reset. This bit controls the GPIO1 pins. When cleared, GPIO1 pin is an input.
  • Page 49 LSB of HashTable(0) is the least significant bit, addressed by the 6-bit index. If the Hash- Table bit addressed by the index is set, the frame is accepted by the ST201 and transferred to higher layers. If the addressed hash table bit is cleared, the frame is discarded.
  • Page 50 BIT DESCRIPTION This field is used to select the size of Inter-Frame Spacing (IFS). By programming a larger number of bit times for the IFS, the ST201 will become less “ aggressive” on the network and may defer more than normal.
  • Page 51 RxFIFO. The state of RcvFCS does not affect the ST201’ s checking of the frame’ s FCS and its posting of FCS error status. RcvFCS is cleared by a system reset.
  • Page 52 Sundance Technology BIT NAME Paused Reserved The loopback modes available to a host system when using the ST201 are shown in Table 3. Loopback Mode FIFOLoopback FIFO Loopback MAC Loopback External Loopback (MII) or True “ On-wire” External TABLE 3: ST201 Loopback Modes External loopback type is controlled by the Mll PHY device.
  • Page 53 Sets the maximum frame size for received frames. BIT NAME 15..0 MaxFrameSize ST201 BIT DESCRIPTION Received frames with sizes equal to or larger than the value in Max- FrameSize will be flagged as oversize by RxOversizedFrame bit in RxDMAStatus. MaxFrameSize defaults to 1514 upon reset. Upon RxReset, MaxFrameSize is automatically loaded with 1514 or 4491 depending upon the value of RcvLargeFrames in MACCtrl.

  • Page 54: Receive Mode

    Setting this bit causes the ST201 to receive all broadcast frames. Setting this bit causes the ST201 to receive all frames promiscuously. Setting this bit enables the ST201 to receive frames that pass the hash filtering mechanism. Setting this bit enables the ST201 to receive all multicast IP data-...
  • Page 55 StationAddress(2). The value set in the StationAddress register is not inserted into the source address field of frames transmitted by the ST201. The source address field for every frame must be specified by the host system as part of the frame data contents.
  • Page 56 Host systems can use TxFrameId register during transmit error recovery by scanning through the TFD’ s in the TxDMAList, searching for a match between the TxFrameId register value and a FrameId value in the TFD. ST201 BIT DESCRIPTION This register contains the value from FrameId sub-field within the frame’...
  • Page 57 Reserved for future use. Should be set to 0. This bit is asserted if the TxIndicate bit was set when the 32-bit Trans- mitFrameControl was written to the ST201 for the frame. If this bit is cleared, then the remainder of the status bits are undefined.
  • Page 58 Setting this read/write bit enables the ST201 to generate wake events via a PCI interrupt due to Magic Packet reception. MagicPktEnable is set after a ST201 reset. PmeEn must be set in the PowerMgmtCtrl reg- ister in order for MagicPktEnable to be recognized. MagicPktEnable has no effect in power mode D0.
  • Page 59 Transmitting is read-only and set by ST201 whenever the MAC is transmitting or waiting to transmit (deferring). This read-only bit is set whenever the ST201 is receiving a frame into the RxFIFO. No particular action is expected on the part of the host based on the state of this bit.
  • Page 60 12..0 RxEarlyThresh 15..13 Unused ST201 BIT DESCRIPTION The number of bytes which must be present in the RxFIFO before a RxEarly interrupt is asserted. The minimum value is 0x08, any value smaller than this will be interpreted as 0x08. Values greater than 0x08 will be interpreted using a resolution of 4 bytes (i.e.
  • Page 61 TxFrameId. BIT NAME 7..0 TxReleaseThresh ST201 BIT DESCRIPTION The number of 16 byte words which must be transmitted before the space in the TxFIFO occupied by the transmitted data can be released. To avoid excessive release errors due to in-window collisions, value less than 4 should not be written into TxReleaseThresh.
  • Page 62 12..0 TxStartThresh 15..13 Unused ST201 BIT DESCRIPTION The number of bytes which must be present in the TxFIFO before frame transmission begins. Values will be interpreted using a resolu- tion of 4 bytes (i.e. 0x00, 0x04, 0x08, 0x0c, 0x0f, etc.) These bits are ignored.
  • Page 63 Sundance Technology ST201 PRELIMINARY draft 2 COUNTDOWN Class...I/O Registers, Interrupt Base Address ...IoBaseAddress register value Address Offset ...0x48 Access Mode ...Read/Write Width ...16 bits Countdown is a programmable down-counter that will generate an interrupt upon its expiration. If the CountdownIntEnable bit in DMACtrl is set, the IntRequested interrupt will be generated when Countdown counts through zero.
  • Page 64 EnUpdateStats EnLinkEvent EnTxDMACom- plete EnRxDMACom- plete 15..11 Unused ST201 BIT DESCRIPTION This bit will be ignored. Enables the HostError interrupt. Enables the TxComplete interrupt. Enables the MACControlFrame interrupt. Enables the RxComplete interrupt. Enables the RxEarly interrupt. Enables the InRequested interrupt.
  • Page 65 Access Mode ...Read/Write Width ...16 bits IntStatus register indicates the source of interrupts and indications on the ST201. Bits 1 through 10 are the interrupt-causing sources for the ST201. These bits can be individually disabled as interrupt sources using the IntEnable register. The host can acknowledge the interrupt by writing a “ 1” into the indication bit(s), which will cause ST201 to clear the interrupt indication.
  • Page 66 TxDMAComplete RxDMAComplete 15..11 Reserved ST201 BIT DESCRIPTION This bit indicates that a frame TxDMA has completed, and the TFD in question had the TxDMAIndicate bit in its TFC set. This bit can be acknowledged by writing a 1 to this bit. The host should examine the TxDMAListPtr to determine which frame(s) have been transferred by TxDMA.
  • Page 67 LinkEvent ST201 BIT DESCRIPTION Asserted when the ST201 is driving the bus interrupt signal. It is a logi- cal OR of all the interrupt-causing bits after they have been filtered through the IntEnable register. This bit is set when a catastrophic error related to the bus interface occurs.
  • Page 68 TxDMAComplete RxDMAComplete 15..11 Reserved ST201 BIT DESCRIPTION This bit indicates that a frame TxDMA has completed, and the TFD in question had the TxDMAIndicate bit in its TFC set. This bit can be acknowledged by writing a 1 to this bit. The host should examine the TxDMAListPtr to determine which frame(s) have been transferred by TxDMA.
  • Page 69 TxRe- set to clear the under run condition. Before checking TxDMAInProg, issue TxDMAHalt to ensure that TxDMAInProg is not set as a result of the ST201 being in a polling mode. PRELIMINARY draft 2...
  • Page 70 Countdown the host can suppress interrupts. Reserved for future use. Should be set to 0. This read-only bit is set when the ST201 experiences a target abort sequence when operating as a bus master. This bit indicates a fatal error, and must be cleared before further TxDMA or RxDMA operation can proceed.
  • Page 71 BIT NAME BIT DESCRIPTION MasterAbort This read-only bit is set when the ST201 experiences a master abort sequence when operating as a bus master. This bit indicates a fatal error, and must be cleared before further TxDMA or RxDMA operation...
  • Page 72 RxFIFO, in units of 32 bytes. When the used space exceeds the threshold, the ST201 may make a RxDMA request on the PCI bus. However, if the used space exceeds the current RxDMAFragLen, ST201 will make RxDMA bus request regardless of whether the used space exceeds the RxDMABurstThresh or not.
  • Page 73 ST201 as it processes RFDs in the RxDMAList. As the ST201 finishes processing a RFD, it loads RxD- MAListPtr with the value from RxDMANextPtr to allow it to move on to the next RFD. If the ST201 loads a value of zero from the current RFD, the RxDMA engine enters the idle state, waiting for a non-zero value to be written to RxDMAListPtr.
  • Page 74 RxDMAStatus shows the status of various operations in the RxDMA Logic. Host systems should read this register only while the RxDMA engine is in the RxDMAHalt state. Otherwise the ST201 may change RFDs between accesses to this register. The format of this register is identical to that of the ReceiveFrameStatus field written into each RFD, since the content of this register is written into the RFD upon RxDMA frame completion with the exception of the ImpliedBufferEnable bit, which is not implemented in this register.
  • Page 75 Indicates that the RFD had insufficient buffer space for the frame data and there were still data left to be transferred by RxDMA when the ST201 ran out of fragment space. The ST201 will transfer what it can into the buffers provided, discard the remainder of the frame and set this bit.
  • Page 76 The maximum value is 127 (or 40.64 us). BIT NAME 6..0 RxDMAPollPeriod Unused ST201 BIT DESCRIPTION The number of 320ns intervals between polls of the RxDMAComplete bit in the ReceiveFrameStatus field of the current RFD. This bit is ignored.
  • Page 77 The value in RxDMAUrgentThresh sets a threshold at which the RxDMA engine will make a urgent bus master request. A urgent RxDMA request will have priority over all other requests on the ST201. The urgent bus request is made when the free space in the RxFIFO falls below the value in RxDMAUrgent- Thresh.
  • Page 78 TxFIFO. The value in TxDMABurstThresh represents free space in the TxFIFO in multiples of 32 bytes. When the free space exceeds the threshold, the ST201 may make a TxDMA request. However, if the free space exceeds the current TxDMAFragLen, ST201 will make TxDMA bus request regardless of whether the free space exceeds the TxDMABurstThresh or not.
  • Page 79 TxDMAListPtr holds the physical address of the current TxDMA Frame Descriptor in the TxDMAList. A value of zero in TxDMAListPtr is interpreted by the ST201 to mean that no more frames remain to be trans- ferred by TxDMA. TxDMAListPtr can only point to addresses on 8-byte boundaries, so TFD’ s must be aligned on 8-byte boundaries.
  • Page 80 The value in TxDMAPollPeriod represents a multiple of 320 ns time intervals. The maximum value is 127 (or 40.64 us). BIT NAME 6..0 TxDMAPollPeriod Unused ST201 BIT DESCRIPTION The number of 320ns intervals between polls of the TxDMANextPtr field of the current TFD. This bit is ignored. PRELIMINARY draft 2...
  • Page 81 Thresh resets to 4, or a threshold of 128 bytes. BIT NAME 5..0 TxDMAUrgent- Thresh 7..6 Unused ST201 BIT DESCRIPTION The minimum number of 32-byte words which must be occupied in the TxFIFO to avoid assertion of a TxDMA Urgent Request. These bits are ignored. PRELIMINARY draft 2...
  • Page 82 EEPROM’ s WriteEnable, WriteDisable, EraseAll and WriteAll commands can be issued. Two-bit opcodes and 8-bit addresses are written to this register to cause the ST201 to carry out the desired EEPROM com- mand. If data is to written to the EEPROM, the 16-bit data word must be written to EepromData by the host prior to issuing the associated write command.
  • Page 83 Sundance Technology ST201 PRELIMINARY draft 2 EEPROMDATA Class...I/O Registers, External Interface Control Base Address ...IoBaseAddress register value Address Offset ...0x34 Access Mode ...Read/Write Width ...16 bits EepromData is a 16-bit data register for use with the adapter’ s serial EEPROM. Data from the EEPROM can be read by the host from EepromData register after EepromBusy is cleared.
  • Page 84 For writes, the new value will be programmed into the ROM upon comple- tion of the write instruction. BIT NAME 15..0 ExpRomAddr 31..16 Reserved ST201 BIT DESCRIPTION Address used for accessing expansion ROM. Reserved for future use. Should be set to 0. PRELIMINARY draft 2...
  • Page 85 ExpRomData causes the write data to be programmed into the ROM location specified by ExpRomAddr. Note: The Atmel EPROM devices supported by ST201 must be programmed in 64-byte pages. Refer to the Atmel Flash Memory Device data book for information on programming EPROMs.
  • Page 86 MII PHY device. The Management Interface is a two-wire serial interface connecting ST201 to any MII-compliant PHY devices residing on the adapter. The host system operates the Management Interface by writing and reading bit patterns to the PhyCtrl register which correspond to the physical waveforms required on the interface signals.
  • Page 87 Width ...8 bits BIT NAME 7..0 BroadcastFrames- ReceivedOk ST201 BIT DESCRIPTION This statistic counts the number of frames that are successfully received and are directed to the broadcast group address. This does not include frames received with frame-too-long, FCS, length or align- ment errors, or frames lost due to internal MAC error.
  • Page 88 BIT NAME 7..0 Broadcast- FramesTransmitte- ST201 BIT DESCRIPTION This statistic counts the number of frames that are successfully trans- mitted to the broadcast address. Frames transmitted to multicast addresses are excluded from this statistic. This is a 8-bit counter and will wrap around to zero after reaching ffh.
  • Page 89 BIT NAME 3..0 CarrierSenseErrors 7..4 Reserved ST201 BIT DESCRIPTION This statistic register counts the number of times that carrier_sense was not asserted or was de-asserted during the transmission of a frame without collision. Carrier sense is not monitored for the purpose of this statistic until after the preamble and start-of-frame delimiter.
  • Page 90 BIT NAME 7..0 FramesAbortedDu- eToXSColls ST201 BIT DESCRIPTION This statistic counts the number of frames that, due to excessive colli- sions, are not transmitted successfully. This is an 8-bit counter and will wrap around to zero after reaching ffh. An UpdateStats indication will occur after the counter has counted through c0h.
  • Page 91 BIT NAME 7..0 FramesLostRxEr- rors ST201 BIT DESCRIPTION This statistic counts the number of frames that should have been received (the destination address matched the filter criteria) but experi- enced a RxFIFO overrun error due to there not being enough space to hold the frame.
  • Page 92 Width ...16 bits BIT NAME 7..0 FramesReceive- ST201 BIT DESCRIPTION This statistic counts the number of frames that are successfully received. This does not include frames with frame-too-long, FCS, length or alignment errors, or frames lost due to internal MAC error.
  • Page 93 Width ...16 bits BIT NAME 7..0 FramesTransmitte- ST201 BIT DESCRIPTION This statistic counts the number of frames that are successfully trans- mitted. This is a 16-bit counter and will wrap around to zero after reach- ing ffffh. An UpdateStats interrupt will occur, if enabled, after the counter counts through c000h.
  • Page 94 BIT NAME 7..0 FramesWithDe- ferredXmission ST201 BIT DESCRIPTION This statistic counts the number of frames that must delay its first attempt of transmission because the medium was busy. Frames involved in any collisions are not counted by this statistic. This is an 8- bit counter and will wrap around to zero after reaching ffh.
  • Page 95 BIT NAME 7..0 FramesWithExces- siveDeferal ST201 BIT DESCRIPTION This statistic counts the number of frames that deferred for an exces- sive period of time (exceeding the defer limit). This statistic is only incremented once per LLC frame. This is an 8-bit counter and will wrap around to zero after reaching ffh.
  • Page 96 Width ...8 bits BIT NAME 7..0 LateCollisions ST201 BIT DESCRIPTION This statistic counts the number of times that a collision has been detected later than 512 BT into the transmitted frame. A late collision is counted both as a Collision and a LateCollision. This is an 8-bit counter and will wrap around to zero after reaching ffh.
  • Page 97 Width ...8 bits BIT NAME 7..0 MulticastFrames- ReceivedOk ST201 BIT DESCRIPTION This statistic counts the number of frames that are successfully received and are directed to an active non-broadcast group address. This does not include frames received with frame-too-long, FCS, length or alignment errors, or frames lost due to internal MAC error.
  • Page 98 BIT NAME 7..0 Multicast- FramesTransmitte- ST201 BIT DESCRIPTION This statistic counts the number of frames that are successfully trans- mitted to a group destination address other than broadcast. This is a 8- bit counter and will wrap around to zero after reaching ffh. An Updat- eStats interrupt will occur, if enabled, after the counter counts through c0h.
  • Page 99 BIT NAME 7..0 MultipleCollision- Frames ST201 BIT DESCRIPTION This statistic counts the number of frames that are involved in more than one collision and are subsequently transmitted successfully. This is a 8-bit counter and will wrap around to zero after reaching ffh. An UpdateStats interrupt will occur, if enabled, when the counter has counted through c0h.
  • Page 100 19..0 OctetsReceivedOk 31..20 Reserved ST201 BIT DESCRIPTION This statistic counts the total number of frame header, data and pad- ding octets in frames that are successfully received. For the purposes of this statistic, a successfully received frame is one that is completely moved into the RxFIFO.
  • Page 101 19..0 OctetsTransmitte- 31..20 Reserved ST201 BIT DESCRIPTION This statistic counts the total number of frame header, data and pad- ding octets in frames that are successfully transmitted. This is a 20-bit counter and will wrap around to zero after reaching fffffh. An Updat- eStats interrupt will occur after the counter has counted through c0000h.
  • Page 102 BIT NAME 7..0 SingleCollision- Frames ST201 BIT DESCRIPTION This statistic counts the number of frames that are involved in a single collision, and are subsequently transmitted successfully. This is a 8-bit counter and will wrap around to zero after reaching ffh. An UpdateStats interrupt will occur after the counter has counted through c0h.

  • Page 103: Pci Configuration Registers

    Configuration Cycles are directed at one out of eight possible PCI logical functions within a single physical PCI device. A ST201 based PCI bus master device responds only to Type 0 Configuration Cycles, directed at function 0. Type 1 cycles, and Type 0 cycles directed at functions other than 0, are ignored by the ST201.
  • Page 104 Sundance Technology byte 3 Reserved PowerMgmtCap MaxLat Reserved SubsystemId Reserved HeaderType ClassCode ConfigStatus DeviceId FIGURE 12: ST201 PCI Register Layout ST201 byte 2 byte 1 Reserved Reserved Reserved PowerMgmtCtrl NextItemPtr Reserved Reserved Reserved Reserved MinGnt InterruptPin Reserved ExpRomBaseAddress SubsystemVendorId Reserved...
  • Page 105 Width ...8 bits BIT NAME 7..0 CacheLineSize ST201 BIT DESCRIPTION The system BIOS writes the system’ s cache line size into this register. The adapter uses this to optimize PCI bus master operation (choosing the best memory command, etc.). The value in CacheLineSize repre- sents the number of dwords in a cache.
  • Page 106 Width ...8 bits BIT NAME 7..0 CapPtr ST201 BIT DESCRIPTION This is a hard-coded value pointing to the beginning of a chain of regis- ters that describe enhanced functions. The CapPtr register returns 50h, which points to the power management registers.
  • Page 107 Base Address ...PCI device configuration header start Address Offset ...0x09 Access Mode ...Read Only Width ...24 bits BIT NAME 23..0 ClassCode ST201 BIT DESCRIPTION This register identifies the general function of the PCI device. The ST201 returns 020000h, indicating Ethernet network controller. PRELIMINARY draft 2...
  • Page 108 Reserved SERREnable 15..9 Reserved ST201 BIT DESCRIPTION Setting this bit allows the adapter to respond to I/O space accesses (if the adapter is in the D0 power state). Setting this bit along with AddressDecodeEnable in ExpRomBaseAd- dress allows the adapter to decode accesses to its Expansion ROM, if one is installed, and if the adapter is in the D0 power state.
  • Page 109 This read-only field is used to encode the slowest time with which the adapter asserts the DEVSELN signal. ST201-based adapters return 01b, indicating that they support “ medium” speed DEVSELN assertion. The adapter sets this bit when it terminates a bus transaction with tar- get-abort.
  • Page 110 Base Address ...PCI device configuration header start Address Offset ...0x02 Access Mode ...Read Only Width ...16 bits BIT NAME 15..0 DeviceId ST201 BIT DESCRIPTION This register contains the 16-bit device ID for the ST201. It is hard- wired to 0201h. PRELIMINARY draft 2...
  • Page 111 14..1 Reserved 31..15 RomBaseAddress ST201 BIT DESCRIPTION When this bit is cleared, the adapter’ s Expansion ROM is disabled. Setting this bit causes the adapter to respond to accesses in its config- ured expansion ROM space, if MemorySpace in the ConfigCommand register is also set.
  • Page 112 Address Offset ...0x0e Access Mode ...Read Only Width ...8 bits BIT NAME 7..0 HeaderType ST201 BIT DESCRIPTION This register is hard-wired to 00h, identifying the ST201 as a single- function PCI and specifies the configuration register layout. PRELIMINARY draft 2...
  • Page 113 Width ...8 bits BIT NAME 7..0 InterruptLine ST201 BIT DESCRIPTION This register is written by the system to communicate to the device driver which interrupt level is being used for the device. This allows the driver to use the appropriate interrupt vector for its ISR. For 80x86 sys-...
  • Page 114 Access Mode ...Read Only Width ...8 bits BIT NAME 7..0 InterruptPin ST201 BIT DESCRIPTION This register indicates which PCI interrupt pin the adapter will use. ST201-based adapters always use INTAN, so 01h is returned in Inter- ruptPin. PRELIMINARY draft 2...
  • Page 115 The host uses this register to define the I/O base address for the adapter. PCI system requires that I/O base addresses be set as if the system used 32-bit I/O addressing. The upper 25 bits of the register are read/write accessible, indicating that the ST201 requires 128 bytes of I/O space in the system I/O map. BIT NAME IoBaseAddrInd 6..1...
  • Page 116 Whenever the ST201 asserts FRAMEN, the latency timer is started. When the timer count expires, the ST201 must relinquish the bus as soon as its GNTN signal has been negated. The granularity of the timer is 8 bus clocks.
  • Page 117 MaxLat ST201 BIT DESCRIPTION MaxLat specifies, in 250 ns increments, how often the ST201 requires bus access while operating as a bus master. The value for MaxLat is stored in the ConfigParm word in EEPROM. Assumes the PCI system allows 64-byte maximum bursts with full duplex operation, the ST201- based 100 Mbps systems return the value 10 in this field, implying a latency tolerance of 2.5us, according to the calculation:...
  • Page 118 6..3 Reserved 31..7 MemBaseAddress ST201 BIT DESCRIPTION A value of 1 indicates this register is the memory base address. These are read-only bits, and [2] is hard wired to 0. Bit[1] is loaded from EEPROM Lower1Meg bit of the ConfigParm. When set to 01, instructs the host system to map the adapter registers into the lowest 1 megabyte of memory address space.
  • Page 119 MinGnt specifies, in 250 ns increments, how long a burst period the adapter requires when operating as a bus master. The value for MinGnt is stored in the ConfigParm word in EEPROM. ST201-based PCI systems return the value 10 in this field. This assumes a 33 MHz bus (30 ns clock period), 1 clock for address phase, 10 clock latency to first data phase, then no wait states for the 64 remaining data phases.
  • Page 120 Width ...8 bits BIT NAME 7..0 RevisionId ST201 BIT DESCRIPTION This register provides a revision code for the ST201. The first ST201 will return 00h. Future revisions of the chip will cause this value to be incremented. PRELIMINARY draft 2...
  • Page 121 Sundance Technology ST201 PRELIMINARY draft 2 SUBSYSTEMID Class...PCI Configuration Registers, Configuration Base Address ...PCI device configuration header start Address Offset ...0x2e Access Mode ...Read Only Width ...16 bits BIT NAME BIT DESCRIPTION 15..0 SubsystemId This is the value read from EEPROM word 03h after system reset.
  • Page 122 Class...PCI Configuration Registers, Configuration Base Address ...PCI device configuration header start Address Offset ...0x2c Access Mode ...Read Only Width ...16 bits BIT NAME 15..0 SubsystemVen- dorId ST201 BIT DESCRIPTION This value is read from EEPROM location 02h after system reset. PRELIMINARY draft 2...
  • Page 123 Access Mode ...Read Only Width ...16 bits BIT NAME 15..0 VendorId ST201 BIT DESCRIPTION This register contains the unique 16-bit manufacturer’ s ID as allocated by the PCI SIG. Sundance’ s manufacturer ID is hard-wired to 0x13f0. PRELIMINARY draft 2...
  • Page 124 Base Address ...PCI device configuration header start Address Offset ...0x50 Access Mode ...Read Only Width ...8 bits BIT NAME 7..0 CapId ST201 BIT DESCRIPTION This register indicates the type of capability data structure. It returns 01h to indicate a PCI Power Management structure. PRELIMINARY draft 2...
  • Page 125 Access Mode ...Read Only Width ...8 bits BIT NAME 7..0 NextItemPtr ST201 BIT DESCRIPTION This register points to the next capability data structure in the capabili- ties list. It returns 00h to indicate that there are no further data struc- tures.
  • Page 126 Power management events can be generated from D3hot. 1xxxx: Power management events can be generated from D3Cold. The ST201 hard-wires bit 11 to zero and bit 14 to one. The values of bits 12,13, and 15 are determined by bits 4, 5 and 3 respectively from the EEPROM ConfigParm.
  • Page 127 01: State D1 10: State D2 11: State D3 If PowerState is set to a non-zero value, the ST201 will not respond to PCI I/O or memory cycles, nor will it be able to generate PCI bus mas- ter cycles.

  • Page 128: Eeprom Data Format

    Sundance Technology EEPROM DATA FORMAT Figure 13 summarizes the layout of the EEPROM. ST201 byte 1 byte 0 StationAddress2 StationAddress1 StationAddress0 SubSystemId SubSystemVendorId AsicCtrl ConfigParam FIGURE 13: EEPROM Data Layout PRELIMINARY draft 2 Offset 0x14 0x12 0x10 0x06 0x04 0x02...
  • Page 129 Class...EEPROM Data Format Base Address ...0x00, address written to EepromCtrl register Address Offset ...0x00 Access Mode ...Read Only Width ...16 bits This is loaded into the ST201 and controls various hardware functions related to PCI bus operation. BIT NAME FastBackToBack Lower1Meg DisableMemBase...
  • Page 130 15..0 StationAddress0 31..16 StationAddress1 47..32 StationAddress2 ST201 BIT DESCRIPTION The least significant word of the station address, corresponding to address 0x10. The second least significant word of the station address, correspond- ing to address 0x12. The most significant word of the station address, corresponding to address 0x14.
  • Page 131 1 = 64 kB This read/write bit, when set, enables transmission of frames that are larger than the TxFIFO. Since ST201’ s TxFIFO size is 2KB, this bit can be left clear (the reset default). This read/write bit, when set, enables reception of frames that are larger than the RxFIFO.
  • Page 132 Sundance Technology BIT NAME 14..8 Reserved ResetPolarity ST201 BIT DESCRIPTION Reserved for future use. Should be set to 0. Setting this read/write bit will cause the RSTOUT pin to be asserted in the HIGH state (default after RESET). PRELIMINARY draft 2...
  • Page 133 Base Address ...0x00, address EepromCtrl register BIT NAME 15..0 SubsystemVen- dorId ST201 Address Offset ... 0x04 Access Mode... Read Only written Width ... 16 bits BIT DESCRIPTION This is the two-byte subsystem vendor ID. Since in this case the sub- system is an adapter, customers needs to use their PCI vendor ID.
  • Page 134 Class...EEPROM Data Format Base Address ...0x00, address EepromCtrl register BIT NAME 15..0 SubsystemId ST201 Address Offset ... 0x06 Access Mode... Read Only written Width ... 16 bits BIT DESCRIPTION This is the two-byte subsystem ID for the adapters, the same code as the DeviceId is used.

  • Page 135: Absolute Maximum Ratings

    Functionality at or above the limits listed below is not guaranteed. Exposure to the environmental stress at the levels listed below for extended periods may adversely affect device reliability. ST201 PRELIMINARY draft 2 OPERATING RANGES Commercial Devices Temperature (T ) ...
  • Page 136 Output low voltage Output leakage current PIN TYPE OP6 (PCI OUTPUT BUFFER FOR PCI I/O WITH PULL UP) Output high voltage Output low voltage Output leakage current ST201 TEST CONDITIONS = -4mA = 4mA = -2mA = 3mA = -2mA...
  • Page 137 EWEN, EOEN, EA[15:0] EEDO EEDI, EESK, EECS TXCLK, CRS, COL, RXER, RXDV, RXD[3:0], RXCLK PHYLNKN, PHYSPDN, PHYDPLXN TXD[3:0], TXEN, MDC IT/OT4 MDIO ST201 TEST CONDITIONS = 6mA = 8mA TABLE 4: DC Characteristics PINS PCI INTERFACE EXPANSIONROM INTERFACE EEPROM INTERFACE...
  • Page 138 Sundance Technology PIN TYPE ITU/OT4 GPIO0, GPIO1 RSTOUT LEDPWRN, LEDLNKN, LEDDPLXN, LEDSPDN CLK25 OSCI X25I OSCOH1 X25O ST201 PINS MISC INTERFACE TABLE 5: Pin Type Assignment PRELIMINARY draft 2...

  • Page 139: Switching Characteristics

    EXPANSION ROM INTERFACE - LOAD EA, EOEN setup wrt EWEN fall EA hold wrt EWEN fall ED setup wrt EWEN rise ED, EOEN hold wrt EWEN fall ST201 TEST CONDITIONS PCI INTERFACE TABLE 6: Switching Characteristics PRELIMINARY draft 2 UNIT...
  • Page 140 RXCLK cycle RXCLK high RXCLK low RXD,RXER,RXDV setup wrt RXCLK rise RXD,RXER,RXDV hold wrt RXCLK rise ST201 TEST CONDITIONS EEPROM INTERFACE MII INTERFACE - TRANSMIT T = 1 when 100Mb/s; 10 when 10Mb/s MII INTERFACE - RECEIVE T = 1 when 100Mb/s; 10...
  • Page 141 MDC low MDIO setup wrt MDC rise MDIO hold wrt MDC rise MDC rise to MDIO valid CLK25 cycle CLK25 high CLK25 low ST201 TEST CONDITIONS MII INTERFACE - MANAGEMENT MISC INTERFACE TABLE 6: Switching Characteristics PRELIMINARY draft 2 UNIT...
  • Page 142 Sundance Technology RSTN PCICLK BUSSED SIGNALS REQN GNTN ANY SIGNAL ANY SIGNAL FIGURE 14: PCI Switching Characteristics EOEN EWEN EA[15..0] ED[7..0] FIGURE 15: Expansion ROM Switching Characteristics ST201 sup2 sup1 Read PRELIMINARY draft 2 rstoff Load...
  • Page 143 Sundance Technology ST201 PRELIMINARY draft 2 EECS EESK EEDI EEDO FIGURE 16: EEPROM Switching Characteristics...
  • Page 144 Sundance Technology TXD[3..0] TXEN TXCLK RXD[3..0] RXER RXDV RXCLK MDIO FIGURE 17: MII Switching Characteristics ST201 Transmit Receive Management PRELIMINARY draft 2...

  • Page 145: Physical Dimensions

    Sundance Technology ST201 PRELIMINARY draft 2 PHYSICAL DIMENSIONS Copyright Sundance Technology, Inc., 1998. The information contained in this data sheet is subject to change without notice. Sun- dance Technology assumes no responsibility for the use of any circuitry other than circuitry embodied in a Sundance Technology product.

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