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Summary of Contents for Designsoft TINALab II
- Page 1 A Quick Start To FPGA Development Kit TINALab II 2009 www.designsoftware.com...
- Page 3 Xilinx Spartan-II FPGA family. The kit can be physically connected to the User Port of TINALab II or can be used stand alone with an external power supply, a Xilinx JTAG programming cable and the free Xilinx ISE WebPACK software.
- Page 4 TINALAB SPARTAN-II DEVELOPMENT KIT CONNECTED TO TINALAB II TINA > Schematic and VHDL based circuit simulator > Measurement control > Virtual instruments Xilinx ISE WebPACK > Implementing FPGA > Create download file TINALab II > High speed multifunctional PC instrument >...
- Page 5 VHDL DESIGN FLOW Design Entry (schematic or VHDL) RTL level Simulation Synthesis Place & Route Results in TINA Diagram Window Configuration Download Virtual Instruments Digital Signal Generator Logic Analyzer TINALab Spartan-II FPGA Card...
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Page 6: Onboard Headers And Connectors
Multilink connector (JTAG, configuration link, JTAG chain broker) PS2 port VGA port Power supply and configuration jumper Close pin 1-2 to be powered by TINALab II, 2-3 by external +5V. FPGA configuration jumpers R/2R Ladder DAC output PROM interface jumper... -
Page 7: Configuration Support
4. Close JP4 pin 2 to 3 and JP1 pin 1 to 2 5. Switch off TINALab II 6. Connect TINALab II User Port to that of TINALab FPGA card (J4) with the 14-wire wide cable 7. Connect TINALab II Digital Outputs to the TINALab II Digital Signal Generator Connector (J2) 8. - Page 8 In any case, remove TINALab II User Port Connection if it has been used before and close JP1 pin 2 to 3 for the powering. The other steps are depending on the configuration method found in detail the later description. In every mode the last step is to connect the external power supply.
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Page 9: User Resources
SLAVE PARALLEL The Slave Parallel mode is the fastest configuration option. Byte-wide data is written into the FPGA through the Multilink and J3 connector. Set JP2 and close JP4 pin 2 to 3. USER RESOURCES CLOCK SOURCES A 50 MHz SMD oscillator (mounted on the bottom side of the PCB) provides the primary clock source for the TINALab FPGA Board. -
Page 10: Slide Switches
NET "switch<7>" PULLUP; Internal pull-up resistor USER LED The TINALab II FPGA board provides eight user LEDs. NET "LED0" LOC = "P10"; LED is ON when signal is low NET "LED1" LOC = "P7"; LED is ON when signal is low NET "LED2"... -
Page 11: Rs232 Serial Port
PC serial port, so a null modem cable that swaps the TXD/RXD and CTS/RTS lines is needed if the TINALab II FPGA board and PC are to communicate. The user provides the RS232 UART code, which resides in the Spartan-II FPGA. -
Page 12: Vga Display Port
VGA DISPLAY PORT The FPGA can generate a video signal for display on a VGA monitor. When the FPGA is generating VGA signals, the FPGA outputs two bits each of red, green, and blue color information to a simple resistor-ladder DAC. The outputs of the DAC (J11) are sent to the RGB inputs of a VGA monitor along with the horizontal and vertical sync pulses (/HSYNC, /VSYNC) from the FPGA. - Page 13 LOC = "P60"; NET "DIn<15>" LOC = "P64"; The following pins can be connected to TINALab II Logic Analyzer by a ribbon cable through J1 block header as outputs or can be used freely as generic I/O. NET "DOut<0>" LOC = "P118";...
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Page 14: Quick Start
TINALab II Digital Signal Generator and Logic Analyzer. TINA provides code developing, simulation and measurement control with TINALab II, which does power supplies and signal link. - Page 15 8. Add the vhd and ucf files as existing sources to the projects. Click Next until Finish. 9. Select the e_FULL_ADD_entity-a_FULL_ADD_arch architecture source in the “Sources in Project” window, and then click the right button on “Generate Programming File” in the Process window.
- Page 16 In a mixed environment, where the circuitry is not pure digital, follow the steps below. 1. Connect TINALab II with your XC2S FPGA card as described under TINALab II User Port on page 7. 2. Open the \EXAMPLES\VHDL\FPGA\FPGA_Wave_Generator.TSC sample design.
- Page 17 ChA input of TINALab II with the supplied probe to JP3, the ladder DAC output. Note, the switch in the probe handle must be in 10X attenuation. For the correct displaying, set the probe attenuation in the software also: T&M >...
- Page 18 7. Stop the oscilloscope then click on the Export curves button. The Diagram Window will come up. Copy the curves into the same diagram. 4.00 Simulated Simulated Measured Measured 0.00 0.00 25.00u 50.00u 75.00u 100.00u TINALab FPGA Quick Start DesignSoft Inc. REV. E http://www.designsoftware.com...
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