- 07/97 - ICC19 CHASSIS TELEVISION SETS: PRINCIPLES AND MAINTENANCE.
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Summary of Contents for Technicolor - Thomson ICC19
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Code : 3504.93.50 - 07/97 - ICC19 CHASSIS TELEVISION SETS: PRINCIPLES AND MAINTENANCE. No copying, translation, modification on other use authorized. All rights reserved worldwide. • Tous droits de reproduction, de traduction, d'adaptation et d'exécution réservés pour tous les pays. • Sämtliche Urheberrechte an diesen Texten und Zeichnungen stehen uns zu. Nachdrucke,...
CONTENTS • IR001 POWER SUPPLY AND OPERATIONAL SIGNALS • DATA MANAGEMENT • CONTROLS • RMICROCONTROLLER/EPROM COMMUNICATION • BUSES • BUS EXPANDER MANAGEMENT • OTHER CONTROLS • SWITCH-ON PROCEDURE • FRONT PANEL LED CONTROL • OFF/ON TIMING DIAGRAM • ERROR CODES CENTRE DE FORMATION TECHNIQUE...
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IR001 POWER SUPPLY AND OPERATIONAL SIGNALS NOTES : POWER SUPPLY The power supply to the microcontroller at Pin 23 is active when the IP130 regulator (which produces a 10VSTBY) and the IP140 regulator (which produces a 5VSTBY from the 10VSTBY) are on Standby. When they are On, the 13 V (LINE) supply takes over from the 10VSTBY.
DATA MANAGEMENT NOTES : ICC19 chassis are 50-Hz or 100-Hz compatible. They are controlled by an 8- bit microcontroller, the ST90R92. It communicates via an address and data bus with its external program memory, an EPROM, IR002, with a basic capacity of 256 KB that can be extended to 1024 KB.
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RR037 IR001 5VSTBY RR044 INFO VOL+ RR035 MENU VOL- RR034 PROG+ MUTE KEY OUT RR033 PROG- EXIT INSTALL RR032 RR924 OPTION RR045 5VSTBY KEY IN CENTRE DE FORMATION TECHNIQUE...
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CONTROLS NOTES : KEYPAD The keypad is compatible with previous ICC10/11 chassis. It can support four to 10 control keys. It is laid out in a matrix of rows and columns. Pins 58 through 60 are the function inputs. They are at 5 V when idle. Pins 35 through 38, which are labelled A, B, C, and D, are the sweep outputs.
5VSTBY 1 - 32 15 bits 4 à 12 1 à12 A0 - A14 66 à 68 25 à 29 BS00 BS01 IR001 IR002 µ C EPROM BS04 BS05 8 bits 13 à15 15 à 22 D0 à D7 17 à 21 Data strobe line DS CENTRE DE FORMATION TECHNIQUE...
REMOTE CONTROL UNIT NOTES : ADDRESSING The IR002, memory for the software and default values, is an EPROM with capacity up to 512 KB or 4 Mbits. The 8-bit ST90R92 microcontroller has an address bus (A0-A14) limited to 15 bits. This provides addressing of only 32 KB. Page-swapping is therefore necessary.
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BUSES NOTES : The IIC1 bus is charged by pull-up resistors connected to the +5VSTBY. It is active in Standby and On Modes. It dialogs with the IR003 NVM (M24C32) to store the user parameters. It distributes its commands to the SCART switching circuits, the Audio Module, and the sweep and video processor (IV001).
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RR103 SAFE TV_OFF TR102 RR910 IR01 µC DR091 MUTE CENTER C MUTE MARK_E_TING DR090 MUTE 13V (L) sensor RR042 (A/D) RR043 (A/D) AV1 (8) AV2 (8) (A/D) FB_DET (A/D) ZOOM /E-FIELD (PWM) SAT_0N (A/D) CENTRE DE FORMATION TECHNIQUE...
OTHER CONTROLS NOTES The function of Pin 27 is to switch the power supply separately from the satellite tuner. Pin 40 is used to switch off the television set using a control independent of the buses. This is very useful in the event of the buses being blocked. The breathing line is pulled down via Transistor TR102.
FRONT PANEL LED CONTROL SWITCH-ON PROCEDURE In Standby Mode, Pin 51 of microcontroller IR001 is in high impedance. The 10VSTBY from the power supply is used. This is limited to 5 V by a Zener Switching transistor TR002 powers the red LED from the 5 V STBY. diode inside the IV001, and powers its IIC1 bus interface.
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OFF to ON CHRONOGRAM 10v STBY 5v STBY Reset DRIVE 40ms Init. I CUT IIC1 IV001 100ms 0,5ms 400ms 100ms TV-OFF H-DRIVE IIC2 +13v Power fail +1,2V Interrupt Mute M-Reset Mute C ORANGE GREEN...
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ERROR CODES LIST OF ERROR CODES CODE ERROR CODE ERROR These error codes are displayed by the red LED. They are displayed only if the management microcontroller is operating. NO WARM TUBE SIGNAL ACR MSP3410 A maximum of 81 codes (11 through 99) can be signalled. These codes consist AFTER 15 s of two digits separated by a 0.7-second pause.
CONTENTS INTRODUCTION PRINCIPLE CHARACTERISTICS LP020 POWER SUPPLY INTEGRATED CIRCUIT TEA2261 SECONDARY REGULATION POWER SUPPLY POWER SUPPLY INTERLOCKS MAINS POWER CUT DETECTION CENTRE DE FORMATION TECHNIQUE...
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INTRODUCTION NOTES : The ICC19 power supply comes in two main versions: one operating at 16 kHz, and the other operating at 32 kHz. The main difference lies in the choice of components. PRINCIPLE IThe power supply is a fixed-frequency flyback-type switching power supply unit.
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220VAC 220VAC D1 conduction level when T1 is ON Narrow current pulse including a high harmonic level Without PFC With PFC WITH PFC CIRCUIT WITHOUT PFC CIRCUIT CENTRE DE FORMATION TECHNIQUE...
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LP020 POWER SUPPLY NOTES : The new European standard, EN60555-2, limits pollution of the mains voltage by harmonics. For this purpose, the main primary winding is connected to the bridge rectifier via a power factor correction circuit. PRINCIPLE Harmonics are generated by the filter capacitor charging current. The narrower the charge pulse, the higher the amplitude of the harmonics (this occurs with a weak voltage residual and therefore a high capacitor value).
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NOTES : APPLICATION A filter, CP15, CP018, and LP15, eliminates the mains pollution generated by the line frequency switching of Diode DP019 (D1). Diode DP16 protects CP15 (C1) against voltage spikes on the mains. Diode DP018 limits the collector overvoltage of TP060 (T1) when diode DP019 is blocked.
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AMPLIFIER ERROR INNER 2,5v 15,7 V POLARISATION SAFETY INNER OVER 2,5 V VOLTAGE REF. α POSITIVE GENERATOR SOFTWARE "BURST" CONTROL REGULATION STBY SOFT β NEGATIVE ORDER STARTING OVER VOLTAGE PROTECTION LIMITATION 4,5 µA SOFT STBY START OSC. 2,6 V 0,9 V 0,15 V 0,6 V 10 µA...
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INTEGRATED CIRCUIT TEA2261 NOTES : TEA2261 incorporates the various stages required for control and regulation of a switching power supply unit. It includes the following: Internal voltage reference and regulation circuit Error oscillator Error amplifier Pulse width modulator (PWM) Gradual start circuit Transformer degaussing control Current limiting threshold detection Logic management of limits and interlocks...
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220VAC LP020 RECTIFIER 300VDC FILTER CP020 RP030 à RP025 RP032 360k RP050 IP050 DP050 DP052 7809 CP052 CP054 RP055 10µ DP051 470µ RP054 CP056 DP053 47µ + Vcc CP055 CP054 PROTECTION 470µ OVER VOLTAGE Output power supply Vcc MAX. RP029 15,7 V 100k SIGNAL...
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GENERATION OF INTERNAL REFERENCES AND POWER SUPPLIES NOTES : The power supply at Pin 16 comes from: On start-up, half-wave rectification of the mains by the mesh RP025, CP054, and a diode of the bridge rectifier. In Standby Mode, winding 9, 8 of LP020 (fly-back mode). 12 V obtained by rectification (DP050, CP054) is applied to regulator IP050 (7809 applied to Diode DP051), which supplies 9 V via DP052.
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OPTIONS NOTES : SWITCHING OF START-UP POWER SUPPLY On 100-Hz chassis, a thyristor (TP025) is added in series with Resistor RP025. When mains power is applied, a current from the 300 V via the RP028, RP030 through 32 resistor network energises the thyristor. The thyristor then channels the CP054 charging current.
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OSCILLATOR NOTES : An oscillator determines the switching frequency of the switching device in Standby Mode. It includes the following: - Current (Q1, Q1', Q2) generator; value of current set by Resistor RP061 (Pin 11). This current charges Capacitor CP060 (Pin 10). Threshold detector which analyses the voltage across CP060: •...
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DP061 Output power supply LP020 300V V REF. V REF. : 2,5 x 0,9 = 2,5V SPECIAL 2,25 V SOFT 1 ; 0,9 U err α TP060 ERROR Output AMPLIFIER β Safeties U int CP064 PULSES GENERATOR RP065 Threshold Safeties T on (1µs) OSC.
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PRIMARY REGULATION LOOP NOTES : This includes an error amplifier that compares a fraction of the image of the secondaries (Winding 8, 9, RP050, DP050, CP051, RP066, RP064) to an internal reference. Resistor RP065 sensitises the primary circuit in Standby Mode. In Steady State, because the secondary regulations brings the voltage at Pin 6 to approximately 4V7, the primary regulation is in a constant overvoltage configuration, and automatically shuts itself off.
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LOGICAL IS STAGE. NOTES : During the transition between Standby and Steady State, the two regulation loops coexist. Because the signals are not synchronous, there is a risk of a Transistor TP060 command during the energy restoration phase, and of the interlock being triggered by a current peak.
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A voltage above 15V7 on Pin 16 blocks TP060. A main reset is then necessary to re-start the circuit (V Pin 16 5V5). SPECIFIC FEATURES OF ICC19 CHASSIS Because the primary interlock is calibrated for U SYS at steady state, the sensitivity of this stage has been increased in Standby Mode to detect faults on the other secondaries.
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TP060 ENVIRONMENT NOTES : OUTPUT STAGE The output stage of the TEA2261 consists of a push-pull. It supplies the basic current for control of TP060, and then channels the reverse locking current caused by the discharging of CP040. In the conduction phase, Resistor RP054 limits the polarisation current. TP060 SWITCHING CIRCUITS Resistors RP029 through RP032 pre-charge CP040 as soon as power is switched on, to ensure an adequate reverse locking current during the start-...
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SECONDARY VOLTAGES NOTES : The secondary windings produce five direct voltages: +USYS which can be between 127 and 140 volts, according to chassis, and according to the winding connector selected (19 through 22 via jumpers JP914 through 917). +US and -US, symmetric power supplies with specific earth distributed to the audio stage via a cable (from BP120).
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+ 13V +U13 LP020 DP140 LL008 RP148 RL040 CP140 (THT) LL045 DL041 ZL041 18 k 0R27 4700µF IP140 TDA8139 CL045 CL042 RP149 470µF 1000µF TP146 + 5 V CP143 470µF RP143 CP146 2k32 10µF Prog. RP142 2k21 VOLTAGE ELABORATION + 5 V (50 Hz Dolby / 100 Hz VERSION) CENTRE DE FORMATION TECHNIQUE...
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IR001 ST90R92 31/32 LP020 DP110 19/20/21/22 300V U SYS I2C1 IV001 CP110 STV2161/2162 Sécurités BREATHING VCC1 Alimentation Sécurité RV242 Bases de temps RV213 CV243 H REF RL081/82 fl CV242 470p TP060 (CL030/038) 470n CSOFT DP140 Régulation CV246 SMPS IN 220n RL080 IP060 +10V...
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NOTES : SECONDARY REGULATION This mode is adopted as soon as Steady-State Mode begins. It regulates voltage USYS. A fraction of USYS, tapped off by divider bridge RL082, RL081, and RL080, is applied to Pin 31 of IV001 (SMPS IN). This information is compared to an internal reference whose value can be adjusted according to operating mode (USYS adjusted in 64 steps within a 16-V range).
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POWER SUPPLY INTERLOCKS NOTES : Overloads and short circuits are detected by analysing the primary current in the emitter resistor of TP060 (input at Pin 3 of circuit IP060). The sensitivity of this stage was increased in Standby Mode to detect errors in the low-voltage secondaries (RP065, TP027, and RP059).
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DETECTION OF MAINS POWER FAILURE NOTES : In the event of mains power failure, the microcontroller must be informed promptly so that the data in the NVM (IR003) can be saved, and to avoid a plop in the speakers (sound mute). To do this, POWER FAIL has a rising edge in the event of mains power failure in ON Mode, and a falling edge in the event of mains power failure in Standby Mode.
CONTENTS INTRODUCTION PRODUCTION OF H-DRIVE COMMAND IN STV2161 SPECIFIC FEATURES OF STV2162 DRIVER STAGE EHT AND LINE POWER EW STAGE FRAME SWEEP TIME BASE INTERLOCKS TIME BASES CENTRE DE FORMATION TECHNIQUE...
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INTRODUCTION NOTES : Time base commands are produced by the IV001 video processor: STV2161 for the 50-Hz chassis. STV2162 for the 1006Hz chassis. Apart from the difference in frequency, the difference between these two circuits is in the internal oscillator, which is used constantly in the STV2161, but only for start-up in the STV2162 (an external 27-MHz signal then takes over).
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SPECIFIC FEATURES OF STV2162 NOTES : For the STV2162, the separation of synchronisation pulses has already been performed by circuit TDA9143 of the video module (50/100 Hz). This module supplies line and frame synchronisation signals, after conversion, with a clock: VDFL Pin 6 of IV001, 64-µs square signal for a period of 10 ms.
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DRIVER STAGE NOTES : At the IV001 circuit output, the H DRIVE command goes through a low-pass filter that reduces interference caused by steep edges (RV216/CV216). The line transistor command is issued via a driver transformer operating in Forward Mode. A positive or negative current constantly passes through its primary.
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EHT AND LINE POWER NOTES : The primary of LL008, which is powered by voltage +USYS, is associated with line power transistor TL030 and diode modulator DL030, DL032, CL031, CL032. These switching elements also channel the current from the horizontal deflector connected in series with the capacitor of S, CL037, and linearity self-induction coil LL037.
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LL008 RL052 BEAM INFO DL023 RL053 RL044 CL023 RL050 RL023 DL030 CL031 RL020 RL025 LL029 470R RL026 EW BACK RL129 CL029 CL032 RL024 VERTICAL DL032 IV001 SIGNAL CL028 GENERATOR RL027 470R EW DRIVE PARABLE GENERATOR CL027 CENTRE DE FORMATION TECHNIQUE...
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EW STAGE NOTES : Circuit IV001 incorporates the E/W parabolic signal generator which is synchronised by the vertical ramp generator. Adjustments are therefore made via Operating Mode, and are routed via Bus I2C. An amplifier also incorporated in IV001 delivers an EW DRIVE command in the form of a current on Pin 32.
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DF033 VERT DF007 CF031 CF029 CF027 100n 470µ 100n IV001 RF036 DF031 DF028 SOFT H RF007 SOFT V RV233 CF028 FRAME DR VERTICAL 1µ DF011 SIGNAL GENERATOR RF011 CF002 IF001 RF020 TDA8177F SAFETY RF002 VERT RF003 CV234 CF021 CF011 RV232 RF023 100n 470n...
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FRAME SWEEP NOTES : Two circuits are involved in the frame sweep. IV001 (STV2161 or STV2162) produces a frame sawtooth signal. IF001 (TDA8177F) amplifies this signal, and delivers the current to the frame deflector. Video scanning processor IV001 includes a vertical ramp generator that uses Capacitor CV234 (Pin 29).
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TIME BASE INTERLOCKS NOTES : The interlock circuit detects short circuits in the line voltages or sweeps, disconnection of the deflectors, or racing of the beam current or EHT voltage. The frame deflector signal supplies a voltage that polarises Zener Diode DL071 and saturates Transistor TP175 via the SAFE line.
CONTENTS • CTT5000T TUNER • INTERMEDIATE FREQUENCY HIGH FREQUENCY INTERMEDIATE FREQUENCY CENTRE DE FORMATION TECHNIQUE...
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RH010 From 19 to II050 From 33/34 to IR001 From Power supply RH007 RH008 USYS DH001 to TI020 CENTRE DE FORMATION TECHNIQUE...
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CTT5000T TUNER NOTES : The CTT5000T tuner is equipped with a frequency synthesiser. It covers the following frequency bands: • Band 1: 48.25 MHz to 112.25 MHz • Band 3: 119.25 MHz to 399.25 MHz • Bands 4 and 5: 407.25 MHz to 863.25 MHz The following table gives information about the pins of this tuner.
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INTERMEDIATE FREQUENCY The NICAM and FM audio intercarriers are available on Output 20 of II050. They are amplified by TI070 via Switching Diodes DI070 (NICAM 5.85 MHz) and DI071 (FM), and are sent to the demodulation stage (MSP3410). Created using three surface wave filters and an integrated circuit: The HF AGC voltage is available on Output 19 of II050.
CONTENTS • VIDEO SWITCHING • AUDIO SWITCHING • RGB SWITCHING SWITCHING CENTRE DE FORMATION TECHNIQUE...
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from front panel sockets sat. BX500 BX400 RX406 SCI MODULE RX403 BX803 TX505 RX330 IR - LINK RX331 TX650 TX620 à à RX803 TX652 TX622 AMPLI AMPLI TX830 à TX833 RX802 RX801 BX001 BX002 AV2- 8 EXT- LINK AV1- 8 IR001 IX900 Y/V2...
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VIDEO SWITCHING FUNCTION INPUT OUTPUT Integrated Circuit IX900 performs the switching of eight input sources (VIDEO or Y/C) to six outputs. Microcontroller IR001 controls this switching 13 of IX900 via Bus IIC1. 15 of IX900 20 of IX900 The values of the voltages from Pins 8 of the SCART connectors, arriving at 16 of IX900 Pins 44 and 45 of Microcontroller IR001, indicate whether the source is 4/3 18 of IX900...
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from front panel sockets BX401 RX737 RX733 SCI MODULE RX736 RX732 BX001 BX002 BX700 1 2 4 MAIN AM - AF BOARD IR001 BA001 BA002 BA002 31 32 BS11 BS01 BS02 BS02 BA001 BS01 55 50 34 47 36 37 53 52 IS40 IS01 IS60...
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AUDIO SWITCHING NOTES : This switching takes place in the audio processor, IS40 (MSP3410). This audio processor is controlled by Microprocessor IR001 via Bus IIC1. The following table summarises the audio switching: FUNCTION INPUT OUTPUT 55 of IS40 25 / 26 of IS40 28 / 29 of IS40 55 / 58 of IS40 33 / 34 of IS40...
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from front panel sockets BX401 RX737 RX733 SCI MODULE RX736 RX732 BX002 BX001 BX700 1 2 4 MAIN AM - AF BOARD IR001 BA001 BA002 BA002 31 32 BS009 3 BS001 BS002 BS002 BA001 BS001 28 33 50 36 48 47 30 31 IS150 IS220 AMPLI...
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AUDIO SWITCHING (DOLBY PROLOGIC) NOTES : This switching takes place in the audio processor, IS150 (MSP3410). This audio processor is controlled by Microprocessor IR001 via Bus IIC1. The following table summarises the audio switching: FUNCTION INPUT OUTPUT 28 of IS150 59 / 60 of IS150 56 / 57 of IS150 28 / 25 of IS150...
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BX001 50Hz VERSION IV001 VIDEO MODULE SCI MODULE 100Hz BV011 VERSION IV601 RV615 RV614 IR001 FB DET BV006 TV600 RV612 MAIN BOARD TV601 CENTRE DE FORMATION TECHNIQUE...
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RGB SWITCHING NOTES : RGB and FB signals from SCART connector AV1 are sent to: • The video processor, IV001, for a 50-Hz television set. • The demodulator, IV601, for a 100-Hz television set. DETECTING A FAST SWITCH, FB (100-Hz MODEL) The microcontroller must be informed of the presence of a fast switch to perform all switching of TV interfaces (RGB switching, mode display and inlay).
CONTENTS • GENERAL INFORMATION • IC001, STV2151 • GROUP DELAY COMPENSATION • IV001, STV2161 50Hz VIDEO PROCESSING CENTRE DE FORMATION TECHNIQUE...
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IV001 IC001 Y DELAY TC002/003/004/008/041 DELAY Y TRANSITION COMPENSATION SUBCARRIER R-Y/B-Y TRANSITION TRAP RVB PROCESS PAL/SECAM/NTSC SWITCHING IDENTIFICATION BRIGHTNESS PAL/SECAM/NTSC CONTRAST DEMODULATION SATURATION (APX) CONTRAST COMPENSATION 6 to 9 RVB,FB BEAM LIMITER RVB MATRIX 50,46 to 48 RVB,FB CUT-OFF SERVO CENTRE DE FORMATION TECHNIQUE...
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GENERAL INFORMATION NOTES : Two integrated circuits, controlled via Bus I2C, are used for video processing. IC001, STV2151. This performs: - Rejection of colour subcarriers, - Identification of colour: PAL/SECAM/NTSC, - Demodulation of colour: PAL/SECAM/NTSC. IV001, STV2161. This performs: - Luminance delay, - Improvement of R-Y and B-Y transitions, - Dematrixing of Teletext/OSD/SCART RGBs into Y, R-Y, and B-Y, - Switching of Y, R-Y, and B-Y,...
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IC001, STV2151 25 IC01 23 IC01 STANDARD ID1 ( B ) ID3 (+R ) POWER SUPPLY 3.8V 3.8V NO BURSTS 9VREG is the IC001 power source. Through a regulator built into IC001 and power Transistor TC001, it powers the IC001 (Pin 18) with a typical voltage 4.85V 2.75V of 7.7 V.
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0,9Vcc 0,4Vcc CC011 LC001 RC021 CC006 T=20ms SECAM to 19 3,85V 4,4V 0,15Vcc BC011 0,9Vcc RC006 V. REF. CVBS CLAMP 0,5Vcc to TC002 RC005 0,3Vcc CVBS SVHS SVHS CC020 SECAM:0,8Vcc to 17 PAL:70mVcc BC011 DEMOD. QC001 20ms CC019 ϕ 4,43MHz COLOR 3,5V OSCILLATOR...
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DEMODULATION GROUP DELAY COMPENSATION This circuit compensates for the delay in the video signal high frequencies The video or luminance signal from the SCART switching part arrives at 24 (CVBS) by delaying the low frequencies using the subcarrier trap built into the of IC001.
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IV001, STV2161 NOTES : LUMINANCE PROCESSING The luminance signal is injected at 2 of IV001, and passes through the following stages: • Programmable delay line, with amount of delay set by the MANAGEMENT microcontroller via Bus IIC. • EDGE REPLACEMENT circuit that improves the signal edges without creating overshoots.
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RGB PROCESSING NOTES : The Y, R-Y, and B-Y signals arrive at Pins 51 through 53 of IV001. They are aligned, and then sent to a switch. The RGBs and FB1 from SCART 1 arrive at Pins 6 through 9 of IV001. They are dematrixed into Y, R-Y, and B-Y, and then inform the switch.
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AUTOMATIC CUTOFF CONTROL NOTES : Automatic cutoff control is performed for Lines 21 through 24 and 334 through 337. To compensate for the tube leakage current, the RGB outputs are erased during Lines 21 and 334. The leakage current measurement determines a compensation current within IV001 that creates a voltage of 1.5 V at the terminals of RV092 (Pin 43 of IV001).
CONTENTS GENERAL INFORMATION • IV601, TDA9143 • SIGNAL PROCESSING BEFORE DIGITISING • 100-Hz DIGITAL PROCESSING • STRUCTURE OF PLL CLOCKS • 100-Hz VIDEO FORMAT CHANGES • PROCESSING SMOOTHING AND CORRECTION OF SIGNALS Y2H, U2H, • AND V2H RGB PROCESSING • BEAM LOCK •...
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B FB VIDEO MODULE IV309 19100 Frame memory IV001 IV308 RVB dematriçage IV601 RVB dematriçage YUV switching IV001 50 /100Hz compression chroma bright./ cont./ satur. YUV transitions demodulation improvment format control beam limiter YUV switching RVB matrix synchro process VCO gestion CRT servo IV602 Delay...
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GENERAL INFORMATION NOTES : Video processing is performed by the following integrated circuits: Circuit IV601, TDA9143 performs the following functions: • Dematrixing of SCART RGBs into YUV (U = B-Y, and V = R-Y), • PAL/SECAM/NTSC colour demodulation, • Switching of the two YUV sources, •...
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IV602 DELAY 1 LINE 1Vcc 1Vcc 4,5Vcc 1Vcc 1Vcc IV601 from 19 CVBS/Y TRAP BV011 1Vcc DELAY (without synchro) to TV801 0,8Vcc SWITCHING to TV821 DEMODULATION 1Vcc from 17 IDENTIFICATION FILTER BV011 0,3Vcc to TV841 1Vcc DEFLECTION 5Vcc 5Vcc 0,16 4,2V 3,8V 20ms...
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IV601, TDA9143 SYNCHRONISATION PROCESSING This is a specialised processor that handles video processing from a CVBS or A second PLL control loop (Pin 24) delivers the line synchronisation (HA) and Y/C signal. It is fully controlled via a IIC bus, and has its own internal filters. frame synchronisation (VA) signals via a time base and based on It requires no adjustment.
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SIGNAL PROCESSING BEFORE DIGITISING NOTES : The Y, U, and V signals from IV601 go through the low-pass anti-overlap filters (limiting their pass band), and are amplified and injected into IV308. After being processed in this way, these signals are digitised in IV308 in 4-1-1 version (Y = 8 bits, U = 2 bits, and V = 2 bits).
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FRAME MEMORY SWCK SRCK 3,5Vcc 10Vcc IV308 RSTW RSTR IV309 à à à 1Vcc 1,2Vcc 9/12 57/58 à18 CLAMP 1,5Vcc 2Vcc à à à à 2Vcc 1,5Vcc 0,7Vcc 4,2v 4Vcc 6Vcc 2,8v LLDFL 12/16/18MHz 27MHz 32MHz TV321 TV322 4,5µs 12µs 52µs T= 64µs 1,6ms...
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100-Hz DIGITAL PROCESSING NOTES : Integrated Circuits IV308 and IV309 are used. The various stages of processing are as follows: • Alignment of the Y, U, and V signals (IV308). The signals are input at 26, 24, and 22 of IV308. The alignment voltage is obtained from the reference voltage at 25 of IV308.
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FRAME MEMORY SWCK SRCK 3,5Vcc 10Vcc IV308 RSTW RSTR IV309 à à à 1,2Vcc 1Vcc 9/12 57/58 à18 CLAMP 2Vcc 1,5Vcc à à à à 2Vcc 1,5Vcc 0,7Vcc 4,2v 4Vcc 6Vcc 2,8v LLDFL 12/16/18MHz 27MHz 32MHz TV321 TV322 4,5µs 12µs 52µs T= 64µs 1,6ms...
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• Reading of frame memory (IV309). Signals SRCK, RSTR, and R control this NOTES : reading. - SRCK is the reading clock. Its frequency is 27 or 32 MHz. Because this is higher than the writing clock frequency, the picture is compressed. MEMOIRE SWCK SRCK...
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STRUCTURE OF PLL CLOCKS NOTES : Integrated Circuit IV308 creates three clocks: an acquisition clock for sampling and writing to memory, a restoration or display clock for reading from memory, and a deflection clock, set at 27 MHz, to deliver small line and frame signals for STV2162.
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PROGRAM 4/3 SCREEN 4/3 PROGRAM 4/3 SCREEN 16/9 W= 16 R= 32 NORMAL NORMAL W= 12 R= 32 ZOOM 1 W= 18 R= 32 W= 16 R= 32 ZOOM 1 ZOOM 2 W= 18 R= 27 W= 18 R= 27 ZOOM 2 PROGRAM 16/9 SCREEN 16/9 PROGRAM 16/9 SCREEN 4/3...
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FORMAT CHANGES NOTES : Format changes are related to the concepts of temporal compression or expansion, and can be applied via the memory writing and reading speeds, W and R. This change is visible only through its effect on picture width. The frame sweep must be acted on accordingly for the picture height.
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CV031 CV027 RV032 LV001/LV002 TV001 à TV003 MAIN Y CV001 à CV004 CORING BLACK EDGES CLAMP LV003/CV006 1Vcc FLAT PEAKING EXTENSION 0,6Vcc 0,6Vcc IMPROVMENT FILTER FILTER IV308 IV001 LV051 MAIN U TV051 TRANSITION CV051 /CV054 CLAMP IMPROVMENT FLAT 1,5Vcc 1,4Vcc 1,4Vcc FILTER LV071...
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SMOOTHING AND CORRECTION OF SIGNALS Y2H, U2H, AND V2H NOTES : Signals Y2H, U2H, and V2H pass through the smoothing filters required after digital-to-analogue conversion, and are injected at 26, 30, and 28 respectively on the PSI (Picture Signal Improvement) board, IV001. In IV001, Signal Y2H passes through the following stages: •...
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VIDEOTEXT IB01 TV063 SEPARATION IV001 MAIN Y WHITE EXTENSION SATURAT. IB03 BLACK MAIN U TV073 CLAMP SWITCHING MATRIX LEVEL CATHODE BRIGHT. MAIN V CONTR. IB02 TV083 BEAM CUT-OFF LIMITER INTERFACE ICUT LB16 RV052 RB17 RV092 TB18 RB18 USYS TTHT RL052 RL053 DV104 RV101...
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RGB PROCESSING NOTES : MAIN Y, MAIN U, and MAIN V arrive at Pins 2 through 4 of IV001. The MAIN Y component goes through the white stretch circuit, is output at 56 of IV001, and is reinjected at 53 of IV001. The three signals are then aligned and sent to a switch.
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VIDEOTEXT IB01 TV063 SEPARATION IV001 MAIN Y WHITE EXTENSION SATURAT. IB03 BLACK MAIN U TV073 CLAMP SWITCHING MATRIX LEVEL CATHODE BRIGHT. MAIN V CONTR. IB02 TV083 BEAM CUT-OFF LIMITER INTERFACE ICUT LB16 RV052 RB17 RV092 TB18 RB18 USYS TTHT RL052 RL053 DV104 RV101...
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AUTOMATIC CUTOFF CONTROL NOTES : Automatic cutoff control is performed for Lines 21 through 24 and 334 through 337. To compensate for the tube leakage current, the RGB outputs are erased during Lines 21 and 334. The leakage current measurement determines a compensation current within IV001 that creates a voltage of 1.5 V at the terminals of RV092 (Pin 43 of IV001).
CONTENTS • PROCESSING OF TELETEXT AND OSD MEGATEXT CENTRE DE FORMATION TECHNIQUE...
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IO1 to IO4 VIDEO_1 2Vcc TT012 à 18/19 IT001 µC 1Vcc R TXT/OSD TT008 A0 to A9 5 à 9 à 11 à 15 V TXT/OSD 1Vcc TT009 B TXT/OSD 1Vcc TT010 IT002 DRAM FB TXT/OSD TT011 2,5Vcc V_SYNC 5Vcc 5Vcc TT001 to TT003 10/11/13...
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PROCESSING OF TELETEXT AND OSD NOTES : Teletext and OSD are completely managed by Microcontroller IT001, assisted by DRAM IT002. IT001 is powered at 5 V and controlled by a 20.48-MHz clock. It communicates with IR001 via Bus M3L (at a rate of 850 kHz). It is configured as slave, and receives the MRESET initialisation command.
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GENERAL INFORMATION Signal Y is reconstituted by summing the RGBs in resistor network RM02 through RM04. The signal is then preamplified, and differentiated by Video amplification (50 Hz and certain 100-Hz models*) is performed by Transistors TM01, TM02, and TM04. The correction current is supplied by an Integrated Circuit IB01, TEA5101B.
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NOTES : AUDIO MODULE WITH MSP3410 Integrated Circuit IS40 (MSP3410) is used for audio processing. It is controlled by an 18.432-MHz clock. Management microcontroller IR001 controls it via Bus IIC1, and executes its reset via Pin 39. This integrated circuit performs the following functions: - Demodulation of FM audio intercarriers, - Demodulation of NICAM audio, - Switching of the various analogue audio sources for the SCART outputs,...
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AUDIO POWER AMPLIFIER, IA001 INTERLOCK WITH DOLBY OPTION The audio power amplifier consists of a single integrated circuit, IA001 In the event of an overload on the +US power supply line, the voltage drop at (TDA7269). This is a B-type amplifier. It has a symmetrical +14 V/-14 V power the terminals of Resistor RP130 increases and leads to the conduction of supply.
CONTENTS • INTRODUCTION • OPERATION MODULE AUDIO WITH DOLBY PROLOGIC CENTRE DE FORMATION TECHNIQUE...
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Full LEFT LEFT +90° DOLBY -3dB -3dB CENTER -90° 7KHz Full RIGHT RIGHT AMBIANCE DOLBY SURROUND SCRAMBLE CENTRE DE FORMATION TECHNIQUE...
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NOTES : INTRODUCTION Dolby Surround and Dolby Surround Prologic encoding are consumer applications of the Dolby Stereo professional audio system used for the cinema. This system consists of matrixing four channels on two tracks: • The classic left and right channels, •...
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BS001 IIC CL-1 TS720 IIC DA-1 TS721 SND RESET IS350 IIS WS TS722 AMPLI IIS CL TS723 SWITCH SND RESET DOLBY PROLOG IS250 BS006A AM AF MUTE IIS WS 55/50 TS400 IIS CL 51/49/27 IIS DA AV1-L SURROUND AV1-R CENTER IIS DA DS400 IIS DA...
OPERATION This circuit is different from the MSP3410 in the following two ways: Decoding takes place on the AM/DP module of the ICC19 chassis, using two - This circuit does not perform NICAM processing, MSP integrated circuits from ITT, and a DSP from Motorola. Operation is fully - A second I2S bus input is wired in place of the SBUS input on the digital.
+13V LINE KB_COLUMN_4 TRANSFORMER(DST) BEAM_INFO POWER (A=A/D DRIVER LINE MODSAFE STANDBY LED USYS CONTROL CIRCUIT CONVERTER) COIL KB_ROW_3 TV_OFF (TEA2261) KB_ROW_2 KB_ROW_1 DEFLECTION INFRARED TV_OFF SMPS_OUT RESET ZOOM ON4914 POWER IR01 CONTROL ICC19 100 Hz First issue 09 / 97...
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Utilice solo piezas originales RL146 LL034 Utilizzare un transformatore per isolarvi dalla rete RL147 e.g. CT 19005 31 Usys 131V LL037 RL149 LL046 Inserted TL030 BUV48CFITH16 BUV48CFITH16 LL047 Not inserted ZL041 MP125 MP125 LL084 ICC19 50 Hz First issue 09 / 97...
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SMPS_IN Utilice solo piezas originales GNDV GNDV GNDV GNDV XP 19900 00 XP 19101.00 GNDV RP 19101.00 CVBS_SAT BREATHING (L,P) SMPS JX923* GNDV GNDV XP 19000.00 V : 5 PAL/SECAM (5) PAL ICC19 50 Hz First issue 09 / 97...
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Las reparaciones en la sección de alimentación de energia FI010 deben ser ejecutadas solamente con un transformador de FI001 separacíon. PI030 FI015 BM03 Trap PI050 FOCUS Tuner AGC Video Level (BG) 40.4 MHz PI035 Video Level (L) ICC19 50 Hz First issue 09 / 97...
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Todos los valores por defecto de la página en curso ,« ∆ » cambia pagina. - Il cursor su están almacenados en RAM. - Cursor en ,« ∆ » cambia las páginas ICC19 50 Hz First issue 09 / 97...
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Por ejemplo,Se va visualizar el código de error 23: 2 parpadeos, una pausa corta; After setting Store (+) 3 parpadeos, una pausa larga. ICC19 50 Hz Para la Lista de códigos de error, consulte la tabla. First issue 09 / 97...
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Las reparaciones en la sección de alimentación de energia II050 deben ser ejecutadas solamente con un transformador de separacíon. FI010 FI001 PI030 FI015 Trap PI050 Tuner AGC Video Level (BG) 40.4 MHz PI035 ICC19 100 Hz First issue 09 / 97...
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Todos los valores por defecto de la página en curso ,« ∆ » cambia pagina. - Il cursor su están almacenados en RAM. - Cursor en ,« ∆ » cambia las páginas ICC19 100 Hz First issue 09 / 97...
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Por ejemplo,Se va visualizar el código de error 23: 2 parpadeos, una pausa corta; After setting Store (+) 3 parpadeos, una pausa larga. ICC19 100 Hz Para la Lista de códigos de error, consulte la tabla. First issue 09 / 97...
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MAIN BOARD - PLATINE PRINCIPALE - CHASSIS GRUNDPLATTE - PIASTRA PRINCIPALE - PLATINA PRINCIPAL COMPONENT SIDE - COTE COMPOSANTS - BESTÜCKUNGSSEITE - LATO COMPONENTI - LADO COMPONENTES SOLDER SIDE - CÔTE SOUDURES - LÖTSEITE - LATO SALDATURE - LADO SOLDADURAS ICC19 50 Hz First issue 09 / 97...
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TECHNICAL INFORMATION TV EQUIPED OF ICC19 CHASSIS (50Hz and 100Hz) Symptom : When the television is in the Standby Mode, residual noise can be heard from the loudspeakers. Solution : Change CP120 from 470µF 35V to 330µF 25V capacitor (codice 10448410)
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TECHNICAL INFORMATION - 32WS88KE ICC19 16/9 50Hz CHASSIS - 32WS83KP - 28WS73KD - 28WS78KE Symptom : Power supply switches to safety mode during VCR operating. Cause : Loss of synchronisation signal for 1 or 2 frames (poor quality video recording).
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TECHNICAL INFORMATION TV EQUIPED OF ICC19 CHASSIS (50Hz and 100Hz) Symptom : In case of failure of IC TDA8177F in position IF001. Solution : CAUTION Version TDA8177F (Part No. 10352880) is able to carry higher output currents than the TDA8177 (Part No. 15053440) used in TX92 chassis.
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TECHNICAL INFORMATION SUBJECT : ICC19 100Hz CHASSIS STEREO or DOLBY STEREO Symptom (only applicable to Italy) : Picture interference when receiving VHF Band 1 signals, either moire patterning or black vertical bars on the screen. Cause : Cross talk between power supply and tuner.
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ICC19 100 Hz BASIC- / IM- / MM- Version tube name description CT-Part Usys jumper Usys Version A66EGW 48X322 4/3 28”MP INVAR BSVM CT 19101 34 10362880 10460360 JP915 134V ICC19 IM CT 19105 37 10351530 10468070 JP914 137V ICC19 IM A59EGD048X322 4/3 25”SF INVAR BSVM...