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OPTi ChromaCast 82C205 Preliminary Programmer’s Manual

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ChromaCast
ChromaCast
82C205
LCD Monitor Controller
Preliminary Programmer's Guide
CONFIDENTIAL
Revision 1.0
915-2000-084
11/22/99

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  • Page 1 ® ChromaCast ChromaCast 82C205 LCD Monitor Controller Preliminary Programmer’s Guide CONFIDENTIAL Revision 1.0 915-2000-084 11/22/99...
  • Page 2 OPTi Inc. to notify any person of such revisions or changes. Trademarks OPTi and OPTi Inc. are registered trademarks of OPTi Inc. All other trademarks and copyrights are the property of their respective holders. OPTi Inc.

  • Page 3: Table Of Contents

    ChromaCast 82C205 ® Table of Contents INTRODUCTION ................................1 ..............................2 OMENCLATURE CHOOSING CHROMACAST 82C205 HARDWARE CONFIGURATION ..............3 CONFIGURING CHROMACAST 82C205 FOR A SPECIFIC PANEL ..............3 CRTC P ..........................4 ISPLAY ROGRAMMING Pixel Clock Frequency (in MHz): ........................4 Horizontal Sync Polarity: ..........................4 Horizontal Sync Width (in units of pixel clock)....................5 Horizontal Display Start (in units of pixel clock) ....................5...
  • Page 4 Programmer's Guide ChromaCast 82C205 ) ....................13 ERTICAL IDTH IN UNITS OF VIDEO LINES ) .....................14 ERTICAL ISPLAY TART IN UNITS OF VIDEO LINES ) ....................14 ERTICAL ISPLAY IN UNITS OF VIDEO LINES )......................14 ERTICAL OTAL IN UNITS OF VIDEO LINES CRTC ...............15...
  • Page 5 CCESS TO THE UFFER .................................42 NTERRUPTS Enabling an event to generate an interrupt ....................42 The interrupt/event status register.......................42 Clearing an interrupt/event ..........................43 POWER MANAGEMENT FOR CHROMACAST 82C205 ..................45 ..................................45 IMER Setting the timer interval..........................45 ® 915-2000-084 Revision 1.0 Page v...
  • Page 6 ANAGEMENT Notifying the CPU of the DPMS state......................46 Monitor is disconnected from the VGA controller ..................46 ChromaCast 82C205 Power Conservation Techniques................46 Example of Power Conservation Policy for DPMS..................47 APPENDIX A: EXAMPLE REGISTER INITIALIZATION VALUES.................49 APPENDIX B: COMMON VGA TIMING VALUES....................51 APPENDIX C: VCLK2 PLL M &...
  • Page 7 Programmer's Guide ChromaCast 82C205 OSD Description Language Select......................59 .........................60 ANUFACTURE DEBUGGING MODE ® 915-2000-084 Revision 1.0 Page vii...
  • Page 8 Programmer's Guide ChromaCast 82C205 ® 915-2000-084 Revision 1.0 Page viii...

  • Page 9: Introduction

    ® Introduction This is the programmer’s guide for the ChromaCast 82C205 LCD Monitor Controller. It is an application note for the ChromaCast 82C205 Databook that contains detailed register descriptions. This guide will walk the programmer through the various programming sequences necessary in order to build a customized LCD monitor control application.

  • Page 10: Nomenclature

    DRAM to buffers for use by the ChromaCast 82C205. Testing This section indicates what sort of testing and debug options are available on the ChromaCast 82C205. TV Mode This section details how to operate the TV mode on the 82C205. The ChromaCast 82C205 interfaces with an NTSC/PAL decoder and accepts YUV 4:2:2 format.

  • Page 11: Choosing Chromacast 82C205 Hardware Configuration

    ® Choosing ChromaCast 82C205 Hardware Configuration ChromaCast 82C205 has a 24-bit digital interface that can be used with a PanelLink or LVDS receiver or external A/D converters. In addition to an external A/D converter, ChromaCast 82C205 supports external clock sources.

  • Page 12: Display Crtc Programming

    The following parameters for the Display CRTC timing, including pixel clock frequency, horizontal and vertical sync timings, timing for DE, and polarities of the horizontal and vertical syncs are determined by the specification for the panel that the ChromaCast 82C205 is controlling. Pixel Clock Frequency (in MHz): The panel is driven by a pixel clock, which is the same clock that drives the display subsystem of the ChromaCast 82C205.

  • Page 13: Horizontal Sync Width (In Units Of Pixel Clock)

    Programmer's Guide ChromaCast 82C205 Note: Polarity can be defined as follows: If the sync is high while data is active, then it is an active low sync. If the sync is low while data is active, then is it an active high sync.

  • Page 14: Horizontal Total (In Units Of Pixel Clock)

    Programmer's Guide ChromaCast 82C205 Horizontal Total (in units of pixel clock) This is the period of Horizontal Sync. Horizontal Total Total Register 80h, 81h Vertical Sync Polarity This register sets the polarity of the vertical sync to the panel. It has no relationship to the polarity of the incoming sync from the VGA.

  • Page 15: Vertical Display End (In Units Of Video Lines)

    Programmer's Guide ChromaCast 82C205 Vertical Display End (in units of video lines) This is the time between the start of the vertical sync and the end of data valid. Vertical Display End Display End Register 90h, 91h Vertical Total (in units of video lines) This is the period of the vertical sync.

  • Page 16: Display Timing Waveforms

    Programmer's Guide ChromaCast 82C205 Display Timing Waveforms Signal Description Symbol Typical Unit FPFRAME Vertical Total 4095 Lines V Sync Width 4095 Lines Vertical Display Start 4095 Lines Vertical Display End 4095 Lines FPLINE Horizontal Total 4095 Pixel Clock H Sync Width...

  • Page 17: Horizontal Timing For Tft Panel

    Programmer's Guide ChromaCast 82C205 Horizontal Timing for TFT Panel FPLINE DE (DRDY) … DATA Detail of Pixel Clock Timing DE (DRDY) FPSHIFT DATA * Polarity of FPFRAME, FPLINE, & FPSHIFT is programmable. * One and Two Pixels Per Clock are supported.
  • Page 18 Programmer's Guide ChromaCast 82C205 ® 915-2000-084 Revision 1.0 Page 10...

  • Page 19: Vga Video Input Interface

    The VESA document VESA Monitor Timing Specifications discusses this in depth. ChromaCast 82C205 provides feedback to the 8051 micro-controller specifying the refresh rate and horizontal sync frequency of the VGA input. The 8051 micro-controller must then update the capture clock divider word (for the line-locked PLL), the capture CRTC registers, and the scaler ratio.

  • Page 20: Determining The Resolution Of The Incoming Vga

    Programmer's Guide ChromaCast 82C205 Determining the Resolution of the Incoming VGA The resolution of the VGA can be determined by reading the resolution counter status register. This register gives the number of horizontal syncs between vertical syncs, i.e. the period of vsync in units of incoming video lines.

  • Page 21: Horizontal Sync Width (In Units Of Vclk1)

    Programmer's Guide ChromaCast 82C205 Horizontal Sync Width (in units of VCLK1) This register defines the width of the active part of the sync (when data is not valid). This is for internal use, so it can be set to any value greater that 1. As a rule of thumb, set this to 10.

  • Page 22: Vertical Display Start In Units Of Video Lines

    Programmer's Guide ChromaCast 82C205 and end value for the Capture CRTC, so in order to achieve a sync width of 1, the sync start should be programmed to be 1, and the sync end should be programmed to be 2.

  • Page 23: Program The Capture Crtc To Synchronize To External Syncs

    Programmer's Guide ChromaCast 82C205 Vertical Total = Resolution Detection Register Value (Register 70h, 71h) Vertical Total V Total Register 50h, 51h Program the Capture CRTC to Synchronize to External Syncs The Capture CRTC can be programmed to synchronize to the incoming horizontal and vertical syncs, or it can free-run by generating its own syncs according to the values in the Capture Horizontal Total and Capture Vertical Total registers.
  • Page 24 Programmer's Guide ChromaCast 82C205 ® 915-2000-084 Revision 1.0 Page 16...

  • Page 25: Dither

    Register 3Ch, Bits[3:0] Scaling The ChromaCast 82C205 can scale an incoming video signal up to a larger panel resolution, or down to a smaller panel resolution. The programmer has to specify the incoming resolution, the outgoing resolution, and the scaling ratios in order for scaling to occur.

  • Page 26: Setting The Output Resolution

    Programmer's Guide ChromaCast 82C205 VGA Example: Assuming a 640 x 480 VGA signal, the Xsize = 640 and the Ysize = 480. When scaling down, add 2Bh to Input Y size (Register 50h, 57h). Assuming a 1280x1024 VGA signal ouptus to a 1024x768 panel, the Xsize=1280 and the Ysize=1024 + 2Bh.

  • Page 27: Horizontal Ratio

    Programmer's Guide ChromaCast 82C205 Vertical Ratio for Scaler Yratio Register 54h, 55h Horizontal Ratio: • Scaler: If capture Xsize > display Xsize then, Xratio = (( display Xsize * 8192 ) / ( capture Xsize + 1 )) / 2...

  • Page 28: Using The Anti-Alias Filter

    Register 66h, 67h Down Random DDA Init Using the Anti-Alias Filter ChromaCast 82C205 has an anti-alias filter that is used only for scale-down. If the 82C205 needs to scale down, enable this filter. Antialias Filter Enable AntiAlias Enable Register 6Eh ®...

  • Page 29: Centering

    Programmer's Guide ChromaCast 82C205 ® “Centering” Up to this point only scaling to the full panel resolution has been discussed. The 82C205 also offers a “centering” option which allows an image that is of lower resolution than the panel to be displayed in the center of the panel, surrounded by a black border that makes up the difference between the image resolution and the panel resolution.
  • Page 30 Programmer's Guide ChromaCast 82C205 ® 915-2000-084 Revision 1.0 Page 22...

  • Page 31: Contrast And Brightness Adjustment

    Programmer's Guide ChromaCast 82C205 ® Contrast and Brightness Adjustment There are two ways to change the contrast of the image. The first is through the analog gain adjustment on the external A/D converters. Usually this is adjusted once and then left alone. When the user adjusts the contrast and brightness through the user interface, the user will adjust the digital contrast and brightness levels.
  • Page 32 Programmer's Guide ChromaCast 82C205 ® 915-2000-084 Revision 1.0 Page 24...

  • Page 33: The On Screen Display

    Register 2Ah, 2Bh Vertical Register 2Eh, 2Fh Selecting OSD Attributes ChromaCast 82C205 is full of useful attributes for the OSD, such as: • transparent pixels – opt for a non-rectangular OSD shape • blinking pixels - the 82C205 can blink to the underlying video, or to the color value in Index 0 of the register CLUT.

  • Page 34: Alpha Blend Operation

    Alpha Blend Operation The alpha blend value in ChromaCast 82C205 is 5-bits wide. When the alpha blend value is set to 10h, the OSD overlay completely obscures the underlying video (this is full scale). When the alpha blend value is set to 00h, the OSD pixel is transparent.

  • Page 35: Memory Configuration And Allocation

    Memory Configuration and Allocation The ChromaCast 82C205 uses a 4 Mbyte DRAM buffer for a FRC (Frame Rate Conversion) frame buffer, as well as a buffer for the OSD bitmap. Frame Rate Conversion means that the 82C205 can accept video arriving at different refresh rates than the panel supports.

  • Page 36: Programming The Refresh Rate

    DRAM, burst type, and burst length. Programming the refresh rate The refresh rate for DRAM is controlled by a counter inside of ChromaCast 82C205. The counter can be programmed and is clocked by a 14.318 MHz reference clock. Whenever the counter reaches the programmed terminal count, a refresh request will be generated.

  • Page 37: Dram Buffer Allocation

    Programmer's Guide ChromaCast 82C205 Now the DRAM interface is configured, and the next step is to allocate the DRAM address space to the various buffers. DRAM Buffer Allocation The frame buffer is used to capture data, and then display it. When the 82C205 is in bypass mode, the frame buffer is not used.

  • Page 38: Vga Frame Buffer

    Programmer's Guide ChromaCast 82C205 which is the number of pixels per lines to be accessed multiplied by the bits per pixel and divided by the word size which is 64*8 for the DRAM configuration. VGA Frame Buffer Calculating the pitch of the frame buffer...

  • Page 39: Osd Buffer

    Programmer's Guide ChromaCast 82C205 OSD Buffer Calculating the OSD Pitch The pitch of the OSD buffer can be calculated as follows: OSD Pitch (in bytes) = [(OSD Horizontal Size x 4)+((64*8)-1)] / 8 Calculating the size of the OSD DRAM buffer The pitch of the OSD determines the size of the OSD buffer required.

  • Page 40: Cpu Scratch Ram

    Programmer's Guide ChromaCast 82C205 Display FIFO Word Count This value indicates how many DRAM read accesses that the FIFO will perform in one line. Use the following formula: Display FIFO Word Count = [(Display Panel Horizontal Size * Primary Bits...

  • Page 41: Testing And Debugging

    The major subsystems of ChromaCast 82C205 are controlled by separate software resets. Various hardware internals of ChromaCast 82C205 can be powered down by software for testing purposes. The video input subsystem can be disabled (stopping the capture), as can the video output subsystem (stopping the display).

  • Page 42: Revision Number

    Programmer's Guide ChromaCast 82C205 Revision Number The Revision number of ChromaCast 82C205 is in a read-only register. Revision Number Revision Register 00h FIFO Status The internal FIFOs within the 82C205 have flags that will trigger for overflow and underflow conditions. In order to clear these flags, the program must write a “1”...

  • Page 43: Memory Subsystem Status

    Programmer's Guide ChromaCast 82C205 Memory Subsystem Status The internal blocks of the memory subsystem have status registers that can be used to observe the state machines of the memory arbiter and sequencer. These registers can be used to detect a lock-up of the memory system.
  • Page 44 Programmer's Guide ChromaCast 82C205 ® 915-2000-084 Revision 1.0 Page 36...

  • Page 45: Tv Mode Setup

    Required Synchronization signals from the TV decoder ChromaCast 82C205 requires an odd/even flag from the TV decoder instead of a vertical sync. The polarity for this flag is programmable, and will switch which field is considered odd and which is even, but this is not really a necessary distinction.

  • Page 46: Programming The Crtc For Tv Mode

    See the section on Scaling. The scalers will have to be updated when TV mode is entered. IP Conversion In order to convert the television signal from interlaced mode to progressive scan mode, IP conversion is necessary. Three types are implemented on ChromaCast 82C205: 1-Field Bob Mode, 2-Field Bob Mode, and Weave Mode. Bob Mode ChromaCast 82C205’s 2-Field Bob Mode is the recommended interlaced-to-progressive method.
  • Page 47 Programmer's Guide ChromaCast 82C205 field is then captured into those ”skipped” lines. This method results in motion artifacts from the temporal inconsistencies. 1. Set the Display Field 2 Start = Display Field 1 Start. 2. Make sure the Capture Field 2 Buffer does not collide with the Capture Field 1 Buffer. Capture Field 1 must now hold 480 lines, and Field 2 should have 0.
  • Page 48 Programmer's Guide ChromaCast 82C205 ® 915-2000-084 Revision 1.0 Page 40...

  • Page 49: Cpu Interface

    Managing the DDC Transfer The ChromaCast 82C205 can ask for service from the CPU by means of an active low interrupt line. This is how the 82C205 communicates events such as a change of resolution on the incoming video, a DDC service request, and a power management service request.

  • Page 50: Interrupts

    Bank Register (Index 1Ch) DRAM Address[21:14] Another bit in the ChromaCast 82C205 will disable the memory accesses (reads and writes), so the 82C205 will ignore any memory reads and writes. For normal operation, this bit should be set to 0h.

  • Page 51: Clearing An Interrupt/Event

    Programmer's Guide ChromaCast 82C205 Interrupt Status Status Register B5h Clearing an interrupt/event Write a “1” to the bit in the Interrupt Clear Register that corresponds to that event. Interrupt Clear Clear Register B5h ® 915-2000-084 Revision 1.0 Page 43...
  • Page 52 Programmer's Guide ChromaCast 82C205 ® 915-2000-084 Revision 1.0 Page 44...

  • Page 53: Power Management For Chromacast 82C205

    Power Management for the system. Timer ChromaCast 82C205 has a general purpose on-chip timer that can be used by the CPU to control power sequencing and power management time intervals. The timer is a 19-bit countdown timer that can count from 5 seconds down to 0 in 10 µs intervals.

  • Page 54: Dpms Power Management

    Operating without External Syncs Free Run Register 52h, Bits[1:0] Capture CRTC ChromaCast 82C205 Power Conservation Techniques The ChromaCast 82C205 can disable its on-chip PLLs and it can power down the panel backlight and panel power. Hardware Enables Enables Register C9h ®...

  • Page 55: Example Of Power Conservation Policy For Dpms

    Programmer's Guide ChromaCast 82C205 Example of Power Conservation Policy for DPMS There are 4 states in the DPMS Power Management system. Below are these states are indicated, along with a possible power conservation policy. This is only one of many possible implementations.
  • Page 56 Programmer's Guide ChromaCast 82C205 Suspend Now it is time to shut down most of the system. Power off the A/Ds and the backlight. The PLLs and the panel will still have power. Wait for 5 s (using the timer). Check the status of the Sync Lost Bits. If horizontal and vertical sync are now present, power the A/Ds and backlight back on, and return to the on state.

  • Page 57: Appendix A: Example Register Initialization Values

    The following table shows initialization values for ChromaCast 82C205 registers for a 1024x768, 60 Hz TFT panel accepting 1024x768, 70 Hz VGA input. The ChromaCast 82C205 is using the DRAM frame buffer and an external line-locked PLL in this example.
  • Page 58 Programmer's Guide ChromaCast 82C205 ® 915-2000-084 Revision 1.0 Page 50...

  • Page 59: Appendix B: Common Vga Timing Values

    Programmer's Guide ChromaCast 82C205 ® Appendix B: Common VGA Timing Values The following values are extracted from the VESA Computer Monitor Timing Standard. These are the values that a programmer may choose to include in a look-up table in order to properly program the Capture CRTC to accept different resolutions and refresh rates.
  • Page 60 Programmer's Guide ChromaCast 82C205 ® 915-2000-084 Revision 1.0 Page 52...

  • Page 61: Appendix C: Vclk2 Pll M & N Values

    Programmer's Guide ChromaCast 82C205 ® Appendix C: VCLK2 PLL M & N Values This table indicates the M and N values for the Display PLL (VCLK2). These values can also be used for programming the memory clock (MCLK) PLL. N Frequency(MHz) 25.056815...
  • Page 62 Programmer's Guide ChromaCast 82C205 44.386358 51.545448 59.181811 44.545449 51.765728 59.318174 44.744312 51.903402 59.475517 44.863631 52.066109 59.659083 44.999994 52.159084 59.876025 45.157337 52.499993 60.136356 45.340903 52.867126 60.340901 45.340903 52.977266 60.454538 45.557845 53.181811 60.576915 45.818176 53.367762 60.852265 46.022721 53.454539 61.090901 46.136358 53.693175 61.177678 46.258735...
  • Page 63 Programmer's Guide ChromaCast 82C205 66.818173 74.454536 82.090899 67.185306 74.659081 82.329535 67.295446 74.772718 82.604885 67.499991 74.895095 82.727262 67.685942 75.170445 82.840899 67.772719 75.409081 83.045444 68.011355 75.495858 83.305775 68.286705 75.681809 83.522717 68.409082 75.886354 83.706283 68.522719 76.363627 83.863626 68.727264 76.704536 83.999989 68.987595 76.797511 84.119308 69.204537...
  • Page 64 Programmer's Guide ChromaCast 82C205 89.727261 93.618869 97.159079 89.814038 93.718996 97.363624 89.999989 93.863624 97.623955 90.204534 94.090897 97.840897 90.314674 94.261352 98.024463 90.681807 94.499988 98.181806 91.022716 94.720268 98.318169 91.115691 94.857942 98.437488 91.278397 95.020649 98.636351 91.416072 95.113624 98.795442 91.636352 95.454533 98.925607 91.874988 95.821666 99.034078 92.045443...

  • Page 65: Appendix D: Chromacast Osd (On-Screen Display) User's Guide

    Programmer's Guide ChromaCast 82C205 ® Appendix D: ChromaCast OSD (On-Screen Display) User's Guide The ChromaCast On-Screen Display (or OSD) allows the user to alter the screen image appearance to suit their individual preferences Enabling OSD The end user can enable OSD on the screen by pressing either the “Select” or the “Adjust” button on the front panel of the LCD.

  • Page 66: Description Of Supported Icons

    Programmer's Guide ChromaCast 82C205 Mode Button: This button is used to select one of the four input modes. Pressing the button once will initially display the current display mode. Pressing the button again will allow the user to toggle between the following four input modes: 1.

  • Page 67: Recall Icon

    Programmer's Guide ChromaCast 82C205 Recall Icon: Use Select button to choose either “USER Recall” mode or “Factory Recall, then use Adjust button to excute it (Your choice will be updated only when you executed Exit command). USER Recall mode Allows you to reinstate all of ChromaCast Registers setting from previous value saved by user.
  • Page 68 Programmer's Guide ChromaCast 82C205 Manufacture debugging mode This mode is provided for debugging only. Only engineers thoroughly familiar with the ChromaCast registers should ever attempt to use this mode. Press both Adjust buttons (“+” and “-“) at the same time, then enter a ChromaCast Register number and its contents will be displayed on the OSD window.

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