Radio Shack TRS-80 II Technical Reference Manual page 9

JO field during disk Read or WrÎte operations. The Sector
Regisler contents can be loaded Irom or translerred la the
DAl. This register should nol be loaded when the FOC is busy.
Command Reglster (CRI - This eight·bil regisler holds the
command presently being execuled. This regisler should riot
be loaded when the FDC is bU!iy except ta load a force
lnlerrupt commando This action results in an inlerrupl. The
command register can
be
loaded from the DAL bul not read
onlo the OAL
Status Aeglater (STRI - This eight·bil register holds device
Slalus information. The meaning of lhe Status bits is a function
of lhe conlents ot the Command Regisler. This register can be
read onto the OAL but not loaded from the DAL
CRC logle - This lagie is used to check or to generate lhe
16-bit Cyclic Redundancy Check (CRC). The CRC includes ait
inlormation starllng with the address mark and up to the CRC
characters. The CRC register is present 10 ones (l's) prior 10
data belng shitled through Ihe circuit.
Arlthmetlc/loglc Unit (AlU) - The ALU is a seriai
comparator. încrementer and decrementor, Il ls used for
register modification and comparisons with the disk recorded
ID lield.
Timing and Control - Ali computer and Floppy Oisk interface
controls are generated throughout Ihe 10gic. The interna)
device timing is generated from an external clock,
The 1791 has two differenl modes 01 operation. according to
Ihe stale of DOEN. When ODEN
=
O. double dansîly (MFM) is
assumed. When DDEN = 1. single density (FM) is assumed.
AM Detector - This address mark deteclor delecls tD. data
and index address marks during Read and Wrile operations.
Proeessor Interface
The interface ta the processor is accomplished lhrough the
eight Data Access Lines (oAl) and associated control signaIs.
The OAL are used to transler DaIa. Slatus and Control word
out of. or into, the F01791.
The DAl are lhree·state bulfers that are enabled as oulput
drivers when Chip Enable (CE') and Read Enable (RE') are
active (Iow·\ogic state) or act as inpul receivers when CE' and
Write Enable (WE') are active.
When transler of data la the Floppy Disk Controller is requir& 1
by the host processor. the devtce address is decoded and CE'
is made low. The least-slgnifieanl address bits A1 and AIJ..
combined with the signais RE' during a Read operation or WE'
during a Write operation. are Interpteted as selecting lh.!
foJlowing registots:
Port
Addreaa Al·AI Read (RPI Wrlte (WeO)
A1
AO
E4H
0
0
Stalus Regisler Command Register
ESH
0
1 Track Register Track Regisler
EBH
1 0 Sector Register Sector Reglster
E7H
1 1 Data Regisler Data Register
Table 4. Reglater Sheet
Ouring Direct Memory Access (OMA). lypes of data
transfer~,
betweBrl the Data Register of the FD1791 and lhe DMA. lhl'
Oata Raquest (DAO) output is used in data Transler control
This signal aise appears as status bit 1 during Read and Wrilt
operations,
On Disk Read operation. the Data Aaquest is activated (se
high when an assembled seriai input byte is translerred ir
parallelto the Data Aegister). This bit is c1eared when the DaI.
Register is read by the processer Of DMA controller,
If the Data Register is read alter one or more characlers arf
lost (by having new data ttanslerred into the reglster prior tc
the processer readout). the lost Data bit is set in the Statu!
Regist8f. The Read operalion continues until the end 01 Ihf
sector is reached.
On Disk Write operalions. lhe Data Requesl is activated wher
the Data Register translers Its contents to the Data Shil'
Regisler and requires a new data byte, lt Is resel when the
Data Shifl Register is loaded with new data by the processor 01
DMA conltoller.
Il new data Is not loaded at the time the next seriai byte
i~
required by the Floppy Oisk. a byte al zeroes ig wrilten on the
diskelte and the lost Data bit is set in the Slatus Aegister.
At the completion of every command, an JNTRO is genetated.
INTRO is reset by either reading the status register or b-y
loading the command register with a new commando In
addition. INTRQ is generated when a Force Interrupl command
condilion is met
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