Page 1 Preliminary Information AMD-761™ System Controller Software/BIOS Design Guide Publication # 24081 Rev: D Issue Date: February 2002...
Page 2 Trademarks AMD, the AMD logo, AMD Athlon, and combinations thereof, AMD-751, AMD-760, AMD-761, AMD-762, and AMD-766 are trademarks of Advanced Micro Devices, Inc. Other product names used in this publication are for identification purposes only and may be trademarks of...
Page 3: Table Of Contents
General BIOS Initialization Requirements ....2 1.1.1 AMD-761™ Configuration Spaces ....2 1.1.2 Special Configuration Sequencing Requirements .
Page 4 Preliminary Information AMD-761™ System Controller Software/BIOS Design Guide 24081D—February 2002 DDR SDRAM Interface Overview ......... 149 DDR DIMMS and DDR SDRAMs .
Page 5 Preliminary Information AMD-761™ System Controller Software/BIOS Design Guide 24081D—February 2002 PCI Bus Interface Delayed Transactions and Ordering Rules Usage ..195 5.1.1 Delayed Transactions and Target Latency ..196 5.1.2 Transaction Ordering Rules .
Page 6 Preliminary Information AMD-761™ System Controller Software/BIOS Design Guide 24081D—February 2002 Table of Contents...
Page 7 24081D—February 2002 List of Figures Figure 1. AMD Athlon Processor Family Address Mapping ..9 Figure 2. AMD Athlon Processor Family x86 Processor Address Mapping........11 Figure 3.
Page 8 Preliminary Information AMD-761™ System Controller Software/BIOS Design Guide 24081D—February 2002 List of Figures...
Page 9 DDR Memory Base Address Register Locations ... . 95 Table 11. AMD-761 DRAM Addressing Modes ..... 96 Table 12.
Page 10 Preliminary Information AMD-761™ System Controller Software/BIOS Design Guide 24081D—February 2002 Table 29. AMD-761 System Controller ECC Behavior (with ECC Enabled) ........171 Table 30.
Page 11 Preliminary Information AMD-761™ System Controller Software/BIOS Design Guide 24081D—February 2002 Revision History Date Description Text added in the following locations explaining that the registers must be saved and restored when entering and exiting the S3 state: „ Section 1.1.5 on page 7, 2nd paragraph added „...
Page 12 Preliminary Information AMD-761™ System Controller Software/BIOS Design Guide 24081D—February 2002 Revision History...
Page 13: Overview
„ Section 1 provides an overview of the general BIOS requirements for initializing the AMD-761 system controller configuration registers. „ Section 2 on page 9 contains a description of all AMD-761 system controller configuration registers. „ Section 3 on page 149 contains additional information on setup of the DDR SDRAM interface configuration registers.
Page 14: General Bios Initialization Requirements
Base Address 1: GART Memory Mapped Register Base 1.1.2 Special Configuration Sequencing Requirements This section outlines a few cases in the AMD-761 system controller configuration registers that require special handling for proper BIOS programming. Configuration Cycles The AMD-761 system controller supports configuration...
Page 15 „ Note that the AMD-761 system controller does not report as a multifunction device (bit 7 is not set in the Header_Type field in the PCI Latency Timer and Header Type register in Dev 0:F0:0x0C).
Page 16: Power-On Reset Initialization
R/W by setting the Int_Pin_Cntl bit in the Miscellaneous Device 1 Control register (Dev 1:F0:0x40). The AMD-761 system controller does not use the Int_Pin field internally, the register is provided for software compatibility only. Silicon Revisions The reader is advised to read the AMD-761™...
Page 17 Preliminary Information AMD-761™ System Controller Software/BIOS Design Guide 24081D—February 2002 Table 1. AMD-761™ System Controller Configuration Register Bits Unknown at RESET# Register Name Offset Bit Name Bit(s) SERR_Enable [15:14] ECC Mode/Status Dev 0:F0:0x48 ECC_Diag [12] ECC_Mode [11:10] SBPWaitState [31] Addr_Timing_A...
Page 18 Preliminary Information AMD-761™ System Controller Software/BIOS Design Guide 24081D—February 2002 Table 1. AMD-761™ System Controller Configuration Register Bits Unknown at RESET# (Continued) Register Name Offset Bit Name Bit(s) SW_Recal Use_Act_Dly DDR PDL Calibration Control Dev 0:F1:0x40 Auto_Cal_En Act_Dly_Inh Auto_Cal_Period [1:0]...
Page 19: Programming Reserved Bits
Preliminary Information AMD-761™ System Controller Software/BIOS Design Guide 24081D—February 2002 Table 1. AMD-761™ System Controller Configuration Register Bits Unknown at RESET# (Continued) Register Name Offset Bit Name Bit(s) PSlewMAB [29:27] NSlewMAB [26:24] PDrvMAB [19:18] NDrvMAB [17:16] DDR MAB/MAA Pad Configuration...
Page 20: Recommended Amd Athlon™ Processor
24081D—February 2002 Recommended AMD Athlon™ Processor SYS_CONFIG Settings Table 2 provides recommendations for settings in the AMD Athlon processor System Configuration register in systems that utilize the AMD-761 system controller. Table 2. Recommended Settings for AMD Athlon™ Processor SYSCFG Register BIOS...
Page 21: System Controller Programmer's Interface
AMD-761™ System Controller Programmer’s Interface Overview The AMD-760™ chipset supports both x86 and Alpha™ processors that conform to the Socket2000 bus specification. Both processors share a compatible view of system memory and peripherals. Legacy x86 (IBM PC-AT) memory mappings are implemented by x86 processors (AMD Athlon™...
Page 22: Address Map
Preliminary Information AMD-761™ System Controller Software/BIOS Design Guide 24081D—February 2002 Address Map Table 3 shows the address map implemented by the AMD-761™ system controller. Table 3. AMD-761™ System Controller Socket2000 Memory Map Address Space Start Address Space End Name/Command Description...
Page 23 AMD-761™ System Controller Software/BIOS Design Guide 24081D—February 2002 For reference, the x86 view of memory from the perspective of the AMD Athlon processor and the mapping to the Socket2000 memory map is shown in Figure 2. Note: Not to scale.
Page 24: Special Cycles
A M D A t h lo n p ro c e ss o r s y s t e m b u s W r LW s commands to a single address (1 F8000 0000) with the data field specifying the desired special cycle. The AMD-761 system controller maps the AMD Athlon processor system bus data value onto the PCI for both address and data phases of the Special Cycle Transaction.
Page 25 Preliminary Information AMD-761™ System Controller Software/BIOS Design Guide 24081D—February 2002 Table 4. AMD Athlon™ Processor Special Cycle Encodings (Continued) PCI Address and Northbridge and Southbridge Special Cycle Data Field Processor Description Description Contents The AMD-761™ system controller The AMD Athlon™ processor gener-...
Page 26 Preliminary Information AMD-761™ System Controller Software/BIOS Design Guide 24081D—February 2002 Table 4. AMD Athlon™ Processor Special Cycle Encodings (Continued) PCI Address and Northbridge and Southbridge Special Cycle Data Field Processor Description Description Contents The AMD-761™ system controller waits for all queues to memory to be empty (assumes the PCI grant enable register is clear, “Dev0:F0:0x84”...
Page 27: Iack
SysAdd Field[23:0] taken from the register that saved the most recent write to 0CF8 (above). „ In traditional mode, which the AMD-761 system controller implements, IN and OUT instructions that reference 0CF8 and 0CFC are passed normally on to the AMD Athlon processor system bus where the Northbridge generates the appropriate PCI configuration access.
Page 28: Address Decoding
AMD-761™ System Controller Software/BIOS Design Guide 24081D—February 2002 Address Decoding A consistent view of memory and PCI devices is enforced by decoding logic in the AMD-761 system controller in the AMD Athlon processor system bus and PCI interfaces. 2.3.1 Socket2000 Address Decoding...
Page 29: Pci/Agp Master Address Decoding
SysAddOut[23:0] are asserted on PCI AD[23:0] with the PCI I/O read or write command. Using Dev1:0x1C, I/O range address decoding, send to • either PCI or AGP/PCI. Note: Low-order AMD Athlon processor system bus address bits, per AMD Athlon processor system specification, SysAddOut only goes down to PA[3].
Page 30: Configuration Registers
GART control registers from either PCI or AGP/PCI masters. Configuration Registers All functional registers in the AMD-761 system controller are implemented as PCI configuration registers. The AMD-761 system controller implements a standard PCI hierarchy that allows BIOS software to enumerate devices on the primary PCI, the AGP port, and future interfaces.
Page 31 Preliminary Information AMD-761™ System Controller Software/BIOS Design Guide 24081D—February 2002 Processor Processor 2 Processor System Only Host to PCI Bridge Device 0:F0/F1 PCI Devices Southbridge PCI-to-PCI Bridge Master Device 1:F0 PCI-to-PCI (Future Interface) Bridge Device 1:F1 Figure 3. AMD-761™ System Controller Logical Bus Hierarchy Chapter 2 AMD-761™...
Page 32: I/O Register Map
24081D—February 2002 2.4.1 I/O Register Map The AMD-761 system controller implements some I/O registers (accessed by processor I/O instructions). These registers, as presented in Table 5, are the Configuration Address and Configuration Data registers as specified in PCI Local Bus Specification, Revision 2.2.
Page 33 Preliminary Information AMD-761™ System Controller Software/BIOS Design Guide 24081D—February 2002 Configuration Address Register Type 0 I/O:0CF8 Config_En Reserved Reset PCI_Bus_Num Reset Dev_Num Func_Num Reset Reg_Num Reserved Reset Register Description When writes to the configuration address register have [23:16] == 0h00, a Type 0 configuration access is specified.
Page 34 This bit field defines which device is accessed in the system. Devices are assigned numbers in a system by tying the device IDSEL wire to a specific PCI AD wire. The AMD-761 system controller decodes this field and asserts the appropriate AD wire during the address phase to select the defined device.
Page 35 Preliminary Information AMD-761™ System Controller Software/BIOS Design Guide 24081D—February 2002 Configuration Address Register Type 1 I/O:0CF8 Config_En Reserved Reset PCI_Bus_Num Reset Dev_Num Func_Num Reset Reg_Num Reserved Reset Register Description When writes to the configuration address register have [23:16] ~= 0h00, a type 1 configuration access is specified.
Page 36 This bit field defines which PCI bus in the system is referenced with this address. The AMD-761™ system controller logically implements two PCI buses. The main PCI bus normally enumerates as bus 0 and the AGP bus enumerates as bus 1.
Page 37 Preliminary Information AMD-761™ System Controller Software/BIOS Design Guide 24081D—February 2002 Configuration Data I/O:0CFC Config_Data Reset Config_Data Reset Config_Data Reset Config_Data Reset Register Description Bit Definitions Configuration Data (I/O:0CFC) Name Function 31—0 Config_Data Configuration Data This bit field is used to access the PCI configuration register specified in the Configuration Address register above.
Page 38: Configuration Register Access
Configuration accesses in the AMD-761 system controller conform to the following rules: „ The AMD-761 system controller is defined to be function 0 and 1, device 0; and function 0, device 1. The IDSEL pin of all external PCI devices must be wired to 1 of AD[31:13] as logically [12:11] are assigned to device 0, 1 (AMD-761 system controller).
Page 39: Device 0: Pci Configuration Registers
Preliminary Information AMD-761™ System Controller Software/BIOS Design Guide 24081D—February 2002 2.4.3 Device 0: PCI Configuration Registers In Table 6, the column entitled Offset consists of the register number specified in the Configuration Address register bits [7:2] concatenated with 0b00 to form a simple 1-byte offset.
Page 40 Preliminary Information AMD-761™ System Controller Software/BIOS Design Guide 24081D—February 2002 Table 6. Device 0, Function 0 Configuration Register Map (Continued) Host to PCI Bridge (Device 0, Function 0) Offset Reference Reserved 0x68–0x6B Reserved 0x6C–0x6F “Dev0:F0:0x70” Memory Status/Control 0x70–0x73 on page 66 Reserved 0x74–0x77...
Page 41 Preliminary Information AMD-761™ System Controller Software/BIOS Design Guide 24081D—February 2002 Table 6. Device 0, Function 0 Configuration Register Map (Continued) Host to PCI Bridge (Device 0, Function 0) Offset Reference “Dev0:F0:0xC8” Memory Base Address 2 0xC8–0xCB on page 95 “Dev0:F0:0xCC”...
Page 42 Preliminary Information AMD-761™ System Controller Software/BIOS Design Guide 24081D—February 2002 PCI ID Dev0:F0:0x00 Dev_ID Reset Dev_ID Reset Vend_ID Reset Vend_ID Reset Register Description AMD-761™ System Controller Programmer’s Interface Chapter 2...
Page 43 This 16-bit field is assigned by the device manufacturer and identifies the type of device. The current Northbridge device ID assignments are: AMD-761™ system controller — AMD Athlon™ processor, 1P DDR 133 MHz 0x700E host to PCI bridge 0x700F PCI-to-PCI bridge (4-X AGP) AMD-762™...
Page 44 Preliminary Information AMD-761™ System Controller Software/BIOS Design Guide 24081D—February 2002 PCI Command and Status Dev0:F0:0x04 Trgt_ABRT PERR_Rcv SERR_Sent Mas_ABRT Trgt_ABRT DEVSEL_Timing Data_PERR _ Signaled Reset R/W1C R/W1C R/W1C Fast_B2B Cap_Lst Reserved Reset Reserved FBACK SERR Reset STEP PERR MWINV SCYC...
Page 45 This bit is always 0 because the AMD-761 system controller does not report parity errors. Fast B2B Fast Back-to-Back Capable This bit is always 0, indicating that the AMD-761 system controller as a target is not capable of accepting fast back-to-back transactions when the transactions are not to the same agent.
Page 46 PCI bus. Programming Notes Table 7 lists the controls required to enable the assertion of the AMD-761 SERR# pin and the various status bits that can be read to determine when the SERR# and A_SERR# pins have been asserted.
Page 47 Indicates a Host/PCI bridge. 7–0 Rev_ID Revision Identification Identifies revision number of the device. Programming Notes Refer to the AMD-761™ System Controller Revision Guide, order# 23613, for details of the Rev_ID field for each silicon revision. Chapter 2 AMD-761™ System Controller Programmer’s Interface...
Page 48 Reserved Reserved 23–16 Header_Type Header Type Bit 23 is always 0, indicating that the AMD-761™ system controller is a single function device. Bits [22:16] are 0, indicating that Type 00 configuration space header format is supported. 15–8 Lat_Timer Latency Timer This bit field defines the minimum amount of time in PCI clock cycles that the bus master can retain ownership of the bus.
Page 49 Preliminary Information AMD-761™ System Controller Software/BIOS Design Guide 24081D—February 2002 Base Address 0: AGP Virtual Address Space Dev0:F0:0x10 Base- Base_Addr_High Addr_Low Reset Base_Addr_Low Reset Base_Addr_Low Reset Base_Addr_Low Prefetchable Type Memory Reset Register Description This register is used by system BIOS memory mapping software to allocate virtual address space for AGP.
Page 50 Preliminary Information AMD-761™ System Controller Software/BIOS Design Guide 24081D—February 2002 Bit Definitions Base Address 0: AGP Virtual Address Space (Dev0:F0:0x10) Name Function 31–25 Base_Addr_High Base Address High This bit field forms the upper part of BAR0. This field is loaded by BIOS software. Note that when the GART enable bit in the AGP Virtual Address Space Size register is 0 (see “Dev0:F0:0xAC”...
Page 51 Preliminary Information AMD-761™ System Controller Software/BIOS Design Guide 24081D—February 2002 Base Address 1: GART Memory-Mapped Register Base Dev0:F0:0x14 Base_Addr_High Reset Base_Addr_High Reset Base_Addr_High Base_Addr_Low Reset Base_Addr_Low Prefetchable Type Memory Reset Register Description This register provides the base address for the GART memory-mapped configuration register space (see “Memory- Mapped Register Map”...
Page 52 Preliminary Information AMD-761™ System Controller Software/BIOS Design Guide 24081D—February 2002 Bit Definitions Base Address 1: GART Memory-Mapped Register Base (Dev0:F0:0x14) Name Function 31–12 Base_Addr_High Base Address High This bit field forms the upper part of BAR1. This field is loaded by BIOS software.
Page 53 Preliminary Information AMD-761™ System Controller Software/BIOS Design Guide 24081D—February 2002 AGP/PCI Capabilities Pointer Dev0:F0:0x34 Reserved Reset Reserved Reset Reserved Reset CAP_PTR Reset Register Description Bit Definitions AGP/PCI Capabilities Pointer (Dev0:0x34) Name Function 31–8 Reserved Reserved 7–0 CAP_PTR Capabilities Pointer This field contains a byte offset into a device’s configuration space containing the first item in the capabilities list.
Page 54 Preliminary Information AMD-761™ System Controller Software/BIOS Design Guide 24081D—February 2002 Extended BIU Control Dev0:F0:0x44 Reserved Reset Reserved Reserved Reset Reserved Reserved P0_WrDataDly Reset SIP Stream Reserved Reserved Reserved Reserved P0_2BitPF Reset Register Description This register provides controls for the processor interface, in addition to the BIU Control register at Dev 0:F0:0x60 for Processor 0.
Page 55 P0_2BitPF Two Bit Times Per Frame Enable This bit enables the use of the two bit time commands on the AMD Athlon™ processor system bus. This bit must be set when connected to an AMD Athlon processor and disabled when connected to an Alpha processor. For proper operation, BIOS must not clear this bit once it has been set.
Page 56 Preliminary Information AMD-761™ System Controller Software/BIOS Design Guide 24081D—February 2002 ECC Mode/Status Dev0:F0:0x48 Reserved Reset Reserved Reset SERR_Enable Reserved ECC_Diag ECC_Mode ECC_Status Reset R/W1C ECC_CS_MED ECC_CS_SED Reset Register Description This register provides ECC mode control and status reporting for the DRAM system.
Page 57 The ECC status bits and corresponding failing chip-select indicators are set by the first error detected of each type (SED or MED). The AMD-761 system controller does not log any new errors of each type or assert SERR# until software clears the associated ECC_Status bit by writing a 1.
Page 58 Preliminary Information AMD-761™ System Controller Software/BIOS Design Guide 24081D—February 2002 Bit Definitions (Continued) ECC Mode/Status (Dev0:F0:0x48) Name Function 7–4 ECC_CS_MED Multiple Bit Error Chip Select These bits provide the binary encoded chip select for the first multiple-bit error detected by the AMD-761™ system controller.
Page 59 Preliminary Information AMD-761™ System Controller Software/BIOS Design Guide 24081D—February 2002 PCI Control Dev0:F0:0x4C Reserved Reset Reserved Reset Reserved Reserved Reserved Reserved Reset WSC_DIR Reserved Reserved Reserved PCI_DT_En PCI_OR_En Func1_En (See Note.) Reset Register Description This register controls various functions in the primary PCI and AGP interfaces.
Page 60 Refer to See Chapter 5, “PCI Bus Interface” on page 195 for more information on the transaction options in the AMD-761 system controller. Refer to See Chapter 7, “Recommended BIOS Settings” on page 211 for the recommended bit settings for these bits.
Page 61 Preliminary Information AMD-761™ System Controller Software/BIOS Design Guide 24081D—February 2002 AMD Athlon™ Processor System Bus Dynamic Compensation Dev0:F0:0x50 Reserved Reset PVal NVal Reset BYP_P BYP_N Reset SlewCntl Reserved Reset Register Description Note that the default value of the BYP, BYP_P, and BYP_N fields of this register can be optionally controlled by SIP bits when loading the SIP stream from external ROM.
Page 62 This field reflects the P transistor strength value that was automatically written to the AMD Athlon™ processor system bus I/O pads by the auto-compensation circuit. In bypass mode (bit 4=1) this field returns the values in the BYP_P field (bits [15:12]). The P values are active Low.
Page 63 Preliminary Information AMD-761™ System Controller Software/BIOS Design Guide 24081D—February 2002 DRAM Timing Dev0:F0:0x54 SBPWaitState AddrTiming_A AddrTiming_B RD_Wait_State Reg_DIMM_En Reset Reserved Idle_Cyc_Limit Reset PH_Limit Reserved Reset Reset Register Description This register defines the DRAM timing parameters for all banks. BIOS software must set appropriate values in this register before setting the SDRAM_Init bit (See “Bit Definitions DRAM Mode/Status (Dev0:F0:0x58)”...
Page 64 Reg_DIMM_En Registered DIMM Enable This bit enables the use of registered DIMMs on the motherboard. AMD-761™ system controller 0 = Unbuffered DIMMs 1 = Registered DIMMs Write Data In to Read Command Delay This bit controls the number of clock cycles that must occur between the last valid write operation and the next read command.
Page 65 Preliminary Information AMD-761™ System Controller Software/BIOS Design Guide 24081D—February 2002 Bit Definitions (Continued) DRAM Timing (Dev0:F0:0x54) Name Function 25-24 Write Recovery Time This bit field controls the number of clock cycles that must occur from the last valid write operation to the earliest time a new precharge command can be asserted to the same bank.
Page 66 Preliminary Information AMD-761™ System Controller Software/BIOS Design Guide 24081D—February 2002 Bit Definitions (Continued) DRAM Timing (Dev0:F0:0x54) Name Function 11–9 This bit field indicates the timing value (bank cycle time: minimum time from activate to activate of same bank). 111 = 10 cycles 110 = 9 cycles 101 = 8 cycles (recommended “safe”...
Page 67: Table 8. Wait State Settings For Dram Timing Register
Preliminary Information AMD-761™ System Controller Software/BIOS Design Guide 24081D—February 2002 Bit Definitions (Continued) DRAM Timing (Dev0:F0:0x54) Name Function 1–0 This bit field (t ) is the timing value (RAS to CAS latency, delay from activate to RD/WR command). 11 = 4 cycles 10 = 3 cycles (recommended “safe”...
Page 68 Preliminary Information AMD-761™ System Controller Software/BIOS Design Guide 24081D—February 2002 DRAM Mode/Status Dev0:F0:0x58 Clk_Dis5 Clk_Dis4 Clk_Dis3 Clk_Dis2 Clk_Dis1 Clk_Dis0 SDRAM_Init Reserved Reset R/W1S Mode_Reg STR_Control Burst_Ref_En Ref_Dis Cyc_Per_Ref _ Status Reset R/W1S Reserved Reset CS7_X4Mode CS6_X4Mode CS5_X4Mode CS4_X4Mode CS3_X4Mode CS2_X4Mode CS1_X4Mode CS0_X4Mode...
Page 69 Preliminary Information AMD-761™ System Controller Software/BIOS Design Guide 24081D—February 2002 Bit Definitions DRAM Mode/Status (Dev0:F0:0x58) Name Function Clk_Dis5 Clock Disable This bit controls the DDR CLKOUT5/CLKOUT5# differential clock pair: 0 = Clock pair enabled 1 = Clock pair disabled (three-stated) Note: This bit is meant to disable the clock pair when it is not connected to anything.
Page 70 00 = Default. These bits are cleared to this state any time the RESET# pin is asserted. The AMD-761 memory controller always drives the CKE pins inactive (Low) while these bits are Low. 01 = BIOS sets this pattern after the system resumes from S4 (suspend to disk), S5 (soft off), or mechanical off states.
Page 71 Preliminary Information AMD-761™ System Controller Software/BIOS Design Guide 24081D—February 2002 Bit Definitions (Continued) DRAM Mode/Status (Dev0:F0:0x58) Name Function 17—16 Cyc_Per_Ref Cycles Per Refresh Refresh counter defines period of refresh requests. The following table shows the relationship between the values in this field and the...
Page 72 Preliminary Information AMD-761™ System Controller Software/BIOS Design Guide 24081D—February 2002 Programming Notes Note that some bits of this register are not initialized at reset time, and all bits must be initialized by BIOS for proper operation. This action should be done prior to attempting DRAM access.
Page 73 _Discon_En Reset SysDC_Out Prb_Limit Ack_Limit Bypass_En _Dly Reset Pinstrapping SysDC_Out SysDC_In_Dly WR2_RD RD2_WR _Dly Reset Pinstrapping Register Description This register provides general status and control for the AMD Athlon™ processor system bus interface. Chapter 2 AMD-761™ System Controller Programmer’s Interface...
Page 74 Stp_Grant_ Stop Grant Disconnect Enable Discon_En 0 = No AMD Athlon processor system bus disconnect is performed following STOP/GRANT. 1 = AMD Athlon processor system bus disconnects after receiving a STOP/GRANT special cycle. 16–14 Prb_Limit Probe Limit BIOS software initializes this field with the maximum number of outstanding probes that the given CPU can handle.
Page 75 WR2 Read This field defines the number of SysClk cycles that are inserted between write data and read data cycles to allow the AMD Athlon™ processor system bus data wires to turn around. This field is initialized by pinstrapping during reset.
Page 76 Reset Pinstrapping Sys_Rst_Clk_Offset Sys_Data_Rec_Mux_PreLd Sys_Addr_Rec_Mux_PreLd Reset Pinstrapping Register Description This register provides visibility to the serial initialization packet delivered to the AMD Athlon™ processor during the AMD Athlon processor system bus connect protocol. AMD-761™ System Controller Programmer’s Interface Chapter 2...
Page 77 System Data Rec Mux PreLd -- AMD Athlon processor SIP[8:6] _Mux_PreLd This value specifies the number of SysClk phases from the launch of data by the AMD-761 system controller until it can be read from the AMD Athlon receive FIFO.
Page 78 Preliminary Information AMD-761™ System Controller Software/BIOS Design Guide 24081D—February 2002 Memory Status/Control Dev0:F0:0x70 Reserved Reset Reserved Self_Ref_En Reset PCI_Blk_WR Reserved PCI_Pipe_En Reserved Reset Reserved Reserved Reserved Reserved Reserved Reserved Reset Register Description This register provides general status and control for the memory controller.
Page 79 0 = PCI full-block writes do RID/INV probes, forcing the memory controller to wait for probe data movement. 1 = PCI full-block writes do NOP/INV probes. This bit must be clear when the AMD Athlon™ processor is allowed to issue CleanVictimBlock commands. 8–1...
Page 80 Preliminary Information AMD-761™ System Controller Software/BIOS Design Guide 24081D—February 2002 Who Am I (WHAMI) Dev0:F0:0x80 Reserved Reset Reserved Reserved Reserved Reserved BIU0_Present Reset From CPU FirstBusID Reset WHAMI Reset CPUID Register Description AMD-761™ System Controller Programmer’s Interface Chapter 2...
Page 81 15–8 FirstBusID First BusID This field contains the AMD Athlon processor system bus ID of the first processor to read this register: 00h if CPU0 was the first to read WHAMI after reset, 01h if CPU1 was the first to read WHAMI after reset.
Page 82 Preliminary Information AMD-761™ System Controller Software/BIOS Design Guide 24081D—February 2002 PCI Arbitration Control Dev0:F0:0x84 AGP_VGA_BIOS Reset Tgt_Latency Reserved Reserved AGP_Chain_En PCI_Chain_En Reset PCI_WR_Post AGP_WR_Post RD_Data_Err AGP_Erly_Prb PCI_Erly_Prb AGP_Arb_Pipe MDA_Debug SB_Lock_Dis _Rtry _Rtry _Dis _Dis _Dis _Dis Reset Tgt_Lat_Tim PM_Reg_En 15M_Hole...
Page 83 AGP graphics card has a ROM BIOS. Tgt_Latency Target Latency This bit is designed to ensure that the AMD-761™ system controller is compliant to the PCI maximum target latency rule. Note that this compliance applies only to the PCI bus and not the AGP bus.
Page 84 AGP_Erly_Prb_ AGP Early Probe Disable As soon as the AMD-761 system controller detects a PCI write cycle to memory from an external AGP master, it sends a “probe only” request to the processor that is used to flush data from the processor cache. After one or more data phases, a write request is sent to the memory, which also results in a probe.
Page 85 Tgt_Lat_Tim_ Target Latency Timer Disable When the AMD-761™ system controller acts as a PCI target, it has a latency timer that retries the (write) cycle if it cannot respond within 8 bus clocks (16 clocks for the first transfer). When set, this bit disables the AMD-761 system controller’s target latency timer on both the standard PCI and AGP PCI interfaces.
Page 86 Preliminary Information AMD-761™ System Controller Software/BIOS Design Guide 24081D—February 2002 Config Status Dev0:F0:0x88 AGP_Clk_Mux Sys_Clk_Mux Type_Det S2K_Thresh x (from PCI x (from PCI Reset x (from PCI AD[14:12]) x (from PCI AD[7:5]) AD[20]) AD[4]) K7_PP_En IG_PP_En Clk_Speed Reserved S2K0_Bus_Len x (from PCI...
Page 87 When set, this bit indicates that the AMD-761 system controller push-pull drivers are enabled. 21–20 Clk_Speed Clock Speed This bit field defines the speed of the system clock received by the AMD-761 system controller: 00 = 100 MHz 01 = 66 MHz 10 = Reserved 11 = 133 MHz 19–18...
Page 88 Function Bypass_PLLs Bypass PLLs This bit is set for test and debug of the AMD-761™ system controller with the internal PLLs disabled. 0 = AMD-761 system controller PLLs enabled 1 = AMD-761 system controller PLLs bypassed; clocks driven from SYSCLK and AGPCLK...
Page 89 This register is used to define the top of main system memory. It is used to compare the memory addresses of an external PCI master to determine if it is in the range of the AMD-761™ system controller DRAM. If the address compares, then the AMD-761 system controller responds to the bus master access with DEVSEL# assertion.
Page 90 PCI Memory Top This 8-bit field is compared to the incoming PCI bus master address to determine if a memory cycle falls within the AMD-761™ system controller DRAM region, as follows: 31 30 29 28 27 26 25 24 PCIMemTop Field...
Page 91 Preliminary Information AMD-761™ System Controller Software/BIOS Design Guide 24081D—February 2002 AGP Capability Identifier Dev0:F0:0xA0 Reserved Reset Major_Rev Minor_Rev Reset Next_Pointer Reset Cap_ID Reset Register Description Bit Definitions AGP Capability Identifier (Dev0:F0:0xA0) Name Function 31–24 Reserved Reserved 23–20 Major_Rev Major Revision Major revision of the AGP interface specification conformed to by this device.
Page 92 Preliminary Information AMD-761™ System Controller Software/BIOS Design Guide 24081D—February 2002 AGP Status Dev0:F0:0xA4 Max_ReqQ_Depth Reset Reserved Reset Reserved Reserved Reset Reserved Reserved Rates Reset Register Description AMD-761™ System Controller Programmer’s Interface Chapter 2...
Page 93 8–6 Reserved Reserved Address Limit This bit is always 0, indicating that the AMD-761 system controller does not support addresses greater than 4 Gbytes. Fast Write Transfer This bit indicates supports of fast write transfers. 0 = Fast writes not supported...
Page 94 Preliminary Information AMD-761™ System Controller Software/BIOS Design Guide 24081D—February 2002 AGP Command Dev0:F0:0xA8 Reserved Reset Reserved Reset Reserved SBA_En AGP_En Reset Reserved R4G_En Fast_Writes Reserved Data_Transfer_Mode Reset Register Description AMD-761™ System Controller Programmer’s Interface Chapter 2...
Page 95 Sideband Addressing Enable When this bit is set, sideband addressing is enabled. AGP_En AGP Operations Enable When this bit is set, the AMD-761™ system controller accepts AGP operations. When this bit is clear, the AMD-761 system controller ignores AGP operations. 7–6 Reserved...
Page 96 Preliminary Information AMD-761™ System Controller Software/BIOS Design Guide 24081D—February 2002 AGP Virtual Address Space Size Dev0:F0:0xAC Reserved Reset Reserved Vga_IA_En Reset Reserved Reset Reserved VA_Size GART_En Reset Register Description AMD-761™ System Controller Programmer’s Interface Chapter 2...
Page 97 Vga_IA_En ISA Address Aliasing Enable When set, this bit forces the AMD-761™ system controller to alias ISA addresses, which means that address bits [15:10] are not used in decoding. When clear, no ISA aliasing is performed and address bits [15:10] are used for decoding.
Page 98 GART/AGP Mode Control Dev0:F0:0xB0 Reserved Reset NonGART Reserved PDC_En Lv1_Index _Snoop Reset Reserved Reset Reserved Reset Register Description This register provides bits to control specific features of the AMD-761™ system controller AGP implementation. AMD-761™ System Controller Programmer’s Interface Chapter 2...
Page 99 When set, this bit forces AGP accesses that are not in the GART range to cause AMD Athlon™ processor system bus probes to the processor(s). When clear, AGP addresses that fall outside of the GART range do not cause probes.
Page 100 Preliminary Information AMD-761™ System Controller Software/BIOS Design Guide 24081D—February 2002 AGP 4X Dynamic Compensation Dev0:F0:0xB4 PVal NVal Reset Reserved DisStrb Quantum_Cnt Reset Reserved Reserved Reset Always_ FW_Enable 4X_Override Comp3.3 Reserved Compensate Compensate Reset Register Description AMD-761™ System Controller Programmer’s Interface...
Page 101 AGP Command register (Dev 0:F0:0xA8, bit 4). The Fast_Writes status bit in the AGP Status register (Dev 0:F0:0xA4, bit 4) is 0 by default, indicating that the AMD-761™ system controller does not support this feature. Setting this bit forces the status bit to a 1 to indicate support of fast writes.
Page 102: Table 9. I/O Pad Drive Strength And Input Type
Do Compensate This bit is used to initiate a dynamic compensation command on AGP. This bit is cleared by the AMD-761™ system controller when the compensation cycle is complete. See the programming note below on recommendation for exiting bypass mode.
Page 103 Preliminary Information AMD-761™ System Controller Software/BIOS Design Guide 24081D—February 2002 AGP Compensation Bypass Dev0:F0:0xB8 BYP_PDrvXfer BYP_NDrvXfer Reset BYPXfer Reserved PSlewXfer NSlewXfer Reset BYP_PDrvStrb BYP_NDrvStrb Reset BYPStrb Reserved PSlewStrb NSlewStrb Reset Register Description This register allows BIOS to bypass the AGP auto-compensation to directly control the AGP pad configuration.
Page 104 Preliminary Information AMD-761™ System Controller Software/BIOS Design Guide 24081D—February 2002 Bit Definitions AGP Compensation Bypass (Dev0:F0:0xB8) Name Function 31–28 BYP_PDrvXfer P Drive Strength Control This field is used to directly program the P transistor drive strength on all AGP pins except the data strobes.
Page 105 Preliminary Information AMD-761™ System Controller Software/BIOS Design Guide 24081D—February 2002 Bit Definitions (Continued) AGP Compensation Bypass (Dev0:F0:0xB8) Name Function 3–2 PSlewStrb Slew Rate Control This field is used to directly program the rise time in all AGP data strobes (AD_STB[1:0], AD_STB[1:0]#).
Page 106 Preliminary Information AMD-761™ System Controller Software/BIOS Design Guide 24081D—February 2002 Memory Base The AMD-761 system controller DDR memory controller can Address Registers access up to eight banks of DRAM (four DIMMs, one bank per (Dev0:F0:0xC0 to side). These banks are controlled by eight chip selects. These...
Page 107: Table 10. Ddr Memory Base Address Register Locations
Preliminary Information AMD-761™ System Controller Software/BIOS Design Guide 24081D—February 2002 Table 10. DDR Memory Base Address Register Locations Memory Base Address Register 0 Dev0:F0:0xC0 Memory Base Address Register 1 Dev0:F0:0xC4 Memory Base Address Register 2 Dev0:F0:0xC8 Memory Base Address Register 3...
Page 108: Table 11. Amd-761 Dram Addressing Modes
Preliminary Information AMD-761™ System Controller Software/BIOS Design Guide 24081D—February 2002 Bit Definitions Memory Base Address Registers 0–7 (Dev0:F0:0xC0–0xDF) Name Function 31–23 CS_Base Chip-Select Base This bit field defines which 8-Mbyte boundary the given bank services. Incoming addresses are compared against field, subject to the mask field in bits [15:7].
Page 109: Device 0, Function 1: Ddr Pdl Configuration Registers
Device 0, Function 1: DDR PDL Configuration Registers The registers defined in this section are required to implement Double Data Rate (DDR) DRAM in the AMD-761 system controller Northbridge. The function 1 registers control the 18 DDR programmable delay lines (PDL). In Table 12, the column...
Page 110 Reset Register Description This register allows BIOS control of the calibration circuit for the AMD-761™ system controller’s 18 programmable delay lines. Note that this register is not initialized at reset time but must be initialized by BIOS for proper operation. This action should be done prior to attempting DRAM access.
Page 111 Preliminary Information AMD-761™ System Controller Software/BIOS Design Guide 24081D—February 2002 Bit Definitions DDR PDL Calibration Control (Dev0:F1:0x40) Name Function 31–8 Reserved Reserved SW_Recal Software Recalibration Software should write a 1 to this bit to cause recalibration of the PDLs. The hardware recomputes the Cal_Delay values for all PDLs, based on the values of their SW_Cal_Dly fields.
Page 112: Table 13. Pdl Calibration Modes
Preliminary Information AMD-761™ System Controller Software/BIOS Design Guide 24081D—February 2002 Bit Definitions (Continued) DDR PDL Calibration Control (Dev0:F1:0x40) Name Function Act_Dly_Inh Actual Delay Update Inhibit This bit configures the hardware to either update the actual PDLs (Act_Dly values) with new Cal_Delay values or not. The setting of this bit affects both auto-calibration and SWCalibration but not the Use_Act_Dly method.
Page 113: Table 14. Ddr Pdl Configuration Register Locations
Preliminary Information AMD-761™ System Controller Software/BIOS Design Guide 24081D—February 2002 Table 14. DDR PDL Configuration Register Locations DDR PDL Configuration Register 0 Dev0:F1:0x44 DDR PDL Configuration Register 1 Dev0:F1:0x48 DDR PDL Configuration Register 2 Dev0:F1:0x4C DDR PDL Configuration Register 3...
Page 114 Preliminary Information AMD-761™ System Controller Software/BIOS Design Guide 24081D—February 2002 DDR PDL Configuration Registers Clk_Dly Reset SW_Cal_Dly Reset Cal_Dly Reset Act_Dly Reset Register Description These registers allow configuration of programmable delay lines 0–17. There are a total of 18 PDLs (one per DDR DQS pin in x4 mode).
Page 115 Preliminary Information AMD-761™ System Controller Software/BIOS Design Guide 24081D—February 2002 Bit Definitions DDR PDL Configuration Registers 0–17 (Dev0:F1:0x44–0x8B) Name Function 31–24 Clk_Dly Clock Delay This field provides the number of buffers that amount to one half-period of the system clock.
Page 116 Preliminary Information AMD-761™ System Controller Software/BIOS Design Guide 24081D—February 2002 DDR DQS/MDAT Pad Configuration Dev0:F1:0x8C Reserved PSlewMDAT NSlewMDAT Reset Reserved PDrvMDAT NDrvMDAT Reset Reserved PSlewDQS NSlewDQS Reset Reserved PDrvDQS NDrvDQS Reset Register Description This register allows BIOS control of the DDR DQS and memory data pad drive strength and slew rate.
Page 117 Preliminary Information AMD-761™ System Controller Software/BIOS Design Guide 24081D—February 2002 Bit Definitions DDR DQS/MDAT Pad Configuration (Dev0:F1:0x8C) Name Function 31–30 Reserved Reserved 29–27 PSlewMDAT MDAT Rising Edge Slew Rate These bits control the rising edge slew rate of the MDAT[63:0] and DM[8:0] pins.
Page 118 Preliminary Information AMD-761™ System Controller Software/BIOS Design Guide 24081D—February 2002 Bit Definitions (Continued) DDR DQS/MDAT Pad Configuration (Dev0:F1:0x8C) Name Function 17–16 NDrvMDAT MDAT N Transistor Drive Strength These bits control the N transistor drive strength of the MDAT[63:0] and DM[8:0] pins.
Page 119 Preliminary Information AMD-761™ System Controller Software/BIOS Design Guide 24081D—February 2002 Bit Definitions (Continued) DDR DQS/MDAT Pad Configuration (Dev0:F1:0x8C) Name Function 3–2 PDrvDQS DQS P Transistor Drive Strength These bits control the P transistor drive strength of the DQS[8:0] pins (and DM[8:0] pins) when any chip select is configured for x4 DIMMs in the DRAM Mode/Status register at Dev 0:F0:0x58).
Page 120 Preliminary Information AMD-761™ System Controller Software/BIOS Design Guide 24081D—February 2002 DDR CLK/CS Pad Configuration Dev0:F1:0x90 Reserved PSlewCLK NSlewCLK Reset Reserved PDrvCLK NDrvCLK Reset Reserved PSlewCS NSlewCS Reset Reserved PDrvCS NDrvCS Reset Register Description This register allows BIOS control of the DDR clocks and chip-selects pad drive strength and slew rate.
Page 121 Preliminary Information AMD-761™ System Controller Software/BIOS Design Guide 24081D—February 2002 Bit Definitions DDR CLK/CS Pad Configuration (Dev0:F1:0x90) Name Function 31–30 Reserved Reserved 29–27 PSlewCLK Clocks Rising Edge Slew Rate These bits control the rising edge slew rate of the CLKOUT[5:0] and CLKOUT[5:0]# pins.
Page 122 Preliminary Information AMD-761™ System Controller Software/BIOS Design Guide 24081D—February 2002 Bit Definitions (Continued) DDR CLK/CS Pad Configuration (Dev0:F1:0x90) Name Function 13–11 PSlewCS CS Rising Edge Slew Rate These bits control the rising edge slew rate of the CS[7:0]# pins. 000 = Slew rate 0 (slowest)
Page 123 Preliminary Information AMD-761™ System Controller Software/BIOS Design Guide 24081D—February 2002 DDR CMDB/CMDA Pad Configuration Dev0:F1:0x94 Reserved PSlewCMDB NSlewCMDB Reset Reserved PDrvCMDB NDrvCMDB Reset Reserved PSlewCMDA NSlewCMDA Reset Reserved PDrvCMDA NDrvCMDA Reset Register Description This register allows BIOS control of the DDR RASA#, RASB#, CASA#, CASB#, WEA#, WEB#, CKEA#, and CKEB# pad drive strength and slew rate.
Page 124 Preliminary Information AMD-761™ System Controller Software/BIOS Design Guide 24081D—February 2002 Bit Definitions DDR CMDB/CMDA Pad Configuration (Dev0:F1:0x94) Name Function 31–30 Reserved Reserved 29–27 PSlewCMDB Command B Rising Edge Slew Rate These bits control the rising edge slew rate of the RASB#, CASB#, WEB#, and CKEB# pins.
Page 125 Preliminary Information AMD-761™ System Controller Software/BIOS Design Guide 24081D—February 2002 Bit Definitions (Continued) DDR CMDB/CMDA Pad Configuration (Dev0:F1:0x94) Name Function 13–11 PSlewCMDA Command A Rising Edge Slew Rate These bits control the rising edge slew rate of the RASA#, CASA#, WEA#, and CKEA# pins.
Page 126 Preliminary Information AMD-761™ System Controller Software/BIOS Design Guide 24081D—February 2002 DDR MAB/MAA Pad Configuration Dev0:F1:0x98 Reserved PSlewMAB NSlewMAB Reset Reserved PDrvMAB NDrvMAB Reset Reserved PSlewMAA NSlewMAA Reset Reserved PDrvMAA NDrvMAA Reset Register Description This register allows BIOS control of the DDR MAA and MAB address bus pad drive strength and slew rate.
Page 127 Preliminary Information AMD-761™ System Controller Software/BIOS Design Guide 24081D—February 2002 Bit Definitions DDR MAB/MAA Pad Configuration (Dev0:F1:0x98) Name Function 31–30 Reserved Reserved 29–27 PSlewMAB MAB Rising Edge Slew Rate These bits control the rising edge slew rate of the MAB[14:0] pins.
Page 128 Preliminary Information AMD-761™ System Controller Software/BIOS Design Guide 24081D—February 2002 Bit Definitions (Continued) DDR MAB/MAA Pad Configuration (Dev0:F1:0x98) Name Function 13–11 PSlewMAA MAA Rising Edge Slew Rate These bits control the rising edge slew rate of the MAA[14:0] pins. 000 = Slew rate 0 (slowest)
Page 129: Device 1: Pci-To-Pci Bridge Configuration Registers
Device 1: PCI-to-PCI Bridge Configuration Registers The registers defined in this section are required to implement the PCI-to-PCI bridge function (device 1) in the AMD-761 system controller Northbridge. In Table 15, the column entitled Offset consists of the register number specified in the Configuration Address register bits [7:2] concatenated with 0b00 to form a simple 1-byte offset.
Page 130 Preliminary Information AMD-761™ System Controller Software/BIOS Design Guide 24081D—February 2002 AGP/PCI ID Dev1:0x00 Dev_ID Reset Dev_ID Reset Vend_ID Reset Vend_ID Reset Register Description AMD-761™ System Controller Programmer’s Interface Chapter 2...
Page 131 This 16-bit register is assigned by the device manufacturer and identifies the type of device. The current Northbridge device ID assignments are: AMD-761™ system controller — AMD Athlon™ processor, 1P DDR 133 MHz 0x700E host to PCI bridge 0x700F PCI-to-PCI bridge (4X AGP) AMD-762™...
Page 132 The AGP/PCI Command and Status register provides coarse control over the PCI-PCI bridge function within the AMD-761™ system controller. This register controls the ability to generate and respond to PCI cycles on both the AGP bus and the PCI bus.
Page 133 This bit is always 0 because the AMD-761 system controller does not report data parity errors. Fast_B2B Fast Back-to-Back Capable This bit is always 0, indicating that the AMD-761 system controller as a target is not capable of accepting fast back-to-back transactions when the transactions are not to the same agent. User-Definable Features This bit is always 0, indicating that UDF is not supported on the AMD-761 system controller.
Page 134 This bit is always 0 because the AMD-761 system controller does not report data parity errors. VGA Palette Snoop Enable This bit is always 0, indicating that the AMD-761 system controller does not snoop the VGA palette address range. MWINV...
Page 135 Preliminary Information AMD-761™ System Controller Software/BIOS Design Guide 24081D—February 2002 AGP/PCI Revision ID and Class Code Dev1:0x08 Class_Code Reset Sub-Class_Code Reset Prog_I/F Reset Rev_ID Reset Register Description Bit Definitions AGP/PCI Revision ID and Class Code (Dev1:0x08) Name Function 31–24 Class_Code Class Code This field is always 06h, indicating that it is a bridge device.
Page 136 Reserved Reserved 23–16 Header_Type Header Type Bit 23 is always 0, indicating that the AMD-761™ system controller is a single function device. Bits 22:16 are 0x01, indicating that type 01 configuration space header format is supported (PCI-to-PCI bridge). 15–8 Pri_Lat_Timer...
Page 137 Preliminary Information AMD-761™ System Controller Software/BIOS Design Guide 24081D—February 2002 AGP/PCI Sub Bus Number/Secondary Latency Timer Dev1:0x18 Secon_Lat_Timer Reset Sub-Bus_Num Reset Secon_Bus_Num Reset Pri_Bus_Num Reset Register Description Chapter 2 AMD-761™ System Controller Programmer’s Interface...
Page 138 Preliminary Information AMD-761™ System Controller Software/BIOS Design Guide 24081D—February 2002 Bit Definitions AGP/PCI Sub Bus Number/Secondary Latency Timer (Dev1:0x18) Name Function 31–24 Secon_Lat_Timer Secondary Latency Timer Adheres to the definition of the latency timer in the PCI Local Bus Specification, Revision 2.2, but only applies to the secondary interface of a PCI-to-PCI bridge.
Page 139 Preliminary Information AMD-761™ System Controller Software/BIOS Design Guide 24081D—February 2002 AGP/PCI Status, I/O Base and Limit Dev1:0x1C Trgt_ABRTS PERR_Rcv SERR_Rcv Mas_ABRT Trgt_ABRT DEVSEL_Timing Data_PERR _Signaled Reset R/W1C Fast_B2B Cap_Lst Reserved Reset IO_Lim[15:12] IO_Lim_R Reset IO_Base[15:12] IO_Base_R Reset Register Description The Secondary Status register reflects the conditions of the secondary PCI-to-PCI bridge interface (the AGP bus). The I/O Base register defines the bottom (inclusive) of an address range that is used by the bridge to determine when to forward I/O transactions from one interface to the other.
Page 140 This bit is always 0 because the AMD-761 system controller does not report data parity errors. Fast_B2B Fast Back-to-Back Capable This bit is always 0, indicating that the AMD-761 system controller as a target is not capable of accepting fast back-to-back transactions when the transactions are not to the same agent. User-Definable Features This bit is always 0, indicating that UDF is not supported on the AMD-761 system controller.
Page 141 Preliminary Information AMD-761™ System Controller Software/BIOS Design Guide 24081D—February 2002 Bit Definitions (Continued) AGP/PCI Status, I/O Base and Limit (Dev1:0x1C) Name Function 7–4 IO_Base[15:12] I/O Base (Write) The upper writable 4 bits define the bottom address of an address range that is used by the bridge to determine when to forward I/O transactions from one interface to the other.
Page 142 Preliminary Information AMD-761™ System Controller Software/BIOS Design Guide 24081D—February 2002 AGP/PCI Memory Limit and Base Dev1:0x20 MLim[31:20] Reset MLim[31:20] Reserved Reset MBase[31:20] Reset MBase[31:20] Reserved Reset Register Description AMD-761™ System Controller Programmer’s Interface Chapter 2...
Page 143 Preliminary Information AMD-761™ System Controller Software/BIOS Design Guide 24081D—February 2002 Bit Definitions AGP/PCI Memory Limit and Base (Dev1:0x20) Name Function 31–20 MLim[31:20] Memory Limit Address Memory limit address defines the top address of the non-prefetchable address range used by the AGP target (graphics controller) where control registers and FIFO-like communication interfaces are mapped.
Page 144 Preliminary Information AMD-761™ System Controller Software/BIOS Design Guide 24081D—February 2002 AGP/PCI Prefetchable Memory Limit and Base Dev1:0x24 Prefet_Mem_Lim Reset Prefet_Mem_Lim Reserved Reset Prefet_Mem_Base Reset Prefet_Mem_Base Reserved Reset Register Description AMD-761™ System Controller Programmer’s Interface Chapter 2...
Page 145 Preliminary Information AMD-761™ System Controller Software/BIOS Design Guide 24081D—February 2002 Bit Definitions Bit Definitions AGP/PCI Prefetchable Memory Limit and Base (Dev1:0x24) Name Function 31–20 Prefet_Mem_Lim Prefetchable Memory Limit Address Prefetchable memory limit address defines the top address of the prefetchable address range used by the AGP target (graphics controller) where control registers and FIFO-like communication interfaces are mapped.
Page 146 Preliminary Information AMD-761™ System Controller Software/BIOS Design Guide 24081D—February 2002 AGP/PCI I/O Limit and Base Upper 16 Bits Dev1:0x30 Reserved Reset I/O_Lim[23:16] Reset Reserved Reset I/O_Base[23:16] Reset Register Description This set of registers define the valid range of 32-bit I/O addresses that are allowed to be forwarded from the host to the AGP/PCI.
Page 147 Reserved Reserved Bridge_Fast_ Fast Back-to-Back Capable B2B_En This bit is always 0, indicating that the AMD-761™ system controller as a master is not capable of generating fast back-to-back transactions to different agents on the secondary bus. Secon_Bus_Reset Secondary Bus Reset This bit is always 0.
Page 148 SERR enable bit (Dev 1:F0:0x04) to allow an AGP SERR# to be propagated to the AMD-761™ system controller PCI SERR# pin. Refer to Table 7 on page 34 for details about SERR# assertion and status.
Page 149 Preliminary Information AMD-761™ System Controller Software/BIOS Design Guide 24081D—February 2002 Miscellaneous Device 1 Control Dev1:0x40 Reserved Reset Reserved Reset Reserved Reset Reserved Int_Pin_Cntl Reset Register Description Bit Definitions Miscellaneous Device 1 Control (Dev1:0x40) Name Function 31–1 Reserved Reserved Int_Pin_Cntl Interrupt Pin Control This bit controls the IntPin field in AGP/PCI Interrupt and Bridge Control register (Dev1:0x3C).
Page 150: Memory-Mapped Registers
24081D—February 2002 Memory-Mapped Registers The AMD-761 system controller implements a set of memory- mapped control registers as shown in Section 2.5.2 on page 140. Th e b a se fo r t h e s e reg is t e rs is d ef i n ed i n BA R 1 ( s ee “Dev0:F0:0x14”...
Page 151 Preliminary Information AMD-761™ System Controller Software/BIOS Design Guide 24081D—February 2002 AMD-761™ System Controller Physical Northbridge Memory Table Cache 1K Table Entries GART Table 16 Entries Fully Associative 1K Table Entries GART Directory Directory Cache Directory Entry 2 8 Entries Directory Entry 1...
Page 152: Memory-Mapped Register Map
24081D—February 2002 2.5.2 Memory-Mapped Register Map For registers that are accessed by the AMD-761 system controller miniport driver during run time, the AMD-761 system controller implements a set of memory-mapped registers for quick access. These are defined in Table 16.
Page 153 Preliminary Information AMD-761™ System Controller Software/BIOS Design Guide 24081D—February 2002 Features and Capabilities Bar1 + 0x00 GART_Cache Reserved Valid_Bit_Err_ID P2P_Status Reserved Valid_Err _Status Reset R/W1C SB_STB_Tog Gar_Valid_ Reserved P2P_En TLB_En _Det Err_En Reset Reserved Hang_En P2P_Cap Link_Cap Valid_Cap Reset Rev_ID...
Page 154 P2P_En P2P Enable This bit is hardwired to 0 to indicate that the AMD-761 system controller only implements those PCI-to-PCI bridge commands required to implement AGP (the AMD-761 system controller does not implement a complete PCI 2.1-compliant PCI-to-PCI bridge between PCI and AGP).
Page 155 Link_Cap LinkCap This bit is always Low, indicating that GART entry multiple pages are not supported. Valid_Cap ValCap This bit is set to indicate that the AMD-761 system controller supports the detection of valid bit errors. 7–0 Rev_ID Revision ID This field contains the revision identification.
Page 156 Preliminary Information AMD-761™ System Controller Software/BIOS Design Guide 24081D—February 2002 GART Directory Base Address Bar1 + 0x04 GART_Dir_Base_Addr Reset GART_Dir_Base_Addr Reset GART_Dir_Base_Addr Reserved Reset Reserved Reset Register Description Bit Definitions GART Directory Base Address (Bar1 + 0x04) Name Function 31–12...
Page 157 GART Cache Size (Bar1 + 0x08) Name Function 31–0 GART_Cache_Size GART Cache Size The AMD-761™ system controller implements a GART table cache that contains 16 entries, organized as eight-way set associative. Programming Notes Chapter 2 AMD-761™ System Controller Programmer’s Interface...
Page 158 GART Cache Invalidate _Inval This bit is written by the AMD-761™ miniport driver. When set to 1, the AMD-761 system controller invalidates the entire GART directory and table cache. When the invalidate operation is completed, the AMD-761 system controller resets this bit to 0.
Page 159 Preliminary Information AMD-761™ System Controller Software/BIOS Design Guide 24081D—February 2002 GART Table Cache Entry Control Bar1 + 0x10 GART_Tbl_Entry_Addr Reset GART_Tbl_Entry_Addr Reset GART_Tbl_Entry_Addr Reserved Reset Tbl_Inval Reserved Tbl_Update _Entry Reset R/W1S Register Description This register must be written to with doubleword (32-bit or 4-byte) operands.
Page 160 Tbl_Update Table Update When set, this bit forces the AMD-761 system controller to update the GART table cache entry specified in bits [31:12] with the current entry in the GART table in system memory. The update function is performed immediately following the write to this register. When the update operation is completed, this bit is reset to 0.
Page 161: Ddr Sdram Interface
Overview To date, there are two types of DDR memory DIMMs— unbuffered and registered. The AMD-761 system controller can be configured to support up to two unbuffered DIMM slots with two banks each, or up to four registered DIMM slots with two banks each.
Page 162: Ddr Dimms And Ddr Sdrams
Preliminary Information AMD-761™ System Controller Software/BIOS Design Guide 24081D—February 2002 DI MM and me m ory dev ic e ( m em ory chip) t im ing a nd configuration data exist in the Serial Presence Detect (SPD) EEPROM on the DIMM.
Page 163: Ddr Dimm Data From Serial Presence
3.2.2 DDR DIMM Data from Serial Presence Detect (SPD) Device DDR memory systems implemented with the AMD-761 system controller require use of the Serial Presence Detect (SPD) d a t a . T h i s d a t a d e s c r i b e s c o n f i g u ra t i o n a n d s p e e d characteristics of the DDR DIMM and DDR SDRAM devices mounted on the DIMM.
Page 164: Memory Space Configuration
SPD, byte 31. The number of banks on the DIMM is read from SPD byte 5. The AMD-761 system controller DDR SDRAM controller requires 21 bits of configuration information for each chip select—that is, each side of the DIMM. These 21 bits are within a full 32-bit configuration register that contains 11 reserved bits.
Page 165: Table 19. Memory Size Addresses
DDR device address signals. The addressing modes of the AMD-761 system controller memory controller map to industry- standard DDR device symmetries set forth by the Joint Electron Device Engineering Council (JEDEC). Therefore, the addressing mode is set according to the devices on the DIMM.
Page 166: Table 20. Total Memory
Preliminary Information AMD-761™ System Controller Software/BIOS Design Guide 24081D—February 2002 Note: Modes 00b and 11b are reserved. To determine the size of the DDR SDRAM device from SPD data, BIOS needs to read the size of the bank(s) in SPD byte 31 and the device width in byte 13.
Page 167 2-Kbyte boundary. Note that address modes 00b and 11b are reserved, thus this field should never be specified. Table 21. AMD-761™ System Controller DDR SDRAM Addressing Modes Mode Pins Mode 1...
Page 168: Table 22. Memory Sizing Example, 128 Mbytes Total
Preliminary Information AMD-761™ System Controller Software/BIOS Design Guide 24081D—February 2002 Chip Select Enable The Chip Select Enable bit (Dev 0:F0:0xC0, bit [0] through Dev 0:F0:0xDF, bit [0]) specifies whether a bank of memory exists for that corresponding chip select. When enabled with a 1b, the incoming address is eligible to be compared with bits [31:23] and [15:7] for chip-select decode.
Page 169: Ddr Memory Dimm Timings
Please notice that the AMD-761 system controller supports CL=3.0 as the highest CL setting. Some legacy DDR devices support CL=3.0, but most devices available today specify CL=2.5 as a maximum. The AMD-761 system controller does not support CL=1.5. 3.4.1 Memory Timings...
Page 170: Table 24. Cas Latency Settings
The smaller value for CL (2) would represent best performance. BIOS can choose from any legal CL that exists in the SPD for the DIMM. The AMD-761 system controller supports CL values of 2, 2.5, and 3.
Page 171 Preliminary Information AMD-761™ System Controller Software/BIOS Design Guide 24081D—February 2002 The RAS to CAS delay bits (Dev 0:F0:0x54, bits [1:0]) specify the minimum amount of time required between the opening of a page within the DDR device (via an ACTIVATE command) and the issuance of a READ or WRITE command to that same DDR device’s internal bank.
Page 172: Table 25. Ddr Device Timing Values
Preliminary Information AMD-761™ System Controller Software/BIOS Design Guide 24081D—February 2002 current. Byte 28 of the SPD defines the t timing parameter. Refer to Table 25 on page 160 for typical settings. Write Recovery The Write Recovery bits (Dev 0:F0:0x54, bit [25:24]) specify the...
Page 173: Additional Memory Controller Settings
F6 01 8E 5A Additional Memory Controller Settings This section discusses configuration features that are specific to the AMD-761 system controller DDR memory controller. The AMD-761 memory controller contains DDR memory controller settings starting at (Dev 0:F0:0x54). These settings are Page...
Page 174 Preliminary Information AMD-761™ System Controller Software/BIOS Design Guide 24081D—February 2002 adequate to give fair access to the memory sub-system. Therefore, these bits should be set to 10b. A higher page hit limit allows the prioritization of a large amount of consecutive...
Page 175 The Read Wait State bit (Dev 0:F0:0x54, bits [28]) specifies whether more time is needed in the DDR read data round trip loop. The read data round trip loop originates at the AMD-761 system controller DDR CLK outputs and terminates at the AMD-761 system controller internal requester logic.
Page 176 Preliminary Information AMD-761™ System Controller Software/BIOS Design Guide 24081D—February 2002 This bit assumes A bus and B chip-select DIMM socket mapping is such that the B bus uses Chip Select bit [7:6] and [3:2]. This motherboard mapping should be adhered to should BIOS want to control the A bus and B bus HOLD timing separately.
Page 177: Dram Mode/Status Settings
0:F0:0x58). These settings are: x4 DDR device symmetry configuration, refresh control (which includes refresh rate, refresh disable, and burst refresh enable), suspend to RAM (STR) control, DDR device initialization control, and AMD-761 system controller DDR clock output control. Chip-Select Width...
Page 178 Preliminary Information AMD-761™ System Controller Software/BIOS Design Guide 24081D—February 2002 AMD-761 system controller provides a data width selection for each chip select, although it is unlikely that a double banked DIMM can support x4 devices on one side and x8/x16 devices on the other.
Page 179 DDR refresh rate. The refresh rate is tied directly to the clock frequency, thus it is important for BIOS to configure the refresh rate based on the AMD-761 system controller frequency. BIOS should first determine the...
Page 180: Table 28. Refresh Rate
DIMM mapping to a particular DIMM slot. With a system hard reset, these bits are cleared, thus enabling all clock pairs. Because an AMD-761 system controller system reset is issued during a power-managed S3 state, all clocks are re-enabled following the exit from this state. Therefore, BIOS should return to this register and restore the disabled clock pairs that it had previously disabled during POST.
Page 181: Ecc And Memory Scrubbing
DDR device itself, or a faulted bit that occurred during data transmissions from the DDR devices to the AMD-761 system controller memory controller. To support the ECC function, DIMMs must support additional storage for the ECC check bits. When ECC is enabled, the system must have all DDR DIMMs that are 72 bits wide (also called ECC DDR DIMMs).
Page 182 However, because the AMD Athlon processor checks for its own errors, data is passed directly through the AMD-761 system controller without an additional system clock delay.
Page 183 SERR# to allow monitoring, logging, and analysis of ECC errors by software. SysECCEn bit should be set in the AMD Athlon processor when setting "Report ECC Syndrome case." SysECCEn has an MSR address of MSR C001_0010[15].
Page 184: Ecc And Memory Scrubbing Configuration
0x00 is a valid check bit code, so care should be used to not corrupt a location where the user does not expect this valid check bit value to exist. In the ECC_Diag mode, the AMD-761 system controller always writes 0x00 to the ECC byte to aid testing of the ECC logic.
Page 185 AMD Athlon processor, which performs its own data error detection and correction. Therefore, data correction to the AMD Athlon processor is not inhibited in this mode. This mode provides all the benefits of parity checking with little or no performance impact. It is useful in systems that desire status information but not the overhead that is associated with error correcting or scrubbing.
Page 186: Programmable Delay Lines (Pdl)
The ECC status bits and corresponding failing chip-select indicators (see bits below) are set by the first error detected of each type (SED or MED). The AMD-761 system controller does not log any new errors of each type or assert SERR# until software clears the associated ECC_Status bit by writing a 1.
Page 187 PVT near the actual PDLs used to delay the incoming DQS strobes. Each calibration mechanism is hand placed within the AMD-761 system controller to match gate for gate the actual PDL. This approach minimizes error between the calibration mechanism and the actual PDLs.
Page 188 Because the system clock is generated by a PLL in the AMD-761 system controller, and it is already compensated for PVT, the system clock period is independent of PVT.
Page 189 Cal_Dly value that is applied to the PDL based on the SW_Cal_Dly programmed. The SW_Cal_Dly bits are used by AMD-761 system controller to update the delay times in both auto-calibration mode as well as software-initiated calibrations. For example, if the delay required is 1.7 ns and...
Page 190 „ The Act_Dly value is either 31 or 32 (depending on rounding desired) = 0x1F or 0x20. The AMD-761 system controller provides a configuration bit (Act_Dly_Inh) that inhibits the auto calibration state machine from updating the Act_Dly values after the computation of Clk_Dly and Cal_Dly is completed.
Page 191 Preliminary Information AMD-761™ System Controller Software/BIOS Design Guide 24081D—February 2002 Auto_Cal_En The Auto Calibration Enable bit (Dev 0:F1:0x40, bit [5]) provides a way for BIOS to enable the PDL auto calibration function. When this bit is set, all of the Cal_Dly values are...
Page 192: Manual Pdl Window Detection
(Dev 0:F1:0x44, bits [23:16] through Dev 0:F1:0x88, bits [23:16]) is based on calculated round trip timing assuming worst case AMD-761 system controller conditions, worst case DDR DIMM device conditions, and board routing. The most critical timing relationship during a DDR DIMM read is the round trip data delays and the DQS/data relationship relative to each other.
Page 193 Dev 0:F1:0x44, bits [31:24], through Dev 0:F1:0x88, bits [31:24]. By dividing the appropriate period (as applies to the frequency of the AMD-761 system controller) by the values found in the Clock Delay fields yields the “average delay per PDL tap.” Chapter 3...
Page 194: Ddr I/O Drive Strength
Preliminary Information AMD-761™ System Controller Software/BIOS Design Guide 24081D—February 2002 „ Once the appropriate PDL value is determined for each byte or nibble (as it applies), this value must be converted into a Software Calibration Delay value for the auto- calibration logic.
Page 195 Preliminary Information AMD-761™ System Controller Software/BIOS Design Guide 24081D—February 2002 Note: The AMD-761 system controller provides differential clocks, CLKOUTH and CLKOUTL, for the DDR DIMMs. This single CLKOUT drive strength and slew setting applies for both polarities of CLKOUT. „ Device Chip Select (CS[7:0]#) „...
Page 196 Preliminary Information AMD-761™ System Controller Software/BIOS Design Guide 24081D—February 2002 DDR SDRAM Interface Chapter 3...
Page 197: Power Management
Southbridge, or the operating system support of each power management state. Note: To accommodate the S3 state, some of the AMD-761 system controller register bits are not initialized to a known value at power-on with the RESET# signal. The BIOS must...
Page 198: C1 Halt State Requirements
Enabled when the Stp_Grant_Discon_En bit is set in the BIU Status/Control Register (Dev 0:F0:0x60, bit 17). RESET# assertion in S3 state causes AMD-761 system controller to gate off I/O rings so power can be removed from AGP, PCI, and pro- cessor interfaces while VDD_CORE and DDR interface remains pow- ered.
Page 199: C2 Stop Grant State Requirements
0 to the Halt_Discon_En bit in the BIU Status/Control register (Dev 0:F0:0x60, bit 18). This action causes the AMD-761 system controller to react to the Halt special cycle on the AMD Athlon system bus by forwarding the cycle to the PCI bus but not attempting any processor disconnect.
Page 200 The first option requires no special setup in the AMD-761 s y s t e m c o n t ro l l e r o t h e r t h a n t o w r i t e a 0 t o t h e Stp_Grant_Discon_En bit in the BIU Status/Control register (Dev 0:F0:0x60, bit 17).
Page 201: S1 Power-On Suspend State Requirements
D3 state prior to STPCLK# assertion by the Southbridge. The S1 state is supported by the AMD-761 system controller for both unbuffered and registered DDR DIMMs. However, when registered DIMMs are installed in the system (according to the...
Page 202: S3 Suspend To Ram State Requirements
Because no power is removed from the system, and the RESET# signal is not asserted, all AMD -7 61 syst em c ontroller configuration registers retain their original value prior to entering the S1 state.
Page 203: Str Bit Control For S3 Support
„ The Suspend to RAM control bits (STR_Control[1:0]) in the DRAM Mode/Status register (Dev 0:F0:0x58) must be properly controlled by BIOS to force the AMD-761 system controller to properly enter and exit the S3 state. Refer to Section 4.4.1 on page 191 for details.
Page 204 Refer to Section 1.1.3 on page 4 for a list of the AMD-761 system controller configuration registers that are not set to a known value when the RESET# pin is asserted.
Page 205: Clock Throttling
STR_Control by assertion of RESET# pin • AMD-761™ system controller asserts DRAM CKE pins and exits • DRAM CKE pins are asserted by the AMD-761 system controller. self-refresh mode. • BIOS initiates the AMD-761 system controller to start DRAM. •...
Page 206: Ddr Dram Clock Enables
STPCLK# signal. DDR DRAM Clock Enables The AMD-761 system controller is designed to provide BIOS the ability to disable any unused DDR DRAM clock pairs to reduce power and system noise. These clock pairs are controlled by the Clk_Dis[5:0] field in the DRAM Mode/Status register (Dev 0:F0:0x58).
Page 207: Pci Bus Interface
24081D—February 2002 PCI Bus Interface This chapter provides additional details of some of the AMD-761™ system controller PCI interface options that affect system performance and compliance to the PCI Local Bus Specification, Revision 2.2, as well as some recommended settings for the AMD-761 system controller configuration register bits.
Page 208: Delayed Transactions And Target Latency
„ Setting the delayed transaction enable (PCI_DT_En) causes the AMD-761 system controller to latch the address and read command that was initiated by the external master PCI Bus Interface...
Page 209 Delayed Transactions This example assumes that a memory read transaction is and Target Latency initiated by a PCI master and that the AMD-761™ system Disabled controller is unable to return data within the specified 32 PCI clock latency. 1. The AMD-761 system controller initiates a memory read to the memory controller and simultaneously issues a probe to the processor.
Page 210 If this master’s cycle was targeted to another PCI agent, it still could not begin the transaction because the bus is tied up by the previous master and the AMD-761 system controller. 3. Some number of PCI clocks later, the memory subsystem returns read data to the master completing the transaction.
Page 211: Transaction Ordering Rules
1. The processor writes data (memory write) destined to an agent on the PCI bus, and the data is posted in the AMD-761 system controller PCI posting buffer. 2. The processor then sets a flag in memory, informing the PCI agent that the data is written.
Page 212 1. The processor writes data (memory write) destined to an agent on the PCI bus, and the data is posted in the AMD-761 system controller PCI posting buffer. 2. The processor then sets a flag in memory, informing the PCI agent that the data is written.
Page 213: Special Arbitration Considerations For The Southbridge
Example of System with Flag and Data Stored across PCI Bus Domain 5.1.3 Special Arbitration Considerations for the Southbridge To accommodate legacy DMA as is supported in the AMD-766™ peripheral bus controller (the devices connected to the AMD-761 system controller’s SBREQ# and SBGNT# pins), the AMD-761 system controller makes special exceptions in the arbitration for the Southbridge.
Page 214: Pci Performance Optimization Options
Preliminary Information AMD-761™ System Controller Software/BIOS Design Guide 24081D—February 2002 By default, the AMD-761 system controller does not allow the SBREQ# PCI request to be preempted by requests on the normal REQ#[6:0] pins, and it does not disconnect the Southbridge once it has started a transfer.
Page 215: Pci Chaining
The AMD-761 system controller provides two options for bus parking: „ Park on the AMD-761 system controller—that is, CPU accesses to PCI agents „ Park on the last master that had bus tenure...
Page 216 Preliminary Information AMD-761™ System Controller Software/BIOS Design Guide 24081D—February 2002 PCI Bus Interface Chapter 5...
Page 217: Agp Interface
„ Bypass the compensation and allow BIOS to write drive strength values directly to the I/O cells. The AMD-761 system controller allows the AGP strobe signals (ADSTB[1:0], ADSTB[1:0]#) to be controlled independently from all other AGP signals, including the ability to bypass compensation for one set of signals while the other set is compensated and vice-versa.
Page 218: The Agp 4X Dynamic Compensation Register
AGP compensation is controlled by the AGP 4X Dynamic Compensation register (Dev 0:F0:0xB4). This register contains additional fields that are not directly related to compensation but control various attributes of the AMD-761 system controller AGP interface. This section provides additional details about the fields related to compensation.
Page 219: Selection Of 1.5- Or 3.3-V Agp Signalling
TYPDET# pin unconnected. Cards operating in 1.5-V signalling mode have the pin connected to VSS, forcing it to 0. The AMD-761 system controller latches the value of the TYPEDET# pin at reset, and BIOS can read this value in the Configuration Status register (Dev 0:F0:0x88, bit 25).
Page 220: Feature Override Bits For Agp Cards
Accelerated Graphics Port Interface Specification, Revision 2.0. The operating system is thus able to determine and select the highest rate supported by both the AGP card and the AMD-761 system controller. The AGP interface of the AMD-761 system controller includes...
Page 221: Bios Initialization Requirements
1. Detect the signalling level (1.5 V or 3.3 V) by reading the value of the TYPEDET# pin that was latched by the AMD-761 system controller at reset. This value can be read in the Configuration Status register, Dev 0:F0:0x88, bit 25.
Page 222: Agp Miniport Driver Requirements
NSlewStrb [1:0] AGP Miniport Driver Requirements AMD has found that some early generation 4x AGP cards were not consistently implemented using published 4x AGP guidelines for AGP signal impedance and routing. These AGP cards do not work reliably with the default AGP drive-strengths of the AMD-761 system controller.
Page 223: Recommended Bios Settings
BIOS. This is mandatory. No setting can be assumed by default. „ Refer to the actual configuration register descriptions for details of each bit. These can be found in “AMD-761™ System Controller Programmer’s Interface” on page 9 of this document.
Page 224: Pci Bus 0, Device 0, Function 0 Registers
PCI Bus 0, Device 0, Function 0 Registers PCI Bus 0, Device 0, contains configuration registers that are mostly specific to the AMD-761 system controller and its processor, DDR SDRAM, AGP, and PCI bus interfaces. The Bus 0, Device 0 space contains two separate functions as follows: „...
Page 225 Rev B1 = 11h, B2=12h, B3=13h B= Mandatory BIOS function A= AGP setup by BIOS c = Calculated/set by AMD-761™ internal logic KEY: P= Power management setup by BIOS o = Setup by OS or OS driver F = Performance enhancement set by BIOS...
Page 226 PCI specification B= Mandatory BIOS function A= AGP setup by BIOS c = Calculated/set by AMD-761™ internal logic KEY: P= Power management setup by BIOS o = Setup by OS or OS driver F = Performance enhancement set by BIOS...
Page 227 CS of first SED B= Mandatory BIOS function A= AGP setup by BIOS c = Calculated/set by AMD-761™ internal logic KEY: P= Power management setup by BIOS o = Setup by OS or OS driver F = Performance enhancement set by BIOS...
Page 228 1 = Enable Byp_P and Byp_N Reserved B= Mandatory BIOS function A= AGP setup by BIOS c = Calculated/set by AMD-761™ internal logic KEY: P= Power management setup by BIOS o = Setup by OS or OS driver F = Performance enhancement set by BIOS...
Page 229 SPD # 27 B= Mandatory BIOS function A= AGP setup by BIOS c = Calculated/set by AMD-761™ internal logic KEY: P= Power management setup by BIOS o = Setup by OS or OS driver F = Performance enhancement set by BIOS...
Page 230: Example Settings For Memory Timing
SPD # 29 B= Mandatory BIOS function A= AGP setup by BIOS c = Calculated/set by AMD-761™ internal logic KEY: P= Power management setup by BIOS o = Setup by OS or OS driver F = Performance enhancement set by BIOS...
Page 231 Preliminary Information AMD-761™ System Controller Software/BIOS Design Guide 24081D—February 2002 100 MHz 133 MHz 0x0x0x54h SDRAM Timing SPBWaitState 0 @ 100 MHz , 1 @ 133 MHz FSB AddrTiming_A SPD # 21 0 @ Unbuff, 1 @ Reg DIMM AddrTiming_B, SPD # 21...
Page 232 15:8 0_0h B= Mandatory BIOS function A= AGP setup by BIOS c = Calculated/set by AMD-761™ internal logic KEY: P= Power management setup by BIOS o = Setup by OS or OS driver F = Performance enhancement set by BIOS...
Page 233 SPD # 13 B= Mandatory BIOS function A= AGP setup by BIOS c = Calculated/set by AMD-761™ internal logic KEY: P= Power management setup by BIOS o = Setup by OS or OS driver F = Performance enhancement set by BIOS...
Page 234 RO from Init/SIP logic yy_yyyyh B= Mandatory BIOS function A= AGP setup by BIOS c = Calculated/set by AMD-761™ internal logic KEY: P= Power management setup by BIOS o = Setup by OS or OS driver F = Performance enhancement set by BIOS...
Page 235 Who AM I B= Mandatory BIOS function A= AGP setup by BIOS c = Calculated/set by AMD-761™ internal logic KEY: P= Power management setup by BIOS o = Setup by OS or OS driver F = Performance enhancement set by BIOS...
Page 236 B= Mandatory BIOS function A= AGP setup by BIOS c = Calculated/set by AMD-761™ internal logic KEY: P= Power management setup by BIOS o = Setup by OS or OS driver F = Performance enhancement set by BIOS...
Page 237 PCI master B= Mandatory BIOS function A= AGP setup by BIOS c = Calculated/set by AMD-761™ internal logic KEY: P= Power management setup by BIOS o = Setup by OS or OS driver F = Performance enhancement set by BIOS...
Page 238 Reserved 000_0000h B= Mandatory BIOS function A= AGP setup by BIOS c = Calculated/set by AMD-761™ internal logic KEY: P= Power management setup by BIOS o = Setup by OS or OS driver F = Performance enhancement set by BIOS...
Page 239 001b=1x, 010b=2x,100b=4x B= Mandatory BIOS function A= AGP setup by BIOS c = Calculated/set by AMD-761™ internal logic KEY: P= Power management setup by BIOS o = Setup by OS or OS driver F = Performance enhancement set by BIOS...
Page 240 15:0 Reserved B= Mandatory BIOS function A= AGP setup by BIOS c = Calculated/set by AMD-761™ internal logic KEY: P= Power management setup by BIOS o = Setup by OS or OS driver F = Performance enhancement set by BIOS...
Page 241 Clears when finished B= Mandatory BIOS function A= AGP setup by BIOS c = Calculated/set by AMD-761™ internal logic KEY: P= Power management setup by BIOS o = Setup by OS or OS driver F = Performance enhancement set by BIOS...
Page 242 B= Mandatory BIOS function A= AGP setup by BIOS c = Calculated/set by AMD-761™ internal logic KEY: P= Power management setup by BIOS o = Setup by OS or OS driver F = Performance enhancement set by BIOS...
Page 243 B= Mandatory BIOS function A= AGP setup by BIOS c = Calculated/set by AMD-761™ internal logic KEY: P= Power management setup by BIOS o = Setup by OS or OS driver F = Performance enhancement set by BIOS...
Page 244: Examples: Agp Compensation Register Settings
Preliminary Information AMD-761™ System Controller Software/BIOS Design Guide 24081D—February 2002 7.1.2 Examples: AGP Compensation Register Settings (0xB4-0xBB) TYPEDET# Type_Det = 1 indicates that a card in the AGP slot is a 3.3-V 0x0x0x88[25] signalling card, which supports 2X AGP maximum. A 3.3-V signalling card cannot run above 2X AGP.
Page 245 As 0x0x0xC0h above B= Mandatory BIOS function A= AGP setup by BIOS c = Calculated/set by AMD-761™ internal logic KEY: P= Power management setup by BIOS o = Setup by OS or OS driver F = Performance enhancement set by BIOS...
Page 246 As 0x0x0xC0h above B= Mandatory BIOS function A= AGP setup by BIOS c = Calculated/set by AMD-761™ internal logic KEY: P= Power management setup by BIOS o = Setup by OS or OS driver F = Performance enhancement set by BIOS...
Page 247 As 0x0x0xC0h above B= Mandatory BIOS function A= AGP setup by BIOS c = Calculated/set by AMD-761™ internal logic KEY: P= Power management setup by BIOS o = Setup by OS or OS driver F = Performance enhancement set by BIOS...
Page 248: Pci Bus 0, Device 0, Function 1 Registers
DDR SDRAM interface drive strengths, and calibration of the Programmable Delay Lines (PDLs). All Function 1 register bits are defaulted to an unknown value as required for the AMD-761 system controller to support the Advanced Configuration and Power Interface (ACPI) S3 (Suspend to RAM) state.
Page 249 From SW_Recal or Direct Write B= Mandatory BIOS function A= AGP setup by BIOS c = Calculated/set by AMD-761™ internal logic KEY: P= Power management setup by BIOS o = Setup by OS or OS driver F = Performance enhancement set by BIOS...
Page 250 From SW_Recal or Direct Write B= Mandatory BIOS function A= AGP setup by BIOS c = Calculated/set by AMD-761™ internal logic KEY: P= Power management setup by BIOS o = Setup by OS or OS driver F = Performance enhancement set by BIOS...
Page 251 Direct Write B= Mandatory BIOS function A= AGP setup by BIOS c = Calculated/set by AMD-761™ internal logic P= Power management setup by BIOS o = Setup by OS or OS driver F = Performance enhancement set by BIOS KEY:...
Page 252 From SW_Recal or Direct Write B= Mandatory BIOS function A= AGP setup by BIOS c = Calculated/set by AMD-761™ internal logic KEY: P= Power management setup by BIOS o = Setup by OS or OS driver F = Performance enhancement set by BIOS...
Page 253 From SW_Recal or Direct Write B= Mandatory BIOS function A= AGP setup by BIOS c = Calculated/set by AMD-761™ internal logic KEY: P= Power management setup by BIOS o = Setup by OS or OS driver F = Performance enhancement set by BIOS...
Page 254 DQS N Transistor Drv Strength B= Mandatory BIOS function A= AGP setup by BIOS c = Calculated/set by AMD-761™ internal logic KEY: P= Power management setup by BIOS o = Setup by OS or OS driver F = Performance enhancement set by BIOS...
Page 255 CS N Transistor Drv Strength B= Mandatory BIOS function A= AGP setup by BIOS c = Calculated/set by AMD-761™ internal logic KEY: P= Power management setup by BIOS o = Setup by OS or OS driver F = Performance enhancement set by BIOS...
Page 256 CMDA N Transistor Drv Strength B= Mandatory BIOS function A= AGP setup by BIOS c = Calculated/set by AMD-761™ internal logic KEY: P= Power management setup by BIOS o = Setup by OS or OS driver F = Performance enhancement set by BIOS...
Page 257 MAA N Transistor Drv Strength B= Mandatory BIOS function A= AGP setup by BIOS c = Calculated/set by AMD-761™ internal logic KEY: P= Power management setup by BIOS o = Setup by OS or OS driver F = Performance enhancement set by BIOS...
Page 258: Pci Bus 0, Device 1, Function 0 Registers
24081D—February 2002 PCI Bus 0, Device 1, Function 0 Registers Device 1 registers provide the necessary controls for the AMD-761 system controller’s internal PCI-to-PCI bridge and AGP controller functions. The PCI to PCI bridge functions as a logical bridge between the Host PCI bus and the AGP interface and contains the normal PCI configuration registers for such a device.
Page 259 Revision ID B= Mandatory BIOS function A= AGP setup by BIOS c = Calculated/set by AMD-761™ internal logic KEY: P= Power management setup by BIOS o = Setup by OS or OS driver F = Performance enhancement set by BIOS...
Page 260 Secon_Bus_Num Pri_Bus_Num B= Mandatory BIOS function A= AGP setup by BIOS c = Calculated/set by AMD-761™ internal logic KEY: P= Power management setup by BIOS o = Setup by OS or OS driver F = Performance enhancement set by BIOS...
Page 261 B= Mandatory BIOS function A= AGP setup by BIOS c = Calculated/set by AMD-761™ internal logic KEY: P= Power management setup by BIOS o = Setup by OS or OS driver F = Performance enhancement set by BIOS...
Page 262 1-Mbyte granularity. Reserved B= Mandatory BIOS function A= AGP setup by BIOS c = Calculated/set by AMD-761™ internal logic KEY: P= Power management setup by BIOS o = Setup by OS or OS driver F = Performance enhancement set by BIOS...
Page 263 1=Enable 0x1x0x3C[15:8] B= Mandatory BIOS function A= AGP setup by BIOS c = Calculated/set by AMD-761™ internal logic KEY: P= Power management setup by BIOS o = Setup by OS or OS driver F = Performance enhancement set by BIOS...
Page 264 Preliminary Information AMD-761™ System Controller Software/BIOS Design Guide 24081D—February 2002 Recommended BIOS Settings Chapter 7...

AMD -761 Software/Bios Design Manual

1 Overview

SYS_CONFIG Settings

2 System Controller Programmer's Interface

3 DDR SDRAM Interface

4 Power Management

5 PCI Bus Interface

6 AGP Interface

7 Recommended BIOS Settings

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