Sundance Spas SMT364 User Manual
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Sundance Spas SMT364 User Manual

Sundance Spas SMT364 User Manual

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SMT364
User Manual
User Manual (QCF42); Version 3.0, 8/11/00; © Sundance Multiprocessor Technology Ltd. 1999

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Summary of Contents for Sundance Spas SMT364

  • Page 1 SMT364 User Manual User Manual (QCF42); Version 3.0, 8/11/00; © Sundance Multiprocessor Technology Ltd. 1999...

  • Page 2: Revision History

    Version 1.0 Page 2 of 37 SMT364 User Manual Revision History Date Comments Engineer Version 31/07/03 First release...

  • Page 3: Table Of Contents

    Sundance Standards....................12 Communication Ports (ComPorts)................ 12 Sundance High-speed Bus - SHB................. 13 Communication links implemented on the SMT364..........13 For more details about ComPorts and SHB............14 ADC Performance....................15 SHB pinout....................... 17 FPGA Pinout......................

  • Page 4: Table Of Figures

    You can contact Sundance for additional information by sending email to support@sundance.com. Notes. SMT364 denotes in this document SMT364. The board in available in two options: AC or DC-coupled inputs (ADC). It is to be specified when placing an ordering.

  • Page 5: Precautions

    Page 5 of 37 SMT364 User Manual Precautions. In order to guarantee that the SMT364 functions correctly and to protect the module from damage, the following precautions should be taken: The SMT364 is a static sensitive product and should be handled accordingly.

  • Page 6: Outline Description

    Page 6 of 37 SMT364 User Manual Outline description. The SMT364 is a quad high-speed ADC module offering the following features: - Four 14-bit ADCs (AD6645-105) sampling at up to 105MHz, - Single width module, - Two Sundance High-speed Bus (SHB) connectors,...

  • Page 7: Block Diagram - Architecture

    Version 1.0 Page 7 of 37 SMT364 User Manual Block Diagram - Architecture. The following diagram shows the architecture of the SMT364. 3 Power J2 Bottom Primary TIM supply Connector LEDs 2x CommPorts/SDLs 1 & 4 ‘FPGA configured’ Trig On-board Oscillator...

  • Page 8: Architecture Description

    (DC coupling) or an RF transformer (AC coupling). The option must be defined when ordering a SMT364. ADCs can be coupled together. i.e. they have the same sampling clock or have separate clocks, one external and one coming from the on-board clock synthesizer.

  • Page 9: Virtex Fpga

    SMT364 User Manual Virtex FPGA. What the FPGA does. The SMT364 is populated with a Xilinx Virtex FPGA (XC2V1000-4FG456). This device controls major functions on the module, like CommPorts and SHB communications, data flows from the converters and clock management.

  • Page 10: Adcs

    Data and control lines of the converters are all connected to the FPGA. Clock management. The SMT364 has two identical on-board low-jitter clock synthesizers, one per pair of ADCs. Both have a Serial Port Interface. The FPGA is responsible for setting them to the correct values loaded into a control register.

  • Page 11: Communication Ports (Comports)

    7 latch stages. Communication Ports (ComPorts). The SMT364 provides 4 physical ComPorts: 0, 1, 3 and 4. The default bit stream provided implements ComPort 4 (Input at reset) to load control registers. A physical connection to a ComPort 0, 1 or 2 (Output at reset) is therefore necessary, to an SMT365 for instance.

  • Page 12: Ttl I/Os

    Version 1.0 Page 12 of 37 SMT364 User Manual TTL I/Os. Four TTL I/Os (J4 – see Figure 8 - Connector Location.) are connected directly to the FPGA. They support LVTTL signals. It is recommended to make sure the lines connected to these pins are LVTTL compatible in order not to damage the FPGA pads, as lines are not clamped.

  • Page 13: Sundance High-Speed Bus - Shb

    Figure 4 - SHB interface structure. Communication links implemented on the SMT364. The SMT364 provides 4 ComPort links. They are given the numbers 0, 1, 3 and 4. The default firmware provided with the board implements ComPort4 as a control...

  • Page 14: For More Details About Comports And Shb

    SMT364 User Manual register communication port, which means that every control register word has to be sent to ComPort4 on the SMT364 to be received. The board also connects two full SHB connectors (60 bits) to the FPGA. The FPGA implements two 16-bit (or one 32-bit) unidirectional (transmitter only) interfaces per SHB connector to send out samples coming from ADCs.

  • Page 15: Adc Performance

    Version 1.0 Page 15 of 37 SMT364 User Manual ADC Performance. Description Specification Analogue inputs 1.1 Volts peak-to-peak (AC coupling). Maximum voltage 2.2 Volts peak-to-peak (DC coupling – Gain 1). (Specify ADC coupling when placing an order) 50 Ω. Impedance - No anti-aliasing filter on the board.

  • Page 16: Figure 6 - Fft Adc Channel - On-Board Clock

    ADC inputs. They indeed have a large input bandwidth and therefore allow a high level of harmonics in. The SMT6600 package, provided with the SMT364 contains a documentation dealing with performance. It shows some captures and FFT graphs at different frequencies.

  • Page 17: Shb Pinout

    Version 1.0 Page 17 of 37 SMT364 User Manual SHB pinout. Signal Signal Signal CLK0 D20/ WEN1 D21/ REQ1 D22/ ACK1 D23/ CLK2 D44/ WEN3 D45 REQ23 D46/ ACQ3 D47/ CLK3 D8/ WEN0 D9/ REQ0 D10/ ACK0 D11/CLK1 D32/WEN2 D33/REQ2...

  • Page 18: Fpga Pinout

    An SHB interface can be 8,16 or 32-bit wide. The default FPGA firmware implements 2 16-bit interfaces. FPGA Pinout. ############################### NET "adcd_data<8>" LOC = "AA17" ; # Constraint File Virtex II for SMT364 NET "adcd_data<7>" LOC = "AB17" ; #Author:Philippe ROBERT NET "adcd_data<6>" LOC = "AA18" ; #$Date:23.07.2002 NET "adcd_data<5>"...
  • Page 19 Version 1.0 Page 19 of 37 SMT364 User Manual NET "adcb_rdy_gclk" LOC = "V11" ; NET "adca_data<1>" LOC = "AA6" ; NET "adcb_rdy" LOC = "AB7" ; NET "adca_data<0>" LOC = "Y7" ; NET "adcb_ovr" LOC = "V9" ; # CLOCK SYNTHESIZERS NET "adcb_data<13>"...
  • Page 20 Version 1.0 Page 20 of 37 SMT364 User Manual NET "pxi_trig3" LOC = "C21" ; NET "cp3_rdy" LOC = "V20" ; NET "pxi_trig2" LOC = "C22" ; NET "cp3_data<7>" LOC = "T20" ; NET "pxi_trig1" LOC = "E18" ; NET "cp3_data<6>" LOC = "T19" ;...
  • Page 21 Version 1.0 Page 21 of 37 SMT364 User Manual NET "cp0_data<1>" LOC = "W1" ; NET "shba<32>" LOC = "K1" ; NET "cp0_data<0>" LOC = "W2" ; NET "shba<31>" LOC = "K2" ; NET "cp0_ack" LOC = "R5" ; NET "shba<30>" LOC = "K3" ;...
  • Page 22 Version 1.0 Page 22 of 37 SMT364 User Manual # SHBB NET "shbb<30>" LOC = "K22" ; NET "shbb_clk1" LOC = "F13" ; NET "shbb<29>" LOC = "K21" ; NET "shbb_clk0" LOC = "B11" ; NET "shbb<28>" LOC = "K20" ;...

  • Page 23: At Power-Up And On Reset

    If J1 is not fitted, nothing happens. This condition is useful when needing to configure the FPGA via JTAG. Also at power-up and on a carrier board reset signal, the SMT364 expects receiving a dummy ComPort word (any value) and sends one back containing the Firmware version number.

  • Page 24: Connector Position

    Version 1.0 Page 24 of 37 SMT364 User Manual Connector position. Figure 8 - Connector Location.

  • Page 25: Operating Conditions

    The module must be fixed to a TIM40-compliant carrier board. The SMT364 module is in a range of modules that must be supplied with a 3.3v power source. In addition to the 5v supply specified in the TIM specification, these new generation modules require an additional 3.3v supply to be presented on the two...

  • Page 26: Register Settings

    Version 1.0 Page 26 of 37 SMT364 User Manual Register settings. Register 0x0 – Clock management.
  • Page 27 Version 1.0 Page 27 of 37 SMT364 User Manual Bit number Description Bit 31 Bit 30 Bit 29 Bit 28 Bit 27 Clock Selection Channel D (‘0’=Internal; ‘1’=External) Bit 26 Clock Selection Channel C (‘0’=Internal; ‘1’=External) Bit 25 Clock Selection Channel B (‘0’=Internal; ‘1’=External) Bit 24 Clock Selection Channel A (‘0’=Internal;...

  • Page 28: Figure 11 - Clock Routing

    Version 1.0 Page 28 of 37 SMT364 User Manual (“110”) or 12 (“111”). See ICS8430-01 datasheet for more information performance, jitter, etc. The following diagram shows how clock signals can be routed on the PCB. AC or DC AC or DC...

  • Page 29: Register 0X1 -Channel Data Routing - Triggers

    Version 1.0 Page 29 of 37 SMT364 User Manual Register 0x1 –Channel data routing – Triggers. Bit number Description Bit 31 Bit 30 Bit 29 Bit 28 Bit 27 Bit 26 Bit 25 Bit 24 Bit 23 Bit 22 Bit 21...
  • Page 30 Version 1.0 Page 30 of 37 SMT364 User Manual Data routes can also be configured vie Register 0x1. The following diagram shows all the possibilities (Data go through a pipeline and can be added with each other): Channel A Data Flow A...

  • Page 31: Register 0X2 -Adcc And Adcd Selection Modes And Decimation Factors

    Version 1.0 Page 31 of 37 SMT364 User Manual Register 0x2 –ADCC and ADCD Selection Modes and Decimation factors. Bit number Description Bit 31 Bit 30 Bit 29 Bit 28 Bit 24-27 Bit 23 Bit 22 Bit 21 Channel D Mode Selection – Bit 1.
  • Page 32 Version 1.0 Page 32 of 37 SMT364 User Manual Channel selection: “00”=Channel disabled, “01”=16-bit counter on clock ADCA, “10”=Channel A two’s complement encoding, i.e. samples go straight through as ADCs output samples in two’s complement 14-bit format. 14-bit samples coming from the ADC are extended to 16-bit on SHBA – Bit13 is copied onto Bits14 and 15.

  • Page 33: Register 0X3 -Adca And Adcb Selection Modes And Decimation Factors

    Version 1.0 Page 33 of 37 SMT364 User Manual Register 0x3 –ADCA and ADCB Selection Modes and Decimation factors. Bit number Description Bit 31 Bit 30 Bit 29 Bit 28 Bit 24-27 Bit 23 Bit 22 Bit 21 Channel B Mode Selection – Bit 1.
  • Page 34 Version 1.0 Page 34 of 37 SMT364 User Manual Channel selection: “00”=Channel disabled, “01”=16-bit counter on clock ADCA, “10”=Channel A two’s complement encoding, i.e. samples go straight through as ADCs output samples in two’s complement 14-bit format. 14-bit samples coming from the ADC are extended to 16-bit on SHBA – Bit13 is copied onto Bits14 and 15.

  • Page 35: Register 0Xd - Fpga Global Reset

    It might stick the other end into an unknown state. After a Reset command, the SMT364 expects receiving a dummy ComPort word (any value) and sends one back containing the Firmware version number. It is a way of checking that the firmware is latest and that the board is responding and ready to work.

  • Page 36: Register 0Xf - Serial Interfaces Load

    Version 1.0 Page 36 of 37 SMT364 User Manual Register 0xF – Serial Interfaces load. Description number Bit 31 Bit 30 Bit 29 Bit 28 Bit 27-0 Not Used. The clock synthesizers have all a S erial P ort I nterface. By sending this control word,...

  • Page 37: Smt364 Package

    Page 37 of 37 SMT364 User Manual SMT364 package. The SMT364 comes with an install package (SMT6600) that contain examples and a C header file. When ordered with either an SMT365 or SMT365E or SMT374, it comes with a Pegasus application and a 3L application.

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