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Lime Microsystems LMS7002MR3 Programming And Calibration Manual

Multi-band, multi-standard mimo rf transceiver ic
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Lime Microsystems Limited
Surrey Tech Centre
Occam Road
The Surrey Research Park
Guildford, Surrey GU2 7YG
United Kingdom
Tel:
+44 (0) 1483 685 063
Fax:
+44 (0) 1428 656 662
e-mail:
enquiries@limemicro.com
LMS7002M – Multi-Band, Multi-Standard MIMO
- Programming and Calibration Guide -
Chip version:
Mask revision:
Document version:
Document revision:
RF Transceiver IC
LMS7002M
01
3.01
4

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  • Page 1 Lime Microsystems Limited Surrey Tech Centre Occam Road The Surrey Research Park Guildford, Surrey GU2 7YG United Kingdom Tel: +44 (0) 1483 685 063 Fax: +44 (0) 1428 656 662 e-mail: enquiries@limemicro.com LMS7002M – Multi-Band, Multi-Standard MIMO RF Transceiver IC...

  • Page 3: Table Of Contents

    Contents 1. Serial Port Interface ......................3 Description ......................... 3 2. LMS7002Mr3 Memory Map Description................5 LMS7002Mr3 Memory Map ..................5 General Control, LimeLight and IO Cell Configuration Memory ......8 NCO Configuration Memory ................... 17 TxTSP(A/B) Configuration Memory ............... 20 RxTSP(A/B) Configuration Memory ...............
  • Page 4 A2.16 TxTSP(A/B) BIST Control Diagram ..............95 A2.17 RxTSP(A/B) BIST Control Diagram ..............95 A2.18 LimeLight Control Diagram ................96 A2.19 DC offset correction Control Diagram ..............97 A2.20 Measurement block Control Diagram ..............98 5. Calibration algorithms ...................... 99 A3.1 VCO coarse tuning ....................
  • Page 5 Revision History Version 31r00 Released: 23 Jan, 2017 Initial version. Build based on LMS7002M Programming and Calibration Guide v2.24. New register HBD_DLY[2:0] added (address 0x404[15:13]). Table 1 updated. Chapters 2.24 and 2.25 added. New register CMIX_GAIN[2] added (address 0x40C[12]). Description of register CMIX_GAIN[1:0] changed (address 0x40C[15:14]). New register CMIX_GAIN[2] added (address 0x208[12]).
  • Page 6 LimeLight Control Diagram updated. New register MCLK2_INV added (address 0x002B[9]). New register MCLK1_INV added (address 0x002B[8]). Description of registers at addresses 0x002C updated. New register FCLK2_DLY[1:0] added (address 0x002A[15:14]). New register FCLK1_DLY[1:0] added (address 0x002A[13:12]). Section 1.1 updated (few typo errors fixed). Figure 4 updated –...

  • Page 7: Serial Port Interface

    Serial Port Interface 1.1 Description The functionality of LMS7002Mr3 transceiver is fully controlled by a set of internal registers which can be accessed through a serial SPI port interface. Both write and read operations are supported. The serial SPI port can be configured to run in 3 or 4 wire mode with the following pins used: ...
  • Page 8 bit register address when concatenated ((Maddress << 6) | Reg). Use global address values for particular register from the tables provided in Section 2. Write/read cycle waveforms are shown in Figure 1, Figure 2 and Figure 3. Note that write operation is the same for both 3-wire and 4-wire modes. Although not shown in the figures, multiple byte write/read is possible by repeating instruction/data sequence while keeping SEN low.

  • Page 9: Lms7002Mr3 Memory Map Description

     TX  RX LMS7002Mr3 chip is MIMO, hence it have two channels called A and B. So, some analogue/digital modules appears in MIMO channel A as well as B (from TRX, TX and RX blocks). The rest of moduleMr3s (from Other and Top logical block types) are controlled only from one memory block.
  • Page 10 Using the MAC register simplifies programming for MIMO. As an example, the addresses of registers controlling TBBA and TBBB are the same, but the individual A or B channels are identified using the MAC[1:0] register. Let us consider the write operation to the G_TIA_RFE_A[1:0] register. This register controls the RFE module within MIMO channel A.
  • Page 11 Table 1: LMS7002Mr3 memory map Logical Address Logical Block Size, Block Comments Resserved Maddress Name regs (R/W) Type [3:0] [4:0] [5:0] 0000 00000 00xxxx Address space starts at 0x0000. Addressing do not depend from MAC[1:0]. Lime Light 0000 00000 1xxxxx Address space starts at 0x0020.

  • Page 12: General Control, Limelight Tm And Io Cell Configuration Memory

    2.2 General Control, LimeLight and IO Cell Configuration Memory The block diagram of each IO cell is shown in Figure 21. It is possible to control the drive strength and pull-up resistor value of each IO cell. The tables in this chapter describe the control registers of the IO cells and LimeLightTM Ports 1 and 2.
  • Page 13 Table 2 LimeLight and PAD configuration memory Address (15 bits) Bits Description 0x0020 LRST_TX_B: Resets all the logic registers to the default state for Tx MIMO channel 0 – Reset active 1 – Reset inactive (default) MRST_TX_B: Resets all the configuration memory to the default state for Tx MIMO channel B.
  • Page 14 Address (15 bits) Bits Description Reserved 0x0021 15 – 12 TX_CLK_PE: Pull up control of TX_CLK pad. 0 – Pull up disengaged 1 – Pull up engaged (default) RX_CLK_PE: Pull up control of RX_CLK pad. 0 – Pull up disengaged 1 –...
  • Page 15 Address (15 bits) Bits Description 0x0022 LML2_TRXIQPULSE: TRXIQPULSE mode selection for LML Port 2. 0 – TRXIQPULSE mode off (default) 1 – TRXIQPULSE mode on LML2_SISODDR: SISODDR mode selection for LML Port 2. 0 – SISODDR mode off (default) 1 – SISODDR mode on LML1_TRXIQPULSE: TRXIQPULSE mode selection for LML Port 1.
  • Page 16 Address (15 bits) Bits Description 0x0023 DIQDIRCTR2: DIQ2 direction control mode. 0 – Automatic (default) 1 – Manual, controllable from DIQDIR2 DIQDIR2: DIQ2 direction. 0 – Output 1 – Input (default) DIQDIRCTR1: DIQ1 direction control mode. 0 – Automatic (default) 1 –...
  • Page 17 Address (15 bits) Bits Description 0x0024 15 – 14 LML1_S3S[1:0]: Sample source in position 3, when direction of Port 1 is RF2BB. 11 – Sample in frame position 0 is BQ (default) 10 – Sample in frame position 0 is BI 01 –...
  • Page 18 Address (15 bits) Bits Description 0x0027 15 – 14 LML2_S3S[1:0]: Sample source in position 3, when direction of Port 2 is RF2BB. 11 – Sample in frame position 0 is BQ (default) 10 – Sample in frame position 0 is BI 01 –...
  • Page 19 Address (15 bits) Bits Description 0x002A 15 – 14 FCLK2_DLY[1:0]: FCLK2 clock internal delay. 11 – 3x delay 10 – 2x delay 01 – 1x delay 00 – No delay (default) 13 – 12 FCLK1_DLY[1:0]: FCLK2 clock internal delay. 11 – 3x delay 10 –...
  • Page 20 Address (15 bits) Bits Description 0x002B FCLK2_INV: FCLK2 clock inversion. 1 – Inverted 0 – Not inverted (default) FCLK1_INV: FCLK1 clock inversion. 1 – Inverted 0 – Not inverted (default) 13 – 12 MCLK2_DLY[1:0]: MCLK2 clock internal delay. 11 – 3x delay 10 –...

  • Page 21: Nco Configuration Memory

    2.3 NCO Configuration Memory The NCO configuration memory control is listed in this chapter. There are 4 NCOs – two for each transmit and receive MIMO channel. The carrier frequency f generated by NCO could be set using the following formula: ...
  • Page 22 Address (15 bits) Bits Description TX(A/B): 0x0246 15 – 0 FCW2[31:16]: NCO frequency control word register 2, when MODE = 0. MSB part. RX(A/B): 0x0446 PHO2[15:0]: NCO Phase offset register 2, when MODE = 1. Default: 00000000 00000000 TX(A/B): 0x0247 15 –...
  • Page 23 Address (15 bits) Bits Description TX(A/B): 0x0257 15 – 0 FCW10[15:0]: NCO frequency control word register 10, when MODE = 0. LSB part. RX(A/B): 0x0457 Reserved, when MODE = 1. Default: 00000000 00000000 TX(A/B): 0x0258 15 – 0 FCW11[31:16]: NCO frequency control word register 11, when MODE = 0. MSB RX(A/B): 0x0458 part.

  • Page 24: Txtsp(A/B) Configuration Memory

    2.4 TxTSP(A/B) Configuration Memory The block diagrams of TxTSPA and TxTSPB modules are exactly the same. The control structure is shown in Figure 22. The tables in this chapter describe the control registers of TxTSPA and TxTSPB modules. There is one BIST logic per TxTSPA and TxTSPB. The BIST control structure is shown in Figure 25.
  • Page 25 Address (15 bits) Bits Description 0x0204 15 – 8 DCCORRI[7:0]: DC corrector value, channel I. Integer, 2's complement. Possible values are -128 to 127, default is 0 7 – 0 DCCORRQ[7:0]: DC corrector value, channel Q. Integer, 2's complement. Possible values are -128 to 127, default is 0 Default: 00000000 00000000 0x0205 15 –...
  • Page 26 Address (15 bits) Bits Description 0x0209 15 – 1 BSIGI[14:0]: TxTSP BIST signature, channel I, LSB. BSTATE: TxTSP BIST state indicator 0 – BIST is not running 1 – BIST in progress Read only 0x020A 15 – 8 BSIGQ[7:0]: TxTSP BIST signature, channel Q, LSB. 7 –...

  • Page 27: Rxtsp(A/B) Configuration Memory

    2.5 RxTSP(A/B) Configuration Memory The block diagrams of the RxTSPA and RxTSPB modules are exactly the same. The control structure is shown in Figure 23. The tables in this chapter describe the control registers of RxTSPA and RxTSPB modules. There is one BIST logic per RxTSPA and RxTSPB. The BIST control structure is shown in Figure 26.
  • Page 28 Address (15 bits) Bits Description Reserved 0x0403 HBD_OVR+1 14 – 12 HBD_OVR[2:0]: HBD decimation ratio. Decimation ratio is 2 000 – Decimation ratio is 2 (default) 001 – Decimation ratio is 4 010 – Decimation ratio is 8 011 – Decimation ratio is 16 100 –...
  • Page 29 Address (15 bits) Bits Description 0x040C 15 – 14 CMIX_GAIN[1:0]: Gain of CMIX output, least significant part. CMIX_GAIN[2] CMIX_GAIN[1:0] CMIX output gain ============================================ 0 (default) 00 (default) +6dB 10, 11 –6dB CMIX_SC: Spectrum control of CMIX. 1 – Downconvert 0 – Upconvert (default) CMIX_GAIN[2]: Gain of CMIX output, most significant part.

  • Page 30: Rx/Tx Gfir1/Gfir2 Coefficient Memory

    2.6 RX/TX GFIR1/GFIR2 Coefficient Memory The general purpose digital FIR filter (GFIR1 and GFIR2) coefficients are stored in the following tables. Table 6 Memory space used to store TxGFIR1/RxGFIR1 coefficients Address (15 bits) Bits Description Tx: 0x0280 – 0x0287 8 x 16 Tx(Rx)1CMB0[7:0][15:0]: Coefficients memory bank 0 for TxGFIR1/RxGFIR1.

  • Page 31: Rx/Tx Gfir3 Coefficient Memory

    2.7 RX/TX GFIR3 Coefficient Memory The general purpose digital FIR filter (GFIR3) coefficients are stored in the following table. Table 8 Memory space used to store TxGFIR3 coefficients Address (15 bits) Bits Description Tx: 0x0300 – 0x0307 8 x 16 Tx(Rx)3CMB0a[7:0][15:0]: Coefficients memory bank 0a for TxGFIR2/RxGFIR3.

  • Page 32: Rfe(1, 2) Configuration Memory

    2.8 RFE(1, 2) Configuration Memory The block diagrams of the RFE1 and RFE2 modules are shown in Figure 5 and Figure 6 respectively. The tables in this chapter describes control registers of RFE1 and RFE2 modules. Table 9: RFE(1, 2) configuration memory Address (15 bits) Bits Description...
  • Page 33 Address (15 bits) Bits Description Reserved 0x010D 15 – 9 8 – 7 SEL_PATH_RFE_(1, 2): Selects the active path of the RXFE 0 – No path active 1 – LNAH path active (default) 2 – LNAL path active 3 – LNAW path active EN_DCOFF_RXFE_RFE_(1, 2): Enables the DCOFFSET block for the RXFE 0 –...
  • Page 34 Address (15 bits) Bits Description Reserved 0x0110 14 – 10 ICT_LNACMO_RFE_(1, 2)[4:0]: Controls the current generating LNA output common mode voltage. Default: 2 9 – 5 ICT_LNA_RFE_(1, 2)[4:0]: Controls the current of the LNA core. Default: 12 Block current = Nominal current * (ICT / 12) 4 –...
  • Page 35 Address (15 bits) Bits Description Reserved 0x0113 15 – 10 9 – 6 G_LNA_RFE_(1, 2)[3:0]: Controls the gain of the LNA 15 – Gmax (default) 14 – Gmax-1 13 – Gmax-2 12 – Gmax-3 11 – Gmax-4 10 – Gmax-5 9 –...

  • Page 36: Rbb(1, 2) Configuration Memory

    2.9 RBB(1, 2) Configuration Memory The block diagrams of RBB1 and RBB2 modules are shown in Figure 7 Figure 8 respectively. The tables in this chapter describe the control registers of RBB1 and RBB2 modules. Table 10: RBB(1, 2) configuration memory Address (15 bits) Bits Description...
  • Page 37 Address (15 bits) Bits Description Reserved 0x0117 15 – 14 13 – 11 RCC_CTL_LPFL_RBB_(1, 2)[2:0]: Controls the stability passive compensation of the LPFL_RBB operational amplifier. 0 – when rxMode is 1.4MHz, 1 – when 3MHz 2 – when 5MHz 3 – when 10MHz 4 –...
  • Page 38 Address (15 bits) Bits Description Reserved 0x011A 15 – 14 13 – 9 RCC_CTL_PGA_RBB_(1, 2)[4:0]: Controls the stability passive compensation of the PGA_RBB operational amplifier. Its value is equal to: (430f*(0.65**(G_PGA_RBB/10))-110.35f)/20.4516f + 16 when ICT_PGA is 12. An offline/off chip lookup table can be generated and stored. Default: 23 Reserved 7 –...

  • Page 39: Trf(1, 2) Configuration Memory

    2.10 TRF(1, 2) Configuration Memory The block diagrams of TRF1 and TRF2 modules are shown in Figure 9 and Figure 10 respectively. The tables in this chapter describe control registers of TRF1 and TRF2 modules. Table 11: TRF(1, 2) configuration memory Address (15 bits) Bits Description...
  • Page 40 Address (15 bits) Bits Description 0x0102 GCAS_GNDREF_TXPAD_TRF_(1, 2): Controls if the TXPAD cascode transistor gate bias is referred to VDD or GND. 0 – VDD referred (default) 1 – GNDS referred 14 – 10 ICT_LIN_TXPAD_TRF_(1, 2)[4:0]: Control the bias current of the linearization section of the TXPAD.

  • Page 41: Tbb(1, 2) Configuration Memory

    2.11 TBB(1, 2) Configuration Memory The block diagrams of TBB1 and TBB2 modules are shown in Figure 11 and Figure 12 respectively. The tables in this chapter describe the control registers of TBB1 and TBB2 modules. Table 12: TBB(1, 2) configuration memory Address (15 bits) Bits Description...
  • Page 42 Address (15 bits) Bits Description Reserved 0x0106 14 – 10 ICT_LPFS5_F_TBB_(1, 2)[4:0]: This controls the operational amplifier's output stage bias current of the low band real pole filter of the transmitter's base band. Default: 9 – 5 ICT_LPFS5_PT_TBB_(1, 2)[4:0]: This controls the operational amplifier's input stage bias current of the low band real pole filter of the transmitter's base band.

  • Page 43: Trx Gain Configuration Memory

    Address (15 bits) Bits Description 0x010A 15 – 14 TSTIN_TBB_(1, 2)[1:0]: This control selects where the input test signal (vinp/n_aux_bbq/i) is routed to as well as disabling the route. 0 – Disabled. Test signal is not routed any where. (default) 1 –...
  • Page 44 Table 13: TRX gain configuration memory Address (15 bits) Bits Description 0x0125 15 – 10 CG_IAMP_TBB_(1, 2)[5:0]: This controls the front-end gain of the TBB. For a given gain value, this control value varies with the set TX mode. After resistance calibration, the following table gives the nominal values for each frequency setting.

  • Page 45: Afe Configuration Memory

    2.13 AFE Configuration Memory The block diagram of the AFE module is shown in Figure 13. The tables in this chapter describe the control registers of the AFE module. Table 14: AFE configuration memory Address (15 bits) Bits Description 0x0082 15 –...

  • Page 46: Bias Configuration Memory

    2.14 BIAS Configuration Memory The block diagram of the BIAS module is shown in Figure 14. The tables in this chapter describe the control registers of the BIAS module. Table 15: BIAS configuration memory Address (15 bits) Bits Description 0x0083 15 –...

  • Page 47: Sxr, Sxt Configuration Memory

    2.15 SXR, SXT Configuration Memory The block diagrams of the SXR and SXT modules are shown in Figure 15 and Figure 16 respectively. The tables in this chapter describe the control registers of SXR and SXT modules. Table 16: SXT (SXR) configuration memory Address (15 bits) Bits Description...
  • Page 48 Address (15 bits) Bits Description FRAC_SDM_(SXR, SXT)[15:0]: Fractional control of the division ratio LSB. Default: 0x011D 15 – 0 1024 =2^20*[Fvco/(Fref * 2^ EN_DIV2_DIVPROG_(SXR, SXT)) – int(Fvco/(Fref * 2^ EN_DIV2_DIVPROG_(SXR, SXT)))] Default: 00000100 00000000 0x011E 15 - 14 Reserved 13 – 4 INT_SDM_(SXR, SXT)[9:0]: Controls Integer section of the division ratio INT_SDM_(SXR, SXT)
  • Page 49 Address (15 bits) Bits Description VDIV_VCO_(SXR, SXT)[7:0]: Controls VCO LDO output voltage. Default: 185 0x0120 15 – 8 Vout(VCO_LDO)=VDD18_VCO* [ (29.1/(29.1 + 233/(VDIV_VCO_SX+2)))] 185 --> Vout(VCO_LDO)=1.55V (VDD18_VCO=1.72) 7 – 0 ICT_VCO_(SXR, SXT)[7:0]: Scales the VCO bias current from 0 to 2.5xInom Default: 128 Default: 10111001 10000000 0x0121...
  • Page 50 Address (15 bits) Bits Description RESRV_(SXR, SXT)[4:0]: Reserved. Default: 0 0x0124 15 – 11 (For SXT only RESRV_SXR[0] connected to the output!) 10 – 5 Reserved EN_DIR_(SXR, SXT): Enables direct control of PDs and ENs for SXR/SXT module. 0 – direct control disabled (default) 1 –...

  • Page 51: Cgen Configuration Memory

    2.16 CGEN Configuration Memory The block diagram of the CGEN module is shown in Figure 17. The tables in this chapter describes the control registers of the CGEN module. Table 17: CGEN configuration memory Address (15 bits) Bits Description 0x0086 SPDUP_VCO_CGEN: Bypasses the noise filter resistor for fast settling time.
  • Page 52 Address (15 bits) Bits Description 0x0089 REV_SDMCLK_CGEN: Reverses the SDM clock 0 – default (default) 1 – reversed (after INV) SEL_SDMCLK_CGEN: Selects between the feedback divider output and Fref for 0 – CLK CLK_DIV (default) 1 – CLK CLK_REF SX_DITHER_EN_CGEN: Enabled dithering in SDM 0 –...
  • Page 53 Address (15 bits) Bits Description COARSE_STEPDONE_CGEN: Read only 0x008C COARSEPLL_COMPO_CGEN: Read only VCO_CMPHO_CGEN: Read only VCO_CMPLO_CGEN: Read only 11 – 8 CP2_CGEN[3:0]: Controls the value of CP2 (cap from CP output to GND) in the PLL filter. Default: 6 cp2=CP2_PLL_SX*6*63.2fF 7 –...

  • Page 54: Xbuf Configuration Memory

    2.17 XBUF Configuration Memory The block diagram of the XBUF module is shown in Figure 18. The tables in this chapter describe the control registers of the XBUF module. Table 18: XBUF configuration memory Address (15 bits) Bits Description 0x0085 15 –...

  • Page 55: Ldo Configuration Memory

    2.18 LDO Configuration Memory The block diagram of the LDO module is shown in 9. The tables in this chapter describe the control registers of the LDO modules. Table 19: LDO configuration memory Address (15 bits) Bits Description 0x0092 EN_LDO_DIG: Enables the LDO 0 –...
  • Page 56 Address (15 bits) Bits Description 0x0093 EN_LOADIMP_LDO_TLOB: Enables the load dependent bias to optimize the load regulation 0 – Constant bias (default) 1 – Load dependent bias EN_LOADIMP_LDO_TPAD: Enables the load dependent bias to optimize the load regulation 0 – Constant bias (default) 1 –...
  • Page 57 Address (15 bits) Bits Description 0x0094 EN_LOADIMP_LDO_CPSXT: Enables the load dependent bias to optimize the load regulation 0 – Constant bias (default) 1 – Load dependent bias EN_LOADIMP_LDO_DIG: Enables the load dependent bias to optimize the load regulation 0 – Constant bias (default) 1 –...
  • Page 58 Address (15 bits) Bits Description 0x0095 BYP_LDO_TBB: Bypass signal for the LDO 0 – Does not bypass. Normal LDO operation (default) 1 – Bypasses LDO. Connects Vinput to Voutput BYP_LDO_TIA12: Bypass signal for the LDO 0 – Does not bypass. Normal LDO operation (default) 1 –...
  • Page 59 Address (15 bits) Bits Description 0x0096 BYP_LDO_AFE: Bypass signal for the LDO 0 – Does not bypass. Normal LDO operation (default) 1 – Bypasses LDO. Connects Vinput to Voutput BYP_LDO_CPGN: Bypass signal for the LDO 0 – Does not bypass. Normal LDO operation (default) 1 –...
  • Page 60 Address (15 bits) Bits Description 0x0097 SPDUP_LDO_DIVSXR: Short the noise filter resistor to speed up the settling time 0 – noise filter resistor in place (default) 1 – Noise filter resistor bypassed should be connected to a 1~5uS at the power up SPDUP_LDO_DIVSXT: Short the noise filter resistor to speed up the settling time 0 –...
  • Page 61 Address (15 bits) Bits Description Reserved 0x0098 15 – 9 SPDUP_LDO_AFE: Short the noise filter resistor to speed up the settling time 0 – noise filter resistor in place (default) 1 – Noise filter resistor bypassed should be connected to a 1~5uS at the power up SPDUP_LDO_CPGN: Short the noise filter resistor to speed up the settling time 0 –...
  • Page 62 Address (15 bits) Bits Description 0x009D 15 – 8 RDIV_RXBUF[7:0]:Controls the output voltage of the LDO by setting the resistive voltage divider ratio. Default: 101 Vout=860mV+3.92mV *RDIV 7 – 0 RDIV_TBB[7:0]:Controls the output voltage of the LDO by setting the resistive voltage divider ratio.
  • Page 63 Address (15 bits) Bits Description 0x00A6 15 – 13 ISINK_SPIBUFF[2:0]: Controls the SPIBUF LDO output resistive load. 0 – Off (default); 1 – 10kΩ; 2 – 2.5kΩ; 3 – 2kΩ; 4 – 625Ω; 5 – 588Ω 6 – 500Ω 7 – 476Ω SPDUP_LDO_SPIBUF: Short the noise filter resistor to speed up the settling time 0 –...

  • Page 64: En_Dir Configuration Memory

    2.19 EN_DIR Configuration Memory The tables in this chapters describe the control registers of the EN_DIR module. Each EN_DIR bit enables capability of direct control of PD (powerdown) and EN (enable) outputs. Table 20: EN_DIR configuration memory Address (15 bits) Bits Description 0x0081...

  • Page 65: Sxr, Sxt And Cgen Bist Configuration Memory

    2.20 SXR, SXT and CGEN BIST Configuration Memory The block diagram of the BIST module for SXR, SXT and CGEN is shown in Figure 24. The table in this chapter describes control registers of BIST module. There is one test vector generator which supplies the test vectors for CGEN, SXT and SXR modules.

  • Page 66: Cds Configuration Memory

    2.21 CDS Configuration Memory The block diagram of the Clock Distribution System (CDS) module is shown in Figure 20. The tables in this chapter describe the control registers of CDS module. Table 22: CDS configuration memory Address (15 bits) Bits Description 0x00AD 15 –...
  • Page 67 Address (15 bits) Bits Description 0x00AE 15 – 14 CDS_TXBTSP[1:0]: TX TSP B clock delay. 00 – delay by 400ps (default) 01 – delay by 500ps 10 – delay by 600ps 11 – delay by 700ps 13 – 12 CDS_TXATSP[1:0] : TX TSP A clock delay. 00 –...

  • Page 68: Mspi Configuration Memory

    2.22 mSPI Configuration Memory More information about embedded microcontroller may found in the microcontroller datasheet. Table 23: mSPI configuration memory Address (15 bits) Bits Description 0x0000 15 – 8 Reserved 7 – 0 P0[7:0]: The data at MCU port P0 input can be changed by writing data into this Controls port register...

  • Page 69: Dc Calibration Configuration Memory

    2.23 DC Calibration Configuration Memory The block diagrams of the DC calibration modules are shown in Figure 28. The tables in this chapter describes control registers of DC calibration modules. Table 24: DC calibration configuration memory Address (15 bits) Bits Description 0x05C0 DCMODE: Control for the DC offset calibration mode.
  • Page 70 Address (15 bits) Bits Description DCCAL_CALSTATUS_RXBQ. RXBQ DC calibration status (Read only): 0x05C1 0 – Calibration is not running 1 – Calibration is running DCCAL_CALSTATUS_RXBI. RXBI DC calibration status (Read only): 0 – Calibration is not running 1 – Calibration is running DCCAL_CALSTATUS_RXAQ.
  • Page 71 Address (15 bits) Bits Description 0x05C2 DCCAL_CMPCFG_RXBQ. RXBQ comparator configuration 0 – Comparator output not inverted (default) 1 – Comparator output inverted DCCAL_CMPCFG_RXBI. RXBI comparator configuration 0 – Comparator output not inverted (default) 1 – Comparator output inverted DCCAL_CMPCFG_RXAQ. RXAQ comparator configuration 0 –...
  • Page 72 Address (15 bits) Bits Description 0x05C4 DCWR_TXAQ. Used to enable manual write operation of TXAQ DAC values. Value must be first stored in DC_TXAQ register prior to toggling this flag: 0 to 1 – writes the value to TXAQ DAC from DC_TXAQ register Default: 0 DCRD_TXAQ.
  • Page 73 Address (15 bits) Bits Description 0x05C8 DCWR_RXAQ. Used to enable manual write operation of RXAQ DAC values. Value must be first stored in DC_RXAQ register prior to toggling this flag: 0 to 1 –writes the value to RXAQ DAC from DC_RXAQ register Default: 0 DCRD_RXAQ.

  • Page 74: Rssi, Pdet And Temp Measurement Configuration Memory

    2.24 RSSI, PDET and TEMP measurement Configuration Memory The block diagrams of the analogue RSSI, power detector and temperature measurement modules are shown in Figure 29. The tables in this chapter describes control registers of RSSI, power detector and temperature measurement modules. Table 25 RSSI configuration memory Address (15 bits) Bits...
  • Page 75 Address (15 bits) Bits Description Reserved 0x0602 15 – 14 13 – 9 MEASR_BIAS[4:0]: Controls the reference bias current of the test ADC. Used for measurement ADC calibration routine: 0 – min bias value (lowest threshold) … 16 – middle bias value (default) …...

  • Page 76: Analog Rssi Calibration Configuration Memory

    Address (15 bits) Bits Description MEASR_TREF_VAL[7:0]: Stores the temperature reference value. (Read only) 0x0606 15 – 8 MEASR_TREF_VAL[7:0] – magnitude 7 – 0 MEASR_TPTAT_VAL[7:0]: Stores the voltage proportional to absolute temperature value. (Read only) MEASR_TPTAT_VAL[7:0] – magnitude Default: XXXXXXXX XXXXXXXX 2.25 Analog RSSI Calibration Configuration Memory The block diagram of the analog RSSI calibration module is as shown in Figure 5 and Figure 6.

  • Page 77: Spi Procedures

    SPI Procedures A1.1 SPI READ/WRITE Pseudo Code //---------------------------------------------------------------------------- // Write command, SPI module address, register address // Read data //---------------------------------------------------------------------------- void SPI_Read(unsigned int COMMAND) unsigned int DATA; //We will read data there //Write Command and Address (MSB First) //First 1 bit (MSB) = Command //Next 15 (LSBs) bits = Register Address for(int i=15;...
  • Page 78 //---------------------------------------------------------------------------- // Write data to the chip: // First byte: Command, SPI module address, register address // Second byte: Data //---------------------------------------------------------------------------- void SPI_Write(unsigned int COMMAND, unsigned int DATA) //Write Command, Address for(int i=15; i>=0; i--) if(i’th bit in COMMAND is ‘1’) Set Data Output line to ‘1’;...

  • Page 79: Control Block Diagrams

    Control Block Diagrams...

  • Page 80: A2.1 Rfe Control Diagrams

    A2.1 RFE Control Diagrams CDC_I_RFE_1 (0x010C[15:12]) CDC_Q_RFE_1 (0x010C[11:8]) LMS7002M SEL_PATH_RFE_1 (0x010D[7:8]) Signal input/output PD_QGEN_RFE_1 (0x010C[3]) Analog signal lines RXFE_TOP 1 PD_RLOOPB_1_RFE_1 (0x010C[6]) RESET_N (XXXX) IO control name (register adress) G_RXLOOPB_RFE_1 (0x0113[5:2]) EN_INSHSW_LB1_RFE_1 (0x010D[4]) LO I/Q generator From: LOCH_IR(P/N) (SX RX) SEL_PATH_RFE_1 (0x010D[7:8]) PD_MXLOBUF_RFE_1...
  • Page 81 CDC_I_RFE_2 (0x010C[15:12]) CDC_Q_RFE_2 (0x010C[11:8]) SEL_PATH_RFE_2 (0x010D[7:8]) LMS7002M Signal input/output PD_QGEN_RFE_2 (0x010C[3]) Analog signal lines RXFE_TOP 2 PD_RLOOPB_1_RFE_2 (0x010C[6]) RESET_N (XXXX) IO control name (register adress) G_RXLOOPB_RFE_2 (0x0113[5:2]) EN_INSHSW_LB1_RFE_2 (0x010D[4]) LO I/Q generator From: RLODIVO_OUT1 (RX RF 1) SEL_PATH_RFE_2 (0x010D[7:8]) PD_MXLOBUF_RFE_2 (0x010C[4]) RX RF loopback...

  • Page 82: A2.2 Rbb Control Diagrams

    A2.2 RBB Control Diagrams LMS7002M Channel I RCC_CTL_LPFH_RBB_1 (0x0116[10:8]) RCC_CTL_PGA_RBB_1 (0x011A[13:9]) R_CTL_LPF_RBB_1 (0x0116[15:11]) RBB_TOP 1 PD_PGA_RBB_1 (0x0115[1]) PD_LPFH_RBB_1 (0x0115[3]) OSW_PGA_RBB_1 (0x0119[15]) EN_LB_LPFH_RBB_1 (0x0115[15]) To: rbbi(p/n)_pad_1 (PAD) C_CTL_PGA_RBB_1 (0x011A[7:0]) C_CTL_LPFH_RBB_1 (0x0116[7:0]) From: pdeto(p/n)_1 (ADC, TX RF) From: adcin_i(p/n)_1 (PAD) loop TX loop pdet LPF High From: rfeoi(p/n)_1 (RX RF)
  • Page 83 LMS7002M Channel I RCC_CTL_LPFH_RBB_2 (0x0116[10:8]) RCC_CTL_PGA_RBB_2 (0x011A[13:9]) R_CTL_LPF_RBB_2 (0x0116[15:11]) RBB_TOP 2 PD_PGA_RBB_2 (0x0115[1]) PD_LPFH_RBB_2 (0x0115[3]) OSW_PGA_RBB_2 (0x0119[15]) EN_LB_LPFH_RBB_2 (0x0115[15]) To: rbbi(p/n)_pad_2 (PAD) C_CTL_LPFH_RBB_2 (0x0116[7:0]) C_CTL_PGA_RBB_2 (0x011A[7:0]) From: pdeto(p/n)_2 (ADC, TX RF) From: adcin_i(p/n)_2 (PAD) loop TX loop pdet LPF High From: rfeoi(p/n)_2 (RX RF) LPF H From: txloop_1(p/n)_2 (TX BB loop)

  • Page 84: A2.3 Trf Control Diagrams

    A2.3 TRF Control Diagrams LOSS_LIN_TXPAD_TRF_1 (0x0101[10:6]) CDC_I_TRF_1 (0x0104[7:4]) LMS7002M CDC_Q_TRF_1 (0x0104[3:0]) EN_LOWBWLOMX_TMX_TRF_1 (0x0100[15]) LOSS_MAIN_TXPAD_TRF_1 (0x0101[5:1]) Band 1 PD_TLOBUF_TRF_1 (0x0100[2]) PD_TLOBUF_TRF_1 (0x0100[2]) PD_TLOBUF_TRF_1 (0x0100[2]) TRF_TOP 1 Loss control LO I/Q decoder generator GCAS_GNDREF_TXPAD_TRF_1 (0x0102[15]) From: LOCH_IT(P/N) S1<4:0> D1<18:0> PD_TXPAD_TRF_1 (0x0100[1]) S2<4:0> D2<29:0>...
  • Page 85 LOSS_LIN_TXPAD_TRF_2 (0x0101[10:6]) CDC_I_TRF_2 (0x0104[7:4]) LMS7002M CDC_Q_TRF_2 (0x0104[3:0]) EN_LOWBWLOMX_TMX_TRF_2 (0x0100[15]) LOSS_MAIN_TXPAD_TRF_2 (0x0101[5:1]) Band 1 PD_TLOBUF_TRF_2 (0x0100[2]) PD_TLOBUF_TRF_2 (0x0100[2]) PD_TLOBUF_TRF_2 (0x0100[2]) TRF_TOP 2 Loss control LO I/Q decoder generator GCAS_GNDREF_TXPAD_TRF_2 (0x0102[15]) From:TLODIVOB_BUFOUT1 (TX RF) S1<4:0> D1<18:0> PD_TXPAD_TRF_2 (0x0100[1]) S2<4:0> D2<29:0> EN_LOOPB_TXPAD_TRF_2 (0x0101[0]) L_LOOPB_TXPAD_TRF_2 (0x0101[12:11]) Mixer gate...

  • Page 86: A2.4 Tbb Control Diagrams

    A2.4 TBB Control Diagrams LMS7002M RCAL_LPFH_TBB_1 (0x0109[15:8]) Channel I PD_LPFH_TBB_1 (0x0105[4]) TBB_TOP 1 PD_LPFLAD_TBB_1 (0x0105[2]) PD_LPFS5_TBB_1 (0x0105[1]) EN_G_TBB_1 (0x0105[0]) CCAL_LPFLAD_TBB_1 (0x010A[12:8]) LPF High STARTPULSE_TBB_1 (0x0105[15]) PD_LPFIAMP_TBB_1 (0x0105[3]) PD_LPFLAD_TBB_1 (0x0105[2]) PD_LPFS5_TBB_1 (0x0105[1]) LOOPB_TBB_1 (0x0105[14:12]) EN_G_TBB_1 (0x0105[0]) PD_LPFLAD_TBB_1 (0x0105[2]) CG_IAMP_TBB_1 (0x0108[15:10]) PD_LPFS5_TBB_1 (0x0105[1]) LPF current Switch...
  • Page 87 LMS7002M RCAL_LPFH_TBB_2 (0x0109[15:8]) Channel I PD_LPFH_TBB_2 (0x0105[4]) TBB_TOP 2 PD_LPFLAD_TBB_2 (0x0105[2]) PD_LPFS5_TBB_2 (0x0105[1]) EN_G_TBB_2 (0x0105[0]) CCAL_LPFLAD_TBB_2 (0x010A[12:8]) LPF High STARTPULSE_TBB_2 (0x0105[15]) PD_LPFIAMP_TBB_2 (0x0105[3]) PD_LPFLAD_TBB_2 (0x0105[2]) PD_LPFS5_TBB_2 (0x0105[1]) LOOPB_TBB_2 (0x0105[14:12]) EN_G_TBB_2 (0x0105[0]) PD_LPFLAD_TBB_2 (0x0105[2]) CG_IAMP_TBB_2 (0x0108[15:10]) PD_LPFS5_TBB_2 (0x0105[1]) LPF current Switch buffer From: tbbii(p/n)_2 (DAC) Switch...

  • Page 88: A2.5 Afe Control Diagram

    A2.5 AFE Control Diagram LMS7002M PD_TX_AFE_1 (0x0082[2]) ISEL_DAC_AFE (0x0082[15:13]) To: CLKTX_OUT_A (CLK delay) From: DTXI_AFE1<11:0> (TX TSP) To: tbbii(p/n)_1 (TX BB) core From: DTXQ_AFE1<11:0> (TX TSP) To: tbbiq(p/n)_1 (TX BB) From: CLKDAC (CLKGEN) MUX_AFE_1 (0x0082[11:10]) AFE mux From: pdeto(p/n)_1 (TX RF) From: bias_top_adcin<1:0>...

  • Page 89: A2.6 Bias Control Diagram

    A2.6 BIAS Control Diagram LMS7002M BIAS PD_BIAS_MASTER (0x0084[0]) Bias enable From: CORE_LDO_EN (PAD) block To: ADC and DAC (AFE) bias RP_CALIB_BIAS (0x0084[10:6]) PD_F_BIAS (0x0084[3]) Current Generator To: ip20f<47:1> (various blocks) From: CORE_LDO_EN (PAD) To: vr_rext (PAD) PD_FRP_BIAS (0x0084[4]) Current Generator vr_cal_ref From: CORE_LDO_EN (PAD) To: ip20frp<47:1>...

  • Page 90: A2.7 Sxr And Sxt Control Diagrams

    A2.7 SXR and SXT Control Diagrams VDIV_VCO_SXT<7:0> (0x0120[15:8]) Vtune LMS7002M SPDUP_VCO_SXT (0x011C[14]) CMPLO_CTRL_SXT (0x0122[13]) Comparator SEL_VCO_SXT<1:0> (0x0121[2:1]) PD_VCO_COMP_SXT (0x011C[2]) SX_TOP TX RSEL_LDO_VCO_SXT<4:0> (0x0121[15:11]) PD_VCO _SXT (0x011C[1]) To SPI: VCO_CMPHO_SXT (0x0123[13]) ICT_VCO_SXT<7:0> (0x0120[7:0]) CURLIM_VCO_SXT (0x011C[11]) To SPI: VCO_CMPLO_SXT (0x0123[12]) CSW_VCO_SXT<7:0> (0x0121[10:3]) BYPLDO_VCO_SXT (0x011C[13]) PD_FDIV_SXT...
  • Page 91 VDIV_VCO_SXR<7:0> (0x0120[15:8]) Vtune LMS7002M SPDUP_VCO_SXR (0x011C[14]) CMPLO_CTRL_SXR (0x0122[13]) Comparator SEL_VCO_SXR<1:0> (0x0121[2:1]) PD_VCO_COMP_SXR (0x011C[2]) SX_TOP RX RSEL_LDO_VCO_SXR<4:0> (0x0121[15:11]) PD_VCO _SXR (0x011C[1]) To SPI: VCO_CMPHO_SXR (0x0123[13]) ICT_VCO_SXR<7:0> (0x0120[7:0]) CURLIM_VCO_SXR (0x011C[11]) To SPI: VCO_CMPLO_SXR (0x0123[12]) CSW_VCO_SXR<7:0> (0x0121[10:3]) BYPLDO_VCO_SXR (0x011C[13]) PD_FDIV_SXR (0x011C[4]) TST_SX_SXR<2:0> (0x011F[5:3]) PW_DIV2_LOCH_SXR<2:0>...

  • Page 92: A2.8 Cgen Control Diagram

    A2.8 CGEN Control Diagram CMPLO_CTRL_CGEN (0x008B[14]) Vtune LMS7002M PD_VCO_COMP_CGEN (0x0086[1]) Comparator CLKGEN_TOP To SPI: VCO_CMPHO_CGEN (0x008C[13]) SPDUP_VCO_CGEN (0x0086[15]) PD_VCO _CGEN (0x0086[1]) To SPI: VCO_CMPLO_CGEN (0x008C[12]) PD_FDIV_O_CGEN (0x0086[4]) ICT_VCO_CGEN<7:0> (0x008B[13:9]) REV_CLKADC_CGEN (0x008A[13]) CSW_VCO_CGEN<7:0> (0x008B[8:1]) REV_CLKDAC_CGEN (0x008A[14]) TST_CGEN<2:0> (0x0089[2:0]) CLKH_OV_CLKL_CGEN<1:0> (0x0089[12-11]) TST_CGEN<2:0> (0x0089[2:0]) PD_VCO _CGEN (0x0086[2])

  • Page 93: A2.9 Xbuf Control Diagram

    A2.9 XBUF Control Diagram BYP_XBUF_TX (0x0085[5] LMS7002M Switch XBUF TX PD_XBUF_TX (0x0085[1] 3.3V Buffer 1.2V Buffer From: xoscin_tx (PAD) To: XCLK_TX (SX TX) SLFB_XBUF_TX (0x0085[7]) PD_XBUF_TX (0x0085[1] 1.2V Buffer BYP_XBUF_TX (0x0085[5] To: XCLK_TX_OUT2 (XBUF RX) EN_OUT2_XBUF_TX (0x0085[4] BYP_XBUF_RX (0x0085[6] LMS7002M Switch XBUF RX PD_XBUF_RX...

  • Page 94: A2.10

    A2.10 LDOs Control Diagram EN_LDO_DIGGN (0x0092[14]) EN_LDO_CPGN (0x0093[8]) EN_LOADIMP_LDO_DIGGN (0x0094[13]) EN_LOADIMP_LDO_CPGN (0x0095[1]) BYP_LDO_DIGGN (0x0096[10]) BYP_LDO_CPGN (0x0096[14]) SPDUP_LDO_DIGGN (0x0098[3]) SPDUP_LDO_CPGN (0x0098[7]) RDIV_DIGGN<7:0> (0x00A2[15:8]) RDIV_CPGN<7:0> (0x00A4[15:8]) ISINK_SPIBUFF<2:0> (0x00A6[15:13]) EN_LDO_DIVGN (0x0092[11]) RDIV_DIG<7:0> (0x00A3[7:0]) PD_LDO_SPIBUF (0x00A6[3]) EN_LDO_VCOGN (0x0093[3]) EN_LOADIMP_LDO_DIVGN (0x0094[10]) SPDUP_LDO_DIG (0x0098[4]) EN_LOADIMP_LDO_SPIBUF (0x00A6[6]) EN_LOADIMP_LDO_VCOGN (0x0093[12]) BYP_LDO_DIVGN...

  • Page 95: A2.11

    A2.11 CDS Control Diagram CDS_RXBTSP (0x00AF[11:10]) CDSN_RXBTSP (0x00AD[7]) Clock Delay Module RxTSP B CDS_RXATSP (0x00AF[9:8]) CDSN_RXATSP (0x00AD[6]) Clock Delay Module RxTSP A CDS_RXBLML (0x00AF[3:2]) CDSN_RXBLML (0x00AD[3]) CKRX_OUT Clock Delay Module CKRX_IN CDS_RXALML (0x00AF[1:0]) CDSN_RXALML (0x00AD[2]) CKTX_IN Clock Delay Module CKTX_OUT CDS_MCLK2 (0x00AF[15:14]) CDSN_MCLK2...

  • Page 96: A2.13

    A2.13 TxTSP(A/B) Control Diagram TSGFC (0x0200[9]) TSGFCW (0x0200[8:7]) TSGDCLDQ (0x0200[6]) TSGDCLDI (0x0200[5]) TSGSWAPIQ (0x0200[4]) TSGMODE GFIR2_BYP (0x0200[3]) (0x0208[5]) DCREG CMIX_GAIN GFIR2_L (0x020C[15:0]) (0x0208[15:14]) (0x0206[10:8]) DC_BYP PH_BYP GC_BYP CMIX_BYP GFIR2_N (0x0208[3]) (0x0208[0]) (0x0208[1]) (0x0208[8]) (0x0206[7:0]) ISINC_BYP HBI_OVR DCORRI IQCORR GCORRI CMIX_SC Memory space (0x0208[7]) (0x0203[14:12])

  • Page 97: A2.14

    A2.14 RxTSP(A/B) Control Diagram Data from BIST TSGFC (0x0400[9]) Capture TSGFCW CAPTURE (0x0400[8:7]) Data from RSSI (0x0400[15]) Register TSGDCLDQ CAPSEL (0x0400[6]) (0x0400[14:13]) CAPD[31:0] TSGDCLDI Data from ADC (0x0400[5]) [0x040E : 0x040F] AGC_BYP TSGSWAPIQ (0x040C[6]) (0x0400[4]) AGC_K TSGMODE (0x0409[1:0] & GFIR2_BYP Memory space (0x0400[3]) 0x0408[15:0])

  • Page 98: A2.15 Sxr, Sxt And Cgen Bist Control Diagram

    A2.15 SXR, SXT and CGEN BIST Control Diagram Control Signals FRAC_SDM_SXT 0x011E[3:0] & BSTATE 0x011D[15:0] 0x00A8[8] INT_SDM_SXT BIST 0x011E[13:4] BIST FSM Counter BSTART 0x00A8[0] FRAC_SDM_SXR FRAC_SDM_CGEN 0x011E[3:0] & 0x0088[3:0] & 0x011D[15:0] 0x0087[15:0] INT_SDM_SXR INT_SDM_CGEN 0x011E[13:4] 0x0088[13:4] EN_SDM_TSTO_SXR 0x011C[7] (MIMO A) BENR 0x00A8[2] EN_SDM_TSTO_SXT...

  • Page 99: A2.16 Txtsp(A/B) Bist Control Diagram

    A2.16 TxTSP(A/B) BIST Control Diagram Control Signals BSTATE 0x0209[0] BIST BIST FSM Counter BSTART 0x0200[1] TxTSP Signature Signature Generator Generator Channel Q Channel I Test Vector Generator BSIGQ BSIGI 0x020B[14:0] & 0x020A[7:0] & 0x020A[15:8] 0x0209[15:1] Figure 25 TxTSP(A/B) BIST control structure A2.17 RxTSP(A/B) BIST Control Diagram Control Signals...

  • Page 100: Limelight Tm Control Diagram

    A2.18 LimeLight Control Diagram Data from MCLK2_DIV (0x002C[15:8]) MCLK2_EN (0x002B[0]) RxTSP(A/B) rxtspclk(A/B) rxclkdivided DIV by 2÷512 MCLK2_SRC (0x002B[5:4]) (even numbers) RNDGEN MCLK2_INV (0x002B[9]) txclkdivided rxclkdivided RX_MUX (0x002A[11:10]) txtspclkA mclk2 rxtspclkA fclk1i RX_MUX fclk2i mclk2i RXWRCLK_MUX (0x002A[1:0]) MCLK2_DLY (0x002B[13:12]) RXRDCLK_MUX (0x002A[3:2]) mclk1dly wrclk(A/B) LML2_TRXIQPULSE...

  • Page 101: A2.19

    A2.19 DC offset correction Control Diagram LMS7002M DC offset correction TIA 1 From: tbbii(p/n)_1 (DAC) From: RX_mixer_i_1 (RX RFE) TBB 1 RBB 1 From: tbbiq(p/n)_1 (DAC) From: RX_mixer_q_1 (RX RFE) PD_DCDAC_RXA (0x05C0[6]) PD_DCDAC_TXA (0x05C0[4]) DCWR_RXAI (0x05C7[15]) DCWR_TXAI (0x05C3[15]) PD_DCCMP_TXA (0x05C0[0]) PD_DCCMP_RXA (0x05C0[2]) DCRD_RXAI...

  • Page 102: A2.20 Measurement Block Control Diagram

    A2.20 Measurement block Control Diagram MEASR_PDET2_VAL<7:0> (0x0604[15:8]) LMS7002M MEASR_PDET1_VAL<7:0> (0x0604[7:0]) MEASR_RSSI2_VAL<7:0> (0x0605[15:8]) MEASR_RSSI1_VAL<7:0> (0x0605[7:0]) Measurement MEASR_TREF_VAL<7:0> (0x0606[15:8]) MEASR_TPTAT_VAL<7:0> (0x0606[7:0]) block MEASR_BIAS<4:0> (0x0602[13:9]) MEASR_PD (0x0600[0]) MEASR_MODE (0x0600[1]) MEASR_CLKDIV<7:0> (0x0600[15:8]) Logic and From: XCLK_RX (XBUF RX) SPI control MEASR_DAC_VAL<7:0> (0x0603[7:0]) MEASR_CMPCFG_TREF (0x0602[5]) MEASR_CMPSTATUS_TREF (0x0601[5]) MEASR_HYSCMP<2:0>...

  • Page 103: Calibration Algorithms

    Calibration algorithms A3.1 VCO coarse tuning This chapter describes the algorithm for VCO coarse tuning, which finds the optimum SWC_VCO[7:0] value. VCO coarse tuning algorithm goes through 3 following phases: 1. Initialization: sets the static control words for the synthesizer 2.
  • Page 104 VCO_CoarseTuning_SXT_SXR Input Parameters: Fref_MHz, Fvco_des_MHz, ch Return Parameters: Result MAC[1:0] (0x0040[1:0]) := ch EN_COARSEPLL_(SXT, SXR) (0x011C[12]) := 1 COARSE_START_(SXT, SXR) (0x0121[0]) := 0 EN_INTONLY_SDM_(SXT, SXR) (0x011C[9]) := 1 SPDUP_VCO_(SXT, SXR) (0x011C[14]) := 1 Nround := round(4*Fvco_des/Fref) Initialization FRAC_SDM_(SXT, SXR)[15:0] (0x011D[15:0]) := 0 FRAC_SDM_(SXT, SXR)[19:16] (0x011E[3:0]) := 0 INT_SDM_(SXT, SXR)[9:0] (0x011E[13:4]) := Nround-4 CSW_VCO_(SXT, SXR)[7:0] (0x0121[10:3]) := 0...
  • Page 105 VCO_CoarseTuning_CGEN Input Parameters: Fref_MHz, Fvco_des_MHz Return Parameters: Result EN_COARSE_CKLGEN (0x0086[10]) := 1 COARSE_START_CGEN (0x008B[0]) := 0 EN_INTONLY_SDM_CGEN (0x0086[9]) := 1 SPDUP_VCO_CGEN (0x0086[15]) := 1 Nround := round(4*Fvco_des/Fref) Initialization FRAC_SDM_CGEN[15:0] (0x0087[15:0]) := 0 FRAC_SDM_CGEN[19:16] (0x0088[3:0]) := 0 INT_SDM_CGEN [9:0] (0x0088[13:4]) := Nround-4 CSW_VCO_CGEN[7:0] (0x008B[8:1]) := 0 i := 7 TRY_CNT := 0...

  • Page 106: A3.2 Main Resistor (Bias) Calibration

    while (Get_SPI_Reg_bits(0x0123, 15, 15) != 1) //wait till COARSE_STEPDONE=1 try_cnt++; if(try_cnt > MAX_TRY_CNT) return 0; if (Get_SPI_Reg_bits(0x0123, 14, 14) == 1) //check CAORSEPLL_COMPO Modify_SPI_Reg_bits (0x0121, 3 + i, 3 + i, 0); // SWC_VCO<i>=0 Modify_SPI_Reg_bits (0x0121, 0, 0, 0); // COARSE_START=0 if(i==0) break;...
  • Page 107  Use the Q input of the ADC of Channel 1 to read the difference between on chip fixed voltage and off-chip voltage.  Compare the ADC value with best value (which is initially set to very high). If ADC value is lower, then save it as “Best Value”. 3.

  • Page 108: A3.3 Rbb Calibration

    RP_CALIB_BIAS++; Modify_SPI_Reg_bits (0x0084, 10, 6, RP_CALIB_BIAS_cal); // set the control RP_CAL_BIAS to stored calibrated value *ratio = (float) 16/RP_CALIB_BIAS_cal; //calculate ratio A3.3 RBB calibration RBB calibration is divided into two calibrations for low and high bands. Each calibration consist of several smaller algorithms. A3.3.1 RBB Low Band Calibration Calibration steps:...
  • Page 109 Calibration_LowBand_RBB Input Parameters: channel Return Parameters: status Save current configuration Select channel Perform Algorithm_A_RBB Procedure and get Result Perform Algorithm_B_RBB Procedure and get Result Result == TRUE Perform Algorithm_F_RBB Procedure for 1.4 MHz band and get Result Perform Algorithm_F_RBB Procedure for 3.0 MHz band and get Result Perform Algorithm_F_RBB Procedure for 5.0 MHz band and get Result...

  • Page 110: A3.3.2 Rbb High Band Calibration

    result = 1; RESTORE: Restore_config_RBB (); //restore configuration return result; A3.3.2 RBB High band Calibration Calibration steps: 1. Save current configuration 2. Select channel 3. Calibrate (by measurement using loopback path 8) the control value of the CBANK( High Band Section) at the 37MHz/2 bandwidth. => Register the CBANK control value for the high-band section for 37MHz rxMode.

  • Page 111: A3.4 Nested Algorithms

    The following is the C code implements described algorithm: unsigned char Calibration_HighBand_RBB (unsigned char ch) unsigned char result = 0; Save_config_RBB (); //save current configuration MIMO_Ctrl (ch); Modify_SPI_Reg_bits (0x040A, 13, 12, 1); // AGC Mode = 1 (RSSI mode) Set_cal_path_RBB (8); //Set control signals to path 8 (RX HighBand) if (Algorithm_B_RBB (&LowFreqAmp) != 1) goto RESTORE;...
  • Page 112 1. Set DAC output to 100kHz single tone. 2. Start with the nominal setting value for “CG_IAMP_TBB”. 3. Linearly and proportionally adjust “CG_IAMP_TBB<5:0>” control lines to have about 80% of full scale swing. For this: measure the output, if the output was lower or higher than 80%, then adjust “CG_IAMP_TBB”...

  • Page 113: A3.4.3 Algorithm F

    C code for algorithm B: unsigned char Algorithm_B_RBB (unsigned short *LowFreqAmp) unsigned short ADCOUT; unsigned char CG_IAMP_TBB, gain_inc; Set_NCO_Freq (0.1); // Set DAC output to 100kHz (0.1MHz) single tone. CG_IAMP_TBB = 24; //set nominal CG_IAMP_TBB value Modify_SPI_Reg_bits (0x0108, 15, 10, CG_IAMP_TBB); //write val to reg //Modify_SPI_Reg_bits (0x040A, 13, 12, 1);...
  • Page 114 Algorithm_F_RBB Input Parameters: Band_id Return Parameters: status Band <= 20 MHz ? low_band := 0 low_band := 1 CONTROL := 0x7FF CONTROL := 0xFF C_CTL_LPFH_RBB_(1, 2)[7:0](0x0116[7:0]) := C_CTL_LPFL_RBB_(1, 2)[10:0](0x0117[10:0]) := CONTROL CONTROL Apply a single tone frequency at (Band/2) ADCOUT := RSSI[15:0] (0x040B[15:0]) ADCOUT >= LowFreqAmp CONTROL == 0 CONTROL := CONTROL –...

  • Page 115: A3.5 Tbb Calibration

    if(Band_id <= RBB_20_0MHZ) //low band low_band = 1; // CONTROL=C_CTL_LPFL_RBB CONTROL = 0xFF; // Set the CONTROL to maximum value. This should bring the output cutt-off frequency to minimum. Modify_SPI_Reg_bits (0x0117, 10, 0, CONTROL); // write to C_CTL_LPFL_RBB else //high band low_band = 0;...
  • Page 116 7. Calibrate (by measurement using loopback path 3) the control value of the RBANK (ladder only) for the 5.5MHz bandwidth setting => Register the value of the RBANK controls. 8. Adjust the value of the real pole controls by -50% (pre-emphasis/real pole RBANK). 9.
  • Page 117 Calibration_LowBandBand_TBB Input Parameters: channel Return Parameters: status Save current configuration Select channel AGC_MODE[1:0](0x040A[13:12]) Perform Algorithm_A_TBB Procedure and get Result Perform Algorithm_B_RBB Procedure for 11 MHz band, path 3 and get Result Perform Algorithm_C_TBB Procedure and get Result Perform Algorithm_D_RBB Procedure for path 4 and get Result Perform Algorithm_E_RBB Procedure for 8.2 MHz band, path 5 and get Result...

  • Page 118: A3.7 Tbb High Band Calibration

    A3.7 TBB High Band Calibration Calibration steps: 1. Save current configuration 2. Calibrate (by measurement using loopback path 6) the control value of the RBANK at the18.5MHz bandwidth. => Register the RBANK control value for the 18.5MHz. 3. Calibrate (by measurement using loopback path 6) the control value of the RBANK for the 38MHz bandwidth setting =>...

  • Page 119: A3.8 Nested Algorithms

    A3.8 Nested algorithms A3.8.1 Algorithm A Multiply the ratio of the on-chip resistor to the off-chip resistor by the default control value of the RCAL_LPFLAD_TBB for 11MHz and return the result of the multiplication. C code for algorithm A: void Algorithm_A_TBB () unsigned char RCAL_LPFLAD_TBB;...
  • Page 120 4. Decrease the control value “CCAL_LPFLAD_TBB” by one step. 5. Jump back to line #3. 6. Store the value of “CCAL_LPFLAD_TBB” as the calibrated CBANK value of TBB. C code for algorithm C: unsigned char Algorithm_C_TBB (unsigned char Band_id) unsigned short ADCOUT, LowFreqAmp; unsigned char CONTROL;...

  • Page 121: A3.8.4 Algorithm D

    A3.8.4 Algorithm D Algorithm steps: 1. Apply a single tone at frequency equal to “CalFreq” 2. Compare the amplitude at the input ADC to “LowFreqAmp”. If greater, then the pre- emphasis zero is faster than the real pole. And Vise-Versa. Decrease or increase respectively the zero frequency by one step.
  • Page 122 8. Return the value of CONTROL. Algorithm_E_TBB Input Parameters: Band Return Parameters: status CONTROL := 0 Band <= 11 MHz ? low_band := 0 low_band := 1 RCAL_LPFH_TBB_(1, 2)[7:0](0x0109[15:8]) := RCAL_LPFLAD_TBB_(1, 2)[7:0](0x0109[7:0]) := CONTROL CONTROL Perform Algorithm_B_TBB Procedure and get Result Apply a single tone frequency at Band ADCOUT := RSSI[15:0] (0x040B[15:0]) ADCOUT >= LowFreqAmp...
  • Page 123 if(Band_id <= TBB_11_0MHZ) //If(“CalFreq”) <=11MHz, then CONTROL=RCAL_LPFLAD_TBB, else, CONTROL=RCAL_LPFH_TBB low_band = 1; // CONTROL=RCAL_LPFLAD_TBB Modify_SPI_Reg_bits (0x0109, 7, 0, CONTROL); // write to RCAL_LPFLAD_TBB else low_band = 0; // CONTROL=RCAL_LPFH_TBB Modify_SPI_Reg_bits (0x0109, 15, 8, CONTROL); // write to RCAL_LPFH_TBB if (Algorithm_B_TBB (&LowFreqAmp) != 1) return 0; // Calibrate and Record the low frequency output amplitude (Algorithm B) Set_NCO_Freq (TBB_CalFreq[Band_id]);...

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