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Sundance Technology SMT351T User Manual

Fpga module
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Sundance Multiprocessor Technology Limited
SMT351T
Unit / Module Description:
Unit / Module Number:
Document Issue Number:
Issue Date:
Original Author:
SMT351T User Guide
Sundance Multiprocessor Technology Ltd, Chiltern House, Waterside,
This document is the property of Sundance and may not be copied nor
communicated to a third party without prior written permission.
© Sundance Multiprocessor Technology Limited 2006
SMT351T User Guide
FPGA module
SMT351T
E.P
Chesham, Bucks. HP5 1PS.
Form : QCF42
Date : 6 July 2006
Last Edited: 22/02/2008 18:00:00

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Summary of Contents for Sundance Technology SMT351T

  • Page 1 SMT351T Document Issue Number: Issue Date: Original Author: SMT351T User Guide Sundance Multiprocessor Technology Ltd, Chiltern House, Waterside, Chesham, Bucks. HP5 1PS. This document is the property of Sundance and may not be copied nor communicated to a third party without prior written permission.
  • Page 2 1.0.2 Updated Figure 3, updated RSL, SLB descriptions 30/01/08 1.0.3 updated number of RSL links available per FPGA, 22/02/08 Top and Bottom View, SLB warning considering its voltage level SMT351T User Guide Page 2 of 38 Last Edited: 22/02/2008 18:00:00...

  • Page 3: Table Of Contents

    4.2.15 Performance......................20 Interface Description ....................20 4.3.1 Power Budget .....................20 Footprint ........................22 Top View........................22 Bottom View ......................23 Pinout.........................24 FPGA Pin allocation by bank .................24 SHB..........................33 SLB ..........................33 Qualification Requirements ..................35 SMT351T User Guide Page 3 of 38 Last Edited: 22/02/2008 18:00:00...
  • Page 4 Qualification Tests....................35 7.1.1 Meet Sundance standard specifications............35 7.1.2 Speed qualification tests ..................35 7.1.3 Integration qualification tests ................35 Support Packages ......................35 Physical Properties ....................36 Safety .........................37 EMC ...........................38 Ordering Information ....................38 SMT351T User Guide Page 4 of 38 Last Edited: 22/02/2008 18:00:00...
  • Page 5 Table 3: DIP switch SW1 position for the selection of the Flash erase & program operations........................18 Table 4: Coolrunner II resources summary.................21 Table 5:Coolrunner II pin resources..................21 SMT351T User Guide Page 5 of 38 Last Edited: 22/02/2008 18:00:00...

  • Page 6: Introduction

    1 Introduction The SMT351T is an FPGA TIM module designed to be integrated in modular systems. It is designed to connect to the huge range of other TIM modules and carriers developed by Sundance. Sundance modular solutions provide flexible and upgradeable systems.

  • Page 7: Related Documents

    A TIM with no on-board DSP, where the FPGA provides all functionality. Firmware A proprietary FPGA design providing some sort of functionality. Sundance Firmware is the firmware running in an FPGA of a DSP module. SMT351T User Guide Last Edited: 22/02/2008 18:00:00...
  • Page 8 SMT351T User Guide Page 8 of 38 Last Edited: 22/02/2008 18:00:00...

  • Page 9: Functional Description

    4 Functional Description The SMT351T provides a Virtex 5 FPGA, memory and IO connectors to allow the development of applications ranging from Software defined Radio to MIMO, video, Signal processing. Typically, an ADC/DAC mezzanine can be fitted on the SLB connector and memory is used to store burst data between the outside world/host/other TIMs, while the FPGA implements functions on that data.

  • Page 10: Module Description

    Flash programming selection via switch SW1 (See Table 3) Software Library Support available from Sundance. The code can run on Sundance DSP TIM or a Host. All the flash functionalities are available. SMT351T User Guide Page 10 of 38 Last Edited: 22/02/2008 18:00:00...

  • Page 11: Jtag Header

    The FPGA configuration bitstream source is • On Comport 3: The CPLD is connected to the Comport 3 link of the SMT351T TIM connector. (See block1). A switch is used to select Comport 3 as the link that will be used to receive the bitstream.

  • Page 12: Fpga Reset Scheme

    JTAG and provide an end key word on comport 3 to the CPLD so that it releases the Reset. (FPGAresetn). 4.2.6 FPGA Reset Scheme The CPLD is connected to a TIM global Reset signal provided to the SMT351T via its primary TIM connector pin 30. (See TI TIM specification & User’s guide).

  • Page 13: Figure 2: Cpld State Machine

    Fpgaresetn generated by the CPLD, as the comport is shared between the two. The Reset control is operated by the CPLD line FPGAResetn. The following diagram shows the CPLD states after Reset. Figure 2: CPLD state machine SMT351T User Guide Page 13 of 38 Last Edited: 22/02/2008 18:00:00...

  • Page 14: Fpga Bitstream Formatting

    Depending on the FPGA and design implemented, performances might vary. Each bank is fully independent with separate address, control and data busses and arranged as follows: SMT351T User Guide Page 14 of 38 Last Edited: 22/02/2008 18:00:00...

  • Page 15: Figure 3: Fpga Connections To Ddr2Sdram

    The Memory controllers generated by MIG1.72 and MIG2.0 have been successfully running at 200MHz. The pinout was not generated using MIG2.0 but the controllers generated by MIG2.0 can be used with the SMT351T pinout. Also see Xilinx AR#29313 The devices used are Micron...

  • Page 16: Sundance Rocket Io Serial Link

    Sundance boards can be interconnected using RSL connectors located on the front and back of the board. The SMT351T has four connectors in total (two at the front and two at the back). The boards connected via RSL use the RSL protocol to communicate. Refer to the Sundance Help File for more details.

  • Page 17: Tim Connectors

    TIM connectors provide 4 communication links (Comports) and a Global Bus to the FPGA. The comports which are available on the SMT351T are CP0, CP1, CP3, and CP4. They allow interfacing to Sundance TIM modules or to a Host PC providing that you implement a Comport Interface inside the FPGA.

  • Page 18: Available Clocks

    • 125mhz LVDS oscillator. Connected to the FPGA. Used to clock the MGTs. An external clock can be input into the Virtex 5 FPGA via the SLB connector. Sundance applies this scheme for ADC/DAC mezzanines. SMT351T User Guide Page 18 of 38 Last Edited: 22/02/2008 18:00:00...

  • Page 19: Figure 4: Fpga Clock Buffers Usage

    P side) MIDDLE LEFT COLUMN RIGHT COLUMN COLUMN pxiclk 50Mhz single ended 125MHz differential TIM Conn PXICLK oscillator Figure 4: FPGA clock buffers usage. SMT351T User Guide Page 19 of 38 Last Edited: 22/02/2008 18:00:00...

  • Page 20: Leds

    The SMT351T draws its power from the 3.3v rail of the PCI. The PCI specification stipulates that the maximum power for one card is 25W. Therefore, the maximum current that the SMT351T could draw from +3.3V is 7.6A, assuming zero current on all the other supply voltages.

  • Page 21: Table 4: Coolrunner Ii Resources Summary

    218/256 (86%) 531/896 (60%) 190/256 (75%) 69/106 (66%) 445/640 (70%) Table 4: Coolrunner II resources summary. Signal Type Required Mapped Pin Type Used Total Input Output GCK/IO Bidirectional GTS/IO GSR/IO CDR/IO DGE/IO Table 5:Coolrunner II pin resources. SMT351T User Guide Last Edited: 22/02/2008 18:00:00...

  • Page 22: Footprint

    5 Footprint 5.1 Top View Figure 5: Top View SMT351T User Guide Last Edited: 22/02/2008 18:00:00...

  • Page 23: Bottom View

    5.2 Bottom View RSL Connector DDR2 SDRAM Memory Core Power supply Oscillator Flash Memory RSL Connector Figure 6: Bottom view SMT351T User Guide Last Edited: 22/02/2008 18:00:00...

  • Page 24: Pinout

    X0Y116 IO_L3P_15 DDRA_D16 IOB_X0Y232 X0Y116 IO_L3N_15 DDRA_D15 IOB_X0Y231 X0Y115 IO_L4P_15 IOB_X0Y230 X0Y115 IO_L4N_VREF_15 DDRA_D14 IOB_X0Y229 X0Y114 IO_L5P_15 DDRA_D13 IOB_X0Y228 X0Y114 IO_L5N_15 DDRA_D12 IOB_X0Y227 X0Y113 IO_L6P_15 DDRA_D11 IOB_X0Y226 X0Y113 IO_L6N_15 DDRA_D10 IOB_X0Y225 X0Y112 IO_L7P_15 SMT351T User Guide Last Edited: 22/02/2008 18:00:00...
  • Page 25 DDRA_D51 IOB_X0Y163 X0Y81 IO_L18P_SM10P_11 DDRA_D50 IOB_X0Y162 X0Y81 IO_L18N_SM10N_11 DDRA_D49 IOB_X0Y161 X0Y80 IO_L19P_SM9P_11 DDRA_D48 IOB_X0Y160 X0Y80 IO_L19N_SM9N_11 DDRB_D39 IOB_X0Y159 X0Y79 IO_L0P_SM8P_13 X0Y3 DDRB_D38 IOB_X0Y158 X0Y79 IO_L0N_SM8N_13 DDRB_D37 IOB_X0Y157 X0Y78 IO_L1P_SM7P_13 SMT351T User Guide Page 25 of 38 Last Edited: 22/02/2008 18:00:00...
  • Page 26 IO_L12P_VRN_17 AE31 IOB_X0Y94 X0Y47 IO_L12N_VRP_17 AD30 DDRB_D28 IOB_X0Y93 X0Y46 IO_L13P_17 AC29 DDRB_D50 IOB_X0Y92 X0Y46 IO_L13N_17 AF31 DDRB_D30 IOB_X0Y91 X0Y45 IO_L14P_17 AG31 IOB_X0Y90 X0Y45 IO_L14N_VREF_17 AE29 DDRB_D52 IOB_X0Y89 X0Y44 IO_L15P_17 SMT351T User Guide Page 26 of 38 Last Edited: 22/02/2008 18:00:00...
  • Page 27 IO_L5N_GC_3 SWITCH0 IOB_X1Y207 X48Y103 IO_L6P_GC_3 SWITCH1 IOB_X1Y206 X47Y103 IO_L6N_GC_3 SWITCH2 IOB_X1Y205 X48Y102 IO_L7P_GC_3 SWITCH3 IOB_X1Y204 X47Y102 IO_L7N_GC_3 LED0 IOB_X1Y203 X48Y101 IO_L8P_GC_3 LED1 IOB_X1Y202 X47Y101 IO_L8N_GC_3 LED2 IOB_X1Y201 X48Y100 IO_L9P_GC_3 SMT351T User Guide Page 27 of 38 Last Edited: 22/02/2008 18:00:00...
  • Page 28 IO_L9P_CC_GC_4 AG17 PXITRIG4 IOB_X1Y100 X47Y50 IO_L9N_CC_GC_4 IOB_X2Y279 X100Y139 IO_L0P_20 X1Y6 IOB_X2Y278 X99Y139 IO_L0N_20 IOB_X2Y277 X100Y138 IO_L1P_20 IOB_X2Y276 X99Y138 IO_L1N_20 IOB_X2Y275 X100Y137 IO_L2P_20 IOB_X2Y274 X99Y137 IO_L2N_20 CLOCKOUTIP IOB_X2Y273 X100Y136 IO_L3P_20 SMT351T User Guide Page 28 of 38 Last Edited: 22/02/2008 18:00:00...
  • Page 29 IO_L13N_12 SLB_DAIP6 IOB_X2Y171 X100Y85 IO_L14P_12 SLB_DAIN6 IOB_X2Y170 X99Y85 IO_L14N_VREF_12 SLB_DAIP1 IOB_X2Y169 X100Y84 IO_L15P_12 SLB_DAIN1 IOB_X2Y168 X99Y84 IO_L15N_12 DATAOFRANGEIP IOB_X2Y167 X100Y83 IO_L16P_12 DATAOFRANGEIN IOB_X2Y166 X99Y83 IO_L16N_12 SLB_DBIP0 IOB_X2Y165 X100Y82 IO_L17P_12 SMT351T User Guide Page 29 of 38 Last Edited: 22/02/2008 18:00:00...
  • Page 30 IO_L8P_CC_22 AL10 C3D1 IOB_X2Y62 X99Y31 IO_L8N_CC_22 C3D2 IOB_X2Y61 X100Y30 IO_L9P_CC_22 C3D3 IOB_X2Y60 X99Y30 IO_L9N_CC_22 AD10 C3D4 IOB_X2Y59 X100Y29 IO_L10P_CC_22 AD11 C3D5 IOB_X2Y58 X99Y29 IO_L10N_CC_22 AK11 C3D6 IOB_X2Y57 X100Y28 IO_L11P_CC_22 SMT351T User Guide Page 30 of 38 Last Edited: 22/02/2008 18:00:00...
  • Page 31 MGTRXP1_114 MGTRXN1_114 MGTRXP0_114 MGTRXN0_114 MGTTXP1_114 MGTTXN1_114 MGTTXP0_114 MGTTXN0_114 MGTAVCCPLL_114 MGTAVCC_114 MGTAVCC_114 MGTAVTTRX_114 MGTAVTTTX_114 MGTAVTTTX_114 MGTREFCLKP_116 MGTREFCLKN_116 MGTRXP1_116 MGTRXN1_116 MGTRXP0_116 MGTRXN0_116 MGTTXP1_116 MGTTXN1_116 MGTTXP0_116 MGTTXN0_116 MGTAVCCPLL_116 MGTAVCC_116 MGTAVCC_116 MGTAVTTRX_116 MGTAVTTTX_116 SMT351T User Guide Page 31 of 38 Last Edited: 22/02/2008 18:00:00...
  • Page 32 MGTTXP1_122 MGTTXN1_122 MGTTXP0_122 MGTTXN0_122 MGTAVCCPLL_122 MGTAVCC_122 MGTAVCC_122 MGTAVTTRX_122 MGTAVTTTX_122 MGTAVTTTX_122 MGTREFCLKP_124 MGTREFCLKN_124 MGTRXP1_124 MGTRXN1_124 MGTRXP0_124 MGTRXN0_124 MGTTXP1_124 MGTTXN1_124 MGTTXP0_124 MGTTXN0_124 MGTAVCCPLL_124 MGTAVCC_124 MGTAVCC_124 MGTAVTTRX_124 MGTAVTTTX_124 MGTAVTTTX_124 MGTREFCLKP_126 MGTREFCLKN_126 MGTRXP1_126 SMT351T User Guide Page 32 of 38 Last Edited: 22/02/2008 18:00:00...

  • Page 33: Shb

    SMT384: single ended clock clkoutip ChA (used in standard firmware) Clkoutin ChB (not used in standard firmware) o SMT391: Differential clock Channel I: clkoutip Channel Q: clkoutqp o SMT390: Differential clock clockoutqp SMT351T User Guide Page 33 of 38 Last Edited: 22/02/2008 18:00:00...
  • Page 34 SMT351T User Guide Page 34 of 38 Last Edited: 22/02/2008 18:00:00...

  • Page 35: Qualification Requirements

    Integration qualification tests • Must work on ALL Sundance platforms as a root TIM module or as part of a network of TIMs on carriers. • Must be able to work stand-alone. 8 Support Packages SMT351T User Guide Last Edited: 22/02/2008 18:00:00...

  • Page 36: Physical Properties

    9 Physical Properties Dimensions Weight Supply Voltages Supply Current +12V +3.3V -12V MTBF SMT351T User Guide Last Edited: 22/02/2008 18:00:00...

  • Page 37: Safety

    10 Safety This module presents no hazard to the user when in normal use. SMT351T User Guide Page 37 of 38 Last Edited: 22/02/2008 18:00:00...

  • Page 38: Emc

    SMT351T-SX95-x-2 Fitted with an XC5VSX95T and 2Gbytes of memory. x represents the FPGA speed grade. Note that the LX50 and SX50 options only provide 12 RSL links. See RSL section for more details. SMT351T User Guide Last Edited: 22/02/2008 18:00:00...

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