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Related Manuals for Terasic HSMC-NET
Summary of Contents for Terasic HSMC-NET
- Page 1 HSMC-NET Terasic HSMC-NET Daughter Board User Manual...
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Page 2: Table Of Contents
4.4 Setup the Demonstration ....................... 25 4.5 Demo Operation ........................... 26 4.6 Overview ............................28 4.7 Nios Program..........................29 Chapter 5 Appendix ........................ 31 5.1 Revision History ........................... 31 5.2 Always Visit HSMC-NET Webpage for New Main board .............. 31... -
Page 3: Chapter 1 Introduction
Chapter 1 Introduction The Terasic HSMC-NET is a Gigabit Ethernet transceiver with a High Speed Mezzanine Connector (HSMC) interface. It offers network transfers of up to 1 Gbps with the host board using a HSMC connector. Also, it provides a fully integrated Ethernet solution enabling fast implementation design, shortening development times, and allows you to focus on the core functions of the system design. -
Page 4: About The Kit
Figure 1-1 The HSMC-NET board This section describes the package content HSMC-NET board x 1 System CD-ROM x 1 The CD contains technical documents of the HSMC-NET, and one reference design along with the source code. Figure 1-2 HSMC-NET Package... -
Page 5: Assemble The Hsmc-Net Board
This section describes how to connect the HSMC-NET daughter board to a main board, and using DE3 as an example shown in Figure 1-4. The HSMC-NET daughter board connects to the main boards through the HSMC interface. For the DE3, the HSMC-NET can be connected to any DE3‟s four HSTC connectors using a THCB-HFF... -
Page 6: Getting Help
Note. Do not attempt to connect/remove the HSMC-NET daughter board to/from the main the main board when the power is on, or else the hardware could be damaged. Here are some places to get help if you encounter any problem: ... -
Page 7: Chapter 2 Architecture
Chapter 2 Architecture This Chapter covers the architecture of the HSMC-NET board including its PCB and block diagram. The picture of the HSMC-NET board is shown in Figure 2-1 Figure 2-2. It depicts the layout of the board and indicates the location of the connectors and key components. -
Page 8: Block Diagram
Figure 2-2 The HSMC-NET Back side – HSMC connector view The following components are provided on the HSMC-NET board : Ethernet Transceiver (J2/J3) 25MHz Oscillator (Y1/Y2) HSMC expansion connector (J1) Marvell 88E1111 Ethernet Device (U2/U3) Voltage Regulator (REG1/REG2) ... - Page 9 Figure 2-3 The block diagram of the HSMC-NET board...
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Page 10: Chapter 3 Board Components
This section illustrates the detailed information of the components, connector interfaces, and the pin mapping tables of the HSMC-NET board This section describes pin definition of the HSMC-NET interface onboard All the control and data signals of the Ethernet transmitter and receiver are connected to the HSMC connector, so users can fully control the HSMC daughter board through the HSMC interface. - Page 13 Figure 3-1 The pin-outs on the HSMC connector Table 3-1 below lists the HSMC signal direction and description. Table 3-1 Note. The power pins are not shown in the...
- Page 14 Table 3-1 The pin assignments for the HSMC connector (J1) HSMC Pin Signal Name Number Direction Description NET1_S_RX_p Input SGMII receive data positive (Ethernet 1) NET1_S_RX_n Input SGMII receive data negative (Ethernet 1) NET1_RX_CRS Input Carrier Sense pin (Ethernet 1) NET1_S_TX_p Output SGMII transmit data postive (Ethernet 1)
- Page 15 SGMII 625 MHz positive receive clock NET0_S_CLKp input (Ethernet 0) NET0_GTX_CLK output Transmit Clock (Ethernet 0) SGMII 625 MHz negative receive clock NET0_S_CLKn input (Ethernet 0) NET0_RX_D2 input Receive code group bit 2 (Ethernet 0) Parallel LED output for link indicator NET0_LED_LINK1000 input (Ethernet 0)
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Page 16: I2C Serial Eeprom
This section describes the I2C Serial EEPROM on the HSMC-NET board The HSMC-NET board provides an EEPROM (U1) which is configured by the I2C interface. The size of the EEPROM is 2K-bit which can store MAC information or user‟s data. The Default I2C slave address is „0xA0‟. -
Page 17: Chapter 4 Demonstrations
This section describes the functionality of the demonstration briefly. In this demonstration, we use DE3 as the host board connected to the HSMC-NET daughter board. However, the HSMC-NET and Cyclone III FPGA Starter Kit Demo is also available in the HSMC-NET CD-ROM. -
Page 18: How The Demonstration Is Built
The demonstration is setup using the DE3 System builder (v1.4.2) by configuring the DE3 I/O components and also building a connection between DE3 and HSMC-NET. In DE3 configuration we enabled the IO HSTC connector Group C to connect to the HSMC-NET shown in Figure 4-2. - Page 19 4-3. The I/O standard voltage for the HSMC-NET daughter board is 2.5V. Once the connection is established between DE3 board and HSMC-NET board, the DE3 System builder will change the I/O standard of the connector to fit with the daughter board automatically.
- Page 20 Figure 4-3 Note: A 2.5V standard voltage must be used for the HSMC-NET daughter board) The following step we use the SOPC builder to create our SOPC. The SOPC includes the CPU processor, On-Chip memory, DDR2 controller, JTAG UART, system ID, timer, Triple-Speed Ethernet, Scatter-Gather DMA controller and peripherals which are linked together contained in the Nios II hardware system that are used when building a project.
- Page 21 Figure 4-4 Triple-Speed Ethernet Core Configuration In the Mac Options section, the MDIO module is included that controls the PHY Management Module associated with the MAC block shown in Figure 4-5. The host Clock divisor is to divide the MAC control register interface clock to produce the MDC clock output on the MDIO interface. The MAC control register interface clock frequency is 100 MHz and the desired MDC clock frequency is 2.5 MHz, a host clock divisor of 40 should be used.
- Page 22 Figure 4-5 Triple-Speed Ethernet MAC Options Once the Triple-Speed Ethernet IP configuration has been set and necessary hardware connections has been made shown in Figure 4-6 click on generate.
- Page 23 Figure 4-6 SOPC builder The Block diagram shows the connection for programmable 10/100/1000 Ethernet operation via GMII Figure 4-7 shows how gigabit Ethernet PHYs are connected to the MAC via GMII...
- Page 24 In this next section describes the steps to create the Simple Socket Server using Nios II. We create a new project in Nios II using the project template, Simple Socket Server. The PTF file created using the SOPC builder in Quartus II is used in the Select Target Hardware section. Figure 4-8 Nios II Project Simple Socket Server After the project is created, open network_utilities.c to modifty the flash section which uses flash to store the MAC address.
- Page 25 Figure 4-9 network_utilities.c modified code In the Simple Socket Server, it uses GMII mode interface which we have to modify in the ins_tse_mac.c code shown in Figure 4-10. 327, the code “marvell_cfg_gmii(tse[iface].mi.base);” is included in order for the Around line Simple Socket Server to operate in GMII mode.
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Page 26: System Requirements
HSMC-NET DDR2 SO-DIMM (Bundled in the DE3) DE3 Board THCB-HFF adapter card (Not required for Cyclone III FPGA Starter Kit & HSMC-NET Demo) Standard Cat 5 UTP (unshielded twisted pair) cable Gateway Router USB-Blaster cable Figure 4-11 shows how to setup hardware for the HSMC-NET Server demonstration. -
Page 27: Demo Operation
Figure 4-11 The hardware setup for the HSMC-NET server demonstration Note: A THCB-HFF adapter card is used to establish connection with DE3 and HSMC-NET daughter board This section describes the procedures of running the demonstration FPGA Configuration Demonstration Setup, File Locations, and Instructions ... - Page 28 Altera. Confirm the THCB-HFF adaptor is connected to the DE3 HSTC connector before connecting the HSMC-NET daughter board Power on the DE3 board, with the USB cable connected to the USB Blaster port as well as connecting the Ethernet Cable from the Gateway device to the Ethernet Transceiver ...
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Page 29: Overview
LEDs (D0-D3) to toggle on or off on the DE3 host board. Observe the LED indications on the HSMC-NET daughter board showing what speed is connected, as well as the LEDs (D4-D7) blinking sequence is a lot faster connected to 1000Mbps compared to 100Mbps ... -
Page 30: Nios Program
Figure 4-14 shows the MAC interface options and supported media types for the HSMC-NET board. It supports copper media interface which is connected to an RJ-45 connector though magnetic supporting physical media for 1000BASE-T, 100BASE-TX, and 10BASE-T. Once the link is established an IP address is assigned to the Ethernet device along with the port number. - Page 31 Figure 4-15 Nios Program Software Architecture Figure 4-15 shows the software architecture of the Nios Program for the simple socket server. The top block containing the Nios II processor and the necessary hardware to be implemented into the DE3 host board. The software device drivers contain the necessary device drivers needed for the Ethernet and other hardware components to function.
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Page 32: Chapter 5 Appendix
MAY 9 , 2009 Initial Version October 12,2010 Modify picture description We will be continuing providing interesting examples and labs on our HSMC-NET Webpage. Please visit www.altera.com or hsmcnet.terasic.com for more information. Copyright © 2010 Terasic Technologies. All rights reserved.
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