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Summary of Contents for Sundance Spas PXIe-700
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PXIe-700 FPGA BOARD User Guide PROPRIETARY NOTICE: This document is the property of, and contains proprietary information of Sundance DSP Inc. The document is delivered on condition that it is used exclusively to evaluate the technical contents and pricing therein, it shall not be disclosed, duplicated or reproduced in whole or in part...
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Dec 10 , 2017 Added J5 pinout Stephen Malchi Jan 21 , 2018 PXIe-700 User Guide Rev. 1.7 Sundance Digital Signal Processing Inc. 4790 Caughlin Parkway 233, Reno, NV 89519-0907, U.S.A. Tel: +1 (775) 827-3103, Fax: +1 (775) 827-3664, email: sales@sundancedsp.com www.sundancedsp.com...
NTRODUCTION PXIe-700 is a powerful FPGA board in the ruggedized PXIe form factor. The board is based on the Xilinx Kintex-7 FPGA (XC7K410T-1FFG900C) with interface to 4 lanes of Gen2 PCIe, 2 GB of DDR3 memory attached to 2 banks. It includes an HPC FMC site and SFP+ interface. It fully complies with PXIe standard.
There is one switch, SW1, on the component side of the board. It has the following settings: Control Flash_25 Flash_24 Factory use Page 4 PXIe-700 User Guide Rev. 1.7 Sundance Digital Signal Processing Inc. 4790 Caughlin Parkway 233, Reno, NV 89519-0907, U.S.A. Tel: +1 (775) 827-3103, Fax: +1 (775) 827-3664, email: sales@sundancedsp.com www.sundancedsp.com...
The output frequencies can range from 43.75 MHz to 683.264 MHz see table 4 of CDCM61004 data sheet. The output frequency divider can be chosen using control pins. On PXIe-700 a 25 MHz clock input clock is used and for the output the control pins are set using 0 ohm resistors R187 –...
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214443 from ERNI backplane connector. This is used to provide PXI control signals. Note: Please see appendix for pinout. Page 6 PXIe-700 User Guide Rev. 1.7 Sundance Digital Signal Processing Inc. 4790 Caughlin Parkway 233, Reno, NV 89519-0907, U.S.A. Tel: +1 (775) 827-3103, Fax: +1 (775) 827-3664, email: sales@sundancedsp.com...
3.1 Carrier/Motherboard PXIe-700 provides 4 PCIe lanes on J2 PXI hybrid connector, so to establish this host interface a suitable PXI Express chassis conforming to the latest PXI Express specification which can accept PXI Express boards must be used.
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EEPROM is read the user can enable VADJ with right voltage using VADJ_SEL pins and VADJ_EN pin as described in the table above. Page 8 PXIe-700 User Guide Rev. 1.7 Sundance Digital Signal Processing Inc. 4790 Caughlin Parkway 233, Reno, NV 89519-0907, U.S.A.
Select PC28F00AP30T x16 BPI as your flash device and use .mcs and .prm files to burn the flash. Page 9 PXIe-700 User Guide Rev. 1.7 Sundance Digital Signal Processing Inc. 4790 Caughlin Parkway 233, Reno, NV 89519-0907, U.S.A.
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7 series FPGAs configuration user guide UG470 https://www.xilinx.com/support/documentation/user_guides/ug470_7Series_Config.pdf Note: The multi-boot feature has not been tested as of now. Please refer to the above link. Page 10 PXIe-700 User Guide Rev. 1.7 Sundance Digital Signal Processing Inc. 4790 Caughlin Parkway 233, Reno, NV 89519-0907, U.S.A.
Sundance DSP on the support forum https://www.sundancedsp.com/forum/ or write to support@sundancedsp.com Page 11 PXIe-700 User Guide Rev. 1.7 Sundance Digital Signal Processing Inc. 4790 Caughlin Parkway 233, Reno, NV 89519-0907, U.S.A. Tel: +1 (775) 827-3103, Fax: +1 (775) 827-3664, email: sales@sundancedsp.com...
1PETP4 1PETN4 1PERP4 1PERN4 1PETP7 1PETN7 1PERP7 1PERN7 Table 5 - PXIe-700 J2 Pinout 214443 from ERNI backplane connector. This is used to provide PXI control signals. Note: These signals are connected to 1.8v Bank FPGA_PIN FPGA_PIN FPGA_PIN AB17 AC19...
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Do you have a question about the PXIe-700 and is the answer not in the manual?
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