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PXIe-700 FPGA BOARD
User Guide
PROPRIETARY NOTICE: This document is the property of, and contains proprietary information of
Sundance DSP Inc. The document is delivered on condition that it is used exclusively to evaluate the
technical contents and pricing therein, it shall not be disclosed, duplicated or reproduced in whole or in part
without prior written consent of Sundance DSP Inc.

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  • Page 1 PXIe-700 FPGA BOARD User Guide PROPRIETARY NOTICE: This document is the property of, and contains proprietary information of Sundance DSP Inc. The document is delivered on condition that it is used exclusively to evaluate the technical contents and pricing therein, it shall not be disclosed, duplicated or reproduced in whole or in part...
  • Page 2 Dec 10 , 2017 Added J5 pinout Stephen Malchi Jan 21 , 2018 PXIe-700 User Guide Rev. 1.7 Sundance Digital Signal Processing Inc. 4790 Caughlin Parkway 233, Reno, NV 89519-0907, U.S.A. Tel: +1 (775) 827-3103, Fax: +1 (775) 827-3664, email: sales@sundancedsp.com www.sundancedsp.com...
  • Page 3: Table Of Contents

    Table of Contents Introduction ..........................1 Hardware features ......................1 Board Description ........................2 PXIe-700 Block Diagram and Pictures ................2 BPI FLASH Memory ......................3 Xilinx FPGA ........................3 Memory ..........................3 GTX (High Speed Transceivers) ..................3 HPC FMC ......................... 4 LEDs ..........................
  • Page 4 Table 3 - Switch (SW1) ........................5 Table 4 - VADJ Select and Enable pins ..................7 Table 5 - PXIe-700 J2 Pinout ....................... 13 Table 6 - PXIe-700 J2 pinout ......................13 Table 7 - HPC FMC Pinout ......................14 Table 8 - SFP+ Pinout ........................
  • Page 5: Introduction

    NTRODUCTION PXIe-700 is a powerful FPGA board in the ruggedized PXIe form factor. The board is based on the Xilinx Kintex-7 FPGA (XC7K410T-1FFG900C) with interface to 4 lanes of Gen2 PCIe, 2 GB of DDR3 memory attached to 2 banks. It includes an HPC FMC site and SFP+ interface. It fully complies with PXIe standard.
  • Page 6: Board Description

    OARD ESCRIPTION 2.1 PXIe-700 Block Diagram and Pictures The following diagram shows the major blocks of PXIe-700: 8 GPIO 4 MMCX JTAG Reset In/Out DDR3 2 CLK input config 4LEDs 10 GTX Xilinx Kintex-7 FPGA Rear End J4, PXI 20 IO...
  • Page 7: Bpi Flash Memory

    PXIe (J2) PCIe FMC (J1) User SFP+ User Page 3 PXIe-700 User Guide Rev. 1.7 Sundance Digital Signal Processing Inc. 4790 Caughlin Parkway 233, Reno, NV 89519-0907, U.S.A. Tel: +1 (775) 827-3103, Fax: +1 (775) 827-3664, email: sales@sundancedsp.com www.sundancedsp.com © Sundance Digital Signal Processing Inc 2016.
  • Page 8: Hpc Fmc

    There is one switch, SW1, on the component side of the board. It has the following settings: Control Flash_25 Flash_24 Factory use Page 4 PXIe-700 User Guide Rev. 1.7 Sundance Digital Signal Processing Inc. 4790 Caughlin Parkway 233, Reno, NV 89519-0907, U.S.A. Tel: +1 (775) 827-3103, Fax: +1 (775) 827-3664, email: sales@sundancedsp.com www.sundancedsp.com...
  • Page 9: Clocks

    The output frequencies can range from 43.75 MHz to 683.264 MHz see table 4 of CDCM61004 data sheet. The output frequency divider can be chosen using control pins. On PXIe-700 a 25 MHz clock input clock is used and for the output the control pins are set using 0 ohm resistors R187 –...
  • Page 10 214443 from ERNI backplane connector. This is used to provide PXI control signals. Note: Please see appendix for pinout. Page 6 PXIe-700 User Guide Rev. 1.7 Sundance Digital Signal Processing Inc. 4790 Caughlin Parkway 233, Reno, NV 89519-0907, U.S.A. Tel: +1 (775) 827-3103, Fax: +1 (775) 827-3664, email: sales@sundancedsp.com...
  • Page 11: Operation

    3.1 Carrier/Motherboard PXIe-700 provides 4 PCIe lanes on J2 PXI hybrid connector, so to establish this host interface a suitable PXI Express chassis conforming to the latest PXI Express specification which can accept PXI Express boards must be used.
  • Page 12 EEPROM is read the user can enable VADJ with right voltage using VADJ_SEL pins and VADJ_EN pin as described in the table above. Page 8 PXIe-700 User Guide Rev. 1.7 Sundance Digital Signal Processing Inc. 4790 Caughlin Parkway 233, Reno, NV 89519-0907, U.S.A.
  • Page 13: Fpga Configuration

    Select PC28F00AP30T x16 BPI as your flash device and use .mcs and .prm files to burn the flash. Page 9 PXIe-700 User Guide Rev. 1.7 Sundance Digital Signal Processing Inc. 4790 Caughlin Parkway 233, Reno, NV 89519-0907, U.S.A.
  • Page 14 7 series FPGAs configuration user guide UG470 https://www.xilinx.com/support/documentation/user_guides/ug470_7Series_Config.pdf Note: The multi-boot feature has not been tested as of now. Please refer to the above link. Page 10 PXIe-700 User Guide Rev. 1.7 Sundance Digital Signal Processing Inc. 4790 Caughlin Parkway 233, Reno, NV 89519-0907, U.S.A.
  • Page 15: Application Development

    Sundance DSP on the support forum https://www.sundancedsp.com/forum/ or write to support@sundancedsp.com Page 11 PXIe-700 User Guide Rev. 1.7 Sundance Digital Signal Processing Inc. 4790 Caughlin Parkway 233, Reno, NV 89519-0907, U.S.A. Tel: +1 (775) 827-3103, Fax: +1 (775) 827-3664, email: sales@sundancedsp.com...
  • Page 16: Appendix

    1PERP3 1PERN3 1PERP5 1PERN5 1PERP6 1PERN6 Page 12 PXIe-700 User Guide Rev. 1.7 Sundance Digital Signal Processing Inc. 4790 Caughlin Parkway 233, Reno, NV 89519-0907, U.S.A. Tel: +1 (775) 827-3103, Fax: +1 (775) 827-3664, email: sales@sundancedsp.com www.sundancedsp.com © Sundance Digital Signal Processing Inc 2016.
  • Page 17: Table 5 - Pxie-700 J2 Pinout

    1PETP4 1PETN4 1PERP4 1PERN4 1PETP7 1PETN7 1PERP7 1PERN7 Table 5 - PXIe-700 J2 Pinout 214443 from ERNI backplane connector. This is used to provide PXI control signals. Note: These signals are connected to 1.8v Bank FPGA_PIN FPGA_PIN FPGA_PIN AB17 AC19...
  • Page 18: Hpc Fmc

    4.1.2 HPC FMC Table 7 - HPC FMC Pinout Page 14 PXIe-700 User Guide Rev. 1.7 Sundance Digital Signal Processing Inc. 4790 Caughlin Parkway 233, Reno, NV 89519-0907, U.S.A. Tel: +1 (775) 827-3103, Fax: +1 (775) 827-3664, email: sales@sundancedsp.com www.sundancedsp.com...
  • Page 19: Sfp

    MGTX_AUX_TX+ MGTX_AUX_TX- MGTX_AUX_RX+ MGTX_AUX_RX- Table 9 - MMCX Pinout Page 15 PXIe-700 User Guide Rev. 1.7 Sundance Digital Signal Processing Inc. 4790 Caughlin Parkway 233, Reno, NV 89519-0907, U.S.A. Tel: +1 (775) 827-3103, Fax: +1 (775) 827-3664, email: sales@sundancedsp.com www.sundancedsp.com...
  • Page 20: Leds

    AC10 CLK- AB10 AB13 AA13 AA10 Page 16 PXIe-700 User Guide Rev. 1.7 Sundance Digital Signal Processing Inc. 4790 Caughlin Parkway 233, Reno, NV 89519-0907, U.S.A. Tel: +1 (775) 827-3103, Fax: +1 (775) 827-3664, email: sales@sundancedsp.com www.sundancedsp.com © Sundance Digital Signal Processing Inc 2016.
  • Page 21 AA27 AA22 AB28 AA21 AA25 AC30 Page 17 PXIe-700 User Guide Rev. 1.7 Sundance Digital Signal Processing Inc. 4790 Caughlin Parkway 233, Reno, NV 89519-0907, U.S.A. Tel: +1 (775) 827-3103, Fax: +1 (775) 827-3664, email: sales@sundancedsp.com www.sundancedsp.com © Sundance Digital Signal Processing Inc 2016.
  • Page 22: Table 12 - Ddr3 Pinout

    DQ31 AK26 DQS3- AG28 Table 12 - DDR3 Pinout Page 18 PXIe-700 User Guide Rev. 1.7 Sundance Digital Signal Processing Inc. 4790 Caughlin Parkway 233, Reno, NV 89519-0907, U.S.A. Tel: +1 (775) 827-3103, Fax: +1 (775) 827-3664, email: sales@sundancedsp.com www.sundancedsp.com...
  • Page 23: J5 Header

    GPIO_4 GPIO_5 GPIO_6 GPIO_7 Table 13 - J5 Header Pinout Page 19 PXIe-700 User Guide Rev. 1.7 Sundance Digital Signal Processing Inc. 4790 Caughlin Parkway 233, Reno, NV 89519-0907, U.S.A. Tel: +1 (775) 827-3103, Fax: +1 (775) 827-3664, email: sales@sundancedsp.com www.sundancedsp.com...

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