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Maxim Integrated MAX3420E Programming Manual

Usb peripheral controller with spi interface
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USB Peripheral Controller with
Programming Guide
For more information on the MAX3420E, please visit http://www.maxim-ic.com/max3420e.
For more information on USB and Maxim's USB products, see http://www.maxim-ic.com/usb.
The Maxim logo is a registered trademark of Maxim Integrated Products, Inc.
The Dallas Semiconductor logo is a registered trademark of Dallas Semiconductor Corp.
Copyright 2005 Maxim Integrated Products, Inc. All rights reserved.
MAX3420E
SPI Interface
XI
V
CC
VL
D+
D-
VBCOMP
RES#
GND
XO
SCK
MOSI
MISO
SS#
INT
GPX
GPIN0
GPIN1
GPIN2
GPIN3
GPOUT0
GPOUT1
GPOUT2
GPOUT3
GND
Rev. Sept 28, 2005

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Summary of Contents for Maxim Integrated MAX3420E

  • Page 1 For more information on the MAX3420E, please visit http://www.maxim-ic.com/max3420e. For more information on USB and Maxim’s USB products, see http://www.maxim-ic.com/usb. The Maxim logo is a registered trademark of Maxim Integrated Products, Inc. The Dallas Semiconductor logo is a registered trademark of Dallas Semiconductor Corp.
  • Page 2 Register Map Bits are shown in normal font, registers are shown in italics. Each highlighted cell is a link to a page describing the register or bit. Use the browser left arrow to return to this page. The Index at the end of this document is also linked to the descriptive pages.

  • Page 3: Accessing The Max3420E Registers

    SPI master to set the ACKSTAT bit without doing a full SPI access. Note: The ACKSTAT bit tells the MAX3420E that the SPI master has finished servicing a USB Control transfer. This causes the MAX3420E to ACKnowledge the next Control transfer STATUS stage.
  • Page 4 Registers R0-R4 access internal FIFOS. After selecting the register number R0-R4 with the command byte, the SPI master loads or unloads consecutive FIFO bytes by repeating reads or writes during the SPI transfer. For example, to read 8 bytes from the SUDFIFO, the SPI master would perform the following steps: 1.
  • Page 5 ACKSTAT Meaning: Acknowledge the STATUS stage of a CONTROL transfer. Location: EPSTALLS.6 Set: The CPU sets this bit after it has finished servicing a CONTROL transfer request. This instructs the SIE to send the ACK handshake to the status stage of the current CONTROL transfer.
  • Page 6 BUSACTIE Meaning: Bus Active Interrupt Enable. Location: USBIEN.2 Set: The CPU sets this bit to enable the BUSACT IRQ (page 2). Clear: The CPU clears this bit to disable the BUSACT IRQ. POR: BUSACTIE=0 Chip Reset: BUSACTIE=0 Bus Reset: BUSACTIE=0 Pwr Down: Read-only Programming Notes:...
  • Page 7 BUSACTIRQ Meaning: Bus Active Interrupt Request. Location: USBIRQ.2 Set: The SIE sets this bit to indicate USB bus activity. An internal BUSACT signal is set when the SIE receives a SYNC field, and reset after 32 bit time of a J-state, or during a USB bus reset.
  • Page 8 CHIPRES Meaning: Chip Reset. Location: USBCTL.5 Set: The CPU sets this bit to reset the chip. Its effect is identical to driving the RES# pin low. Clear: The CPU clears this bit to take the chip out of reset. POR: CHIPRES=0 Chip Reset: No change Bus Reset:...
  • Page 9 Only a power-on reset clears the CONNECT bit. If, during operation, an external reset is applied to the MAX3420E via the INT pin, the CONNECT bit retains its state. This means that if a device is connected to USB (CONNECT=1) when the RES# is asserted, it remains connected...
  • Page 10 CTGEP1OUT Meaning: Clear Data Toggle for endpoint 1 OUT. Location: CLRTOGS.2 Set: The CPU sets this bit to clear the data toggle for EP1-OUT to the DATA0 state. Clear: The SIE automatically clears this bit. POR: CTGEP1OUT=0 Chip Reset: CTGEP1OUT=0 Bus Reset: CTGEP1OUT=0 Pwr Down:...
  • Page 11 CTGEP2IN Meaning: Clear Data Toggle for Endpoint 2 IN. Location: CLRTOGS.3 Set: The CPU sets this bit to clear the data toggle for EP2-IN to the DATA0 state. Clear: The SIE automatically clears this bit. POR: CTGEP2IN=0 Chip Reset: CTGEP2IN=0 Bus Reset: CTGEP2IN=0 Pwr Down:...
  • Page 12 CTGEP3IN Meaning: Clear Data Toggle for endpoint 3 IN. Location: CLRTOGS.4 Set: The CPU sets this bit to clear the data toggle for EP3-IN to the DATA0 state. Clear: The SIE automatically clears this bit. POR: CTGEP3IN=0 Chip Reset: CTGEP3IN=0 Bus Reset: CTGEP3IN=0 Pwr Down:...
  • Page 13 EP0BC Meaning: Endpoint 0 Byte Count Register. Since EP0 is a bi-directional endpoint, whereby both IN and OUT transfers share the same FIFO (EP0FIFO, page 10), the action of this register depends on the transfer direction. Location: EP0BC[6:0] Write (IN): For an IN transfer, the CPU writes the byte count to this register after loading the EP0FIFO with data.
  • Page 14 EP0FIFO Meaning: Endpoint 0 FIFO. This 64 byte FIFO is used for OUT and IN transfers to and from the bi-directional endpoint 0. Location: EP0FIFO[7:0] Write (IN): For an IN transfer, the CPU writes a series of bytes to this FIFO to fill it with IN data.
  • Page 15 EP0INAK Meaning: EP0-IN NAK. Location: PINCTL.5 Set: The SIE sets this bit when the EP0-IN endpoint receives an IN request and returns the NAK handshake. Clear: The CPU clears this bit by writing a 1 to it. POR: EP0IBN=0 Chip Reset: EP0IBN=0 Bus Reset: EP0IBN=0 Pwr Down:...
  • Page 16 EP1DISAB Meaning: Disable Endpoint 1-OUT. Location: CLRTOGS.5 Set: The CPU sets this bit to disable traffic to Endpoint 1-OUT. Clear: The CPU clears this bit to enable traffic to Endpoint 1-OUT. POR: EP1DISAB=0 Chip Reset: EP1DISAB=0 Bus Reset: EP1DISAB=0 Pwr Down: Read-only Programming Notes: A disabled endpoint does not respond to any traffic.
  • Page 17 EP1OUTBC Meaning: Endpoint 1-0UT Byte Count. Location: EP1OUTBC[6:0] Write: After successfully receiving an OUT transfer over Endpoint 1, the SIE ACKS the transfer, updates this register with the received byte count, and asserts the OUT1DAV interrupt request (page 51). Read: The CPU reads this register after receiving an OUT1DAV interrupt request to determine how many bytes to read from the EP1OUTFIFO (page 14).
  • Page 18 EP1OUTFIFO Meaning: Double-buffered 64 byte FIFO for Endpoint 1-OUT. Location: EP1OUTFIFO[7:0] Write: The SIE fills the OUT FIFO with bytes transmitted from the host to endpoint 1- OUT. After successfully receiving the OUT transfer, the SIE ACKS the transfer, updates the byte count register (page 13), and asserts the OUT1DAV interrupt request (page 51).
  • Page 19 EP2DISAB Meaning: Disable Endpoint 2. Location: CLRTOGS.6 Set: The CPU sets this bit to disable traffic to endpoint 2-IN. Clear: The CPU sets this bit to enable traffic to endpoint 2-IN. POR: EP2DISAB=0 Chip Reset: EP2DISAB=0 Bus Reset: EP2DISAB=0 Pwr Down: Read-only Programming Notes: A disabled endpoint does not respond to any traffic.
  • Page 20 EP2INAK Meaning: Endpoint 2-IN NAK Location: PINCTL.6 Set: The SIE sets this bit when the EP2-IN endpoint receives an IN request and the SIE returns the NAK handshake. Clear: The CPU clears this bit by writing a 1 to it. POR: EP2INAK=0 Chip Reset: EP2INAK=0...
  • Page 21 EP2INBC Meaning: Endpoint 2-IN Byte Count Register. Location: EP2INBC[6:0] Write: The CPU loads this register with the number of bytes it has loaded into the EP2INFIFO (page 18). This arms the endpoint for the next IN transfer. Read: The SIE sends the data in this FIFO as the response to an EP2-IN host request. POR: EP2INBC=0 Chip Reset: EP2INBC=0...
  • Page 22 EP2INFIFO Meaning: Endpoint 2-IN FIFO (double-buffered 64 byte FIFOS). Location: EP2INFIFO[7:0] Write: The CPU loads bytes into this FIFO in preparation for sending to the host. Read: The SIE sends these bytes over USB in response to an IN request to EP2-IN. POR: EP2INFIFO=0 Chip Reset: EP2INFIFO=0...
  • Page 23 EP3DISAB Meaning: Disable Endpoint 3. Location: CLRTOGS.7 Set: The CPU sets this bit to disable traffic to endpoint 3-IN. Clear: The CPU clears this bit to enable traffic to endpoint 3-IN. POR: EP3DISAB=0 Chip Reset: EP3DISAB=0 Bus Reset: EP3DISAB=0 Pwr Down: Read-only Programming Notes: A disabled endpoint does not respond to any traffic.
  • Page 24 EP3INAK Meaning: Endpoint 3-IN NAK Location: PINCTL.7 Set: The SIE sets this bit when the EP3-IN endpoint receives an IN request and the SIE returns the NAK handshake. Clear: The CPU clears this bit by writing a 1 to it. POR: EP3INAK=0 Chip Reset: EP3INAK=0...
  • Page 25 EP3INBC Meaning: Endpoint 3-IN Byte Count Register. Location: EP3INBC[6:0] Write: The CPU loads this register with the number of bytes it has previously loaded into the EP3INFIFO (page 22). This arms the endpoint for the next IN transfer. Read: The SIE sends the data in this FIFO as the response to an EP3-IN host request. POR: EP3INBC=0 Chip Reset: EP3INBC=0...
  • Page 26 EP3INFIFO Meaning: Endpoint 3-IN FIFO, a 64-byte FIFO. Location: EP3INFIFO[7:0] Write: The CPU loads bytes into this FIFO in preparation for sending to the host. Read: The SIE sends these bytes over USB in response to an IN request to EP3-IN. POR: EP3INFIFO=0 Chip Reset: EP3INFIFO=0...
  • Page 27 FDUPSPI Meaning: Full Duplex SPI port operation. Location: PINCTL.4 Set: The CPU sets this bit to operate the SPI port in full-duplex mode. Clear: The SIE clears this bit to operate the SPI port in half-duplex mode. POR: FDUPSPI=0 (half-duplex) Chip Reset: No change Bus Reset: No change...
  • Page 28 Following the command byte, the SPI master issues one or more groups of 8-SCLK clocks to clock byte data into or out of the MAX3420E. As long as CS# remains low, the register address clocked in with the command remains in effect. This ability to burst bytes is convenient when reading or writing the endpoint FIFOS.
  • Page 29 The scope traces below illustrate identical data transfers between a microprocessor and the MAX3420E. Figure 6 uses SPI mode (0,0) and Figure 7 uses SPI mode (1,1). The difference is the inactive level of the SCLK signal, low for mode (0,0) and high for mode (1,1). In both modes the MOSI and MISO data as sampled by the rising edge of SCLK is the same.
  • Page 30 FNADDR Meaning: The Function Address assigned to the USB peripheral by the host. Location: FNADDR[6:0] Set: The SIE updates this register after receiving the ACK handshake at the conclusion of a Set_Address request from the host Clear: The SIE clears this register during a chip reset or a USB bus reset. POR: FNADDR=0 Chip Reset: FNADDR=0...
  • Page 31 GPIN0 Meaning: General Purpose Input Pin 0. Location: IOPINS.4 Set: This pin indicates the state of the GPIN0 pin (referenced to V ). This pin is pulled high with a weak pullup resistor, so if nothing is connected to the pin it indicates logic 1.
  • Page 32 GPIN1 Meaning: General Purpose Input Pin 1. Location: IOPINS.5 Set: This pin indicates the state of the GPIN1 pin (referenced to V ). This pin is pulled high with a weak pullup resistor, so if nothing is connected to the pin it indicates logic 1.
  • Page 33 GPIN2 Meaning: General Purpose Input Pin 2. Location: IOPINS.6 Set: This pin indicates the state of the GPIN2 pin (referenced to V ). This pin is pulled high with a weak pullup resistor, so if nothing is connected to the pin it indicates logic 1.
  • Page 34 GPIN3 Meaning: General Purpose Input Pin 3. Location: IOPINS.7 Set: This pin indicates the state of the GPIN3 pin (referenced to V ). This pin is pulled high with a weak pullup resistor, so if nothing is connected to the pin it indicates logic 1.
  • Page 35 GPOUT0 Meaning: General Purpose Output Pin 0. Location: IOPINS.0 Set: The CPU sets this bit to set the GPOUT0 pin high (referenced toV ). The CPU can also read this bit. Reading the bit indicates the state of the output flipflop before the output buffer.
  • Page 36 GPOUT1 Meaning: General Purpose Output Pin 1. Location: IOPINS.1 Set: The CPU sets this bit to set the GPOUT1 pin high (referenced toV ). The CPU can also read this bit. Reading the bit indicates the state of the output flipflop before the output buffer.
  • Page 37 GPOUT2 Meaning: General Purpose Output Pin 2. Location: IOPINS.2 Set: The CPU sets this bit to set the GPOUT2 pin high (referenced toV ). The CPU can also read this bit. Reading the bit indicates the state of the output flipflop before the output buffer.
  • Page 38 GPOUT3 Meaning: General Purpose Output Pin 3. Location: IOPINS.3 Set: The CPU sets this bit to set the GPOUT3 pin high (referenced toV ). The CPU can also read this bit. Reading the bit indicates the state of the output flipflop before the output buffer.
  • Page 39 GPXA Meaning: The two bits GPXB:GPXA determine the output of the GPX pin. Location: PINCTL.0 Set: The CPU sets this bit. Clear: The CPU clears this bit. POR: GPXA=0 Chip Reset: No change Bus Reset: No change Pwr Down: Read-write Programming Notes: GPXB GPXA GPX Pin OPERATE (complement of internal POR)
  • Page 40 GPXB Meaning: The two bits GPXB:GPXA determine the output of the GPX pin. Location: PINCTL.1 Set: The CPU sets this bit. Clear: The CPU clears this bit. POR: GPXB=0 Chip Reset: No change Bus Reset: No change Pwr Down: Read-write Programming Notes: GPXB GPXA GPX Pin OPERATE (complement of internal POR)
  • Page 41 DPLUS data line while in low power mode (oscillator is off). The HOSCSTEN bit deals with a special case of item 3, when the MAX3420E is designed into a self-powered peripheral. Suppose a user plugs a self-powered peripheral which is in power-down mode into a PC that is turned off.
  • Page 42 Meaning: Interrupt Enable. Location: CPUCTL.0 Set: The CPU sets this bit to activate the INT output pin. The characteristics of the INT output pin are programmed by the INTLEVEL (page 45) and POSINT (page 54) bits. Clear: The CPU clears this bit to disable the INT output pin. When IE=0 the state of the INT# pin is inactive (open for level mode, high for negative edge, low for positive edge).
  • Page 43 IN0BAVIE Meaning: Endpoint 0 IN Buffer Available Interrupt Enable. Location: EPIEN.0 Set: The CPU sets this bit to enable the IN0BAV interrupt request (page 40). Clear: The CPU clears this bit to disable the IN0BAV interrupt request. POR: IN0BAVIE=0 Chip Reset: IN0BAVIE=0 Bus Reset: IN0BAVIE=0 Pwr Down:...
  • Page 44 IN0BAVIRQ Meaning: Endpoint 0 IN Buffer Available Interrupt Request. Location: EPIRQ.0 Set: The SIE sets this bit after receiving an IN token directed to Endpoint 0, sending the data in the EP0FIFO (page 10) and receiving the ACK handshake from the host.
  • Page 45 IN2BAVIE Meaning: Endpoint 2 IN Buffer Available Interrupt Enable. Location: EPIEN.3 Set: The CPU sets this bit to enable the IN2BAV interrupt request (page 42). Clear: The CPU clears this bit to disable the IN2BAV interrupt request. POR: IN2BAVIE=0 Chip Reset: IN2BAVIE=0 Bus Reset: IN2BAVIE=0 Pwr Down:...
  • Page 46 IN2BAVIRQ bit goes invalid and immediately goes valid again, just as if the first packet had already been sent and accepted by the host. The double buffering action also means that after the MAX3420E is reset, the IN2BAVIRQ bit remains set until the EP2INBC register is loaded twice.
  • Page 47 IN3BAVIE Meaning: Endpoint 3 IN Buffer Available Interrupt Enable. Location: EPIEN.4 Set: The CPU sets this bit to enable the IN3BAV interrupt request (page 44). Clear: The CPU clears this bit to disable the IN3BAV interrupt request. POR: IN3BAVIE=0 Chip Reset: IN3BAVIE=0 Bus Reset: IN3BAVIE=0 Pwr Down:...
  • Page 48 IN3BAVIRQ Meaning: EP3-IN Buffer Available Interrupt Request. Location: EPIRQ.4 Set: The SIE sets this bit after receiving an IN token directed to Endpoint 3, sending the data in the EP3INFIFO (page 22) and receiving the ACK handshake from the host. This indicates that the EP3INFIFO is again available for loading by the CPU.
  • Page 49 INTLEVEL Meaning: The INT output pin is level-active. Location: PINCTL.3 Set: The CPU sets this bit to make the INT output pin level sensitive. When INTLEVEL=1 the output pin is active low, open-drain. When INTLEVEL=1 the system must include a pullup resistor to VL. Clear: The CPU clears this bit to make the INT pin edge active.
  • Page 50 NOVBUSIE Meaning: No V Interrupt Enable. Location: USBIEN.5 Set: Enables the NOVBUS Interrupt Request (page 47). Clear: Disables the NOVBUS Interrupt Request. POR: NOVBUSIE=0 Chip Reset: NOVBUSIE=0 Bus Reset: NOVBUSIE=0 Pwr Down: Read-only Programming Notes: Because most of the Interrupt Enable bits are cleared during a USB bus reset, the initialization routine that turns on the interrupt enable bits should be called as part of servicing a USB bus reset.
  • Page 51 Chip Reset: NOVBUSIRQ=0 Bus Reset: NOVBUSIRQ=0 Pwr Down: Read-only Programming Notes: This IRQ bit provides an easy way for a self-powered device to determine that the USB peripheral implemented by the MAX3420E has just been disconnected from a USB host.
  • Page 52 OSCOKIE Meaning: Oscillator OK Interrupt Enable. Location: USBIEN.0 Set: The CPU sets this bit to enable the OSCOK Interupt Request (page 49). Clear: The CPU clears this bit to disable the OSCOK Interrupt Request. POR: OSCOKIE=0 Chip Reset: OSCOKIE=0 Bus Reset: OSCOKIE=0 Pwr Down: Read-only...
  • Page 53 OSCOKIRQ Meaning: Oscillator OK Interrupt Request. Location: USBIRQ.0 Set: An internal OSCOK bit indicates that the internal 12 MHz oscillator is stable and the chip is ready to operate. The SIE sets the OSCOKIRQ bit when the OSCOK signal makes a 0-1 transition, indicating that the chip is ready to operate. Clear: The CPU clears this bit by writing a “1”...
  • Page 54 OUT0DAVIE Meaning: Endpoint 0 OUT Data Available Interrupt Enable. Location: EPIEN.1 Set: The CPU sets this bit to enable the OUT0DAV interrupt request (page 53). Clear: The CPU clears this bit to disable the OUT0DAV interrupt request. POR: OUT0DAVIE=0 Chip Reset: OUT0DAVIE=0 Bus Reset: OUT0DAVIE=0 Pwr Down:...
  • Page 55 OUT0DAVIRQ Meaning: Endpoint 0 OUT Data Available Interrupt Request. Location: EPIRQ.1 Set: The SIE sets this bit when it has successfully received (and ACK’d) an OUT data packet to EP0. Clear: The CPU clears this bit by writing a 1 to it. This also arms the endpoint for another transfer.
  • Page 56 OUT1DAVIE Meaning: Endpoint 1 OUT Data Available Interrupt Enable. Location: EPIEN.2 Set: The CPU sets this bit to enable the OUT1DAV Interrupt Request (page 51). Clear: The CPU clears this bit to disable the OUT1DAV Interrupt Request. POR: OUT1DAVIE=0 Chip Reset: OUT1DAVIE=0 Bus Reset: OUT1DAVIE=0 Pwr Down:...
  • Page 57 OUT1DAVIRQ Meaning: Endpoint 1 OUT Data Available Interrupt Request. Location: EPIRQ.2 Set: The SIE sets this bit when it has successfully received (and ACK’d) an OUT data packet to EP1-OUT. Clear: The CPU clears this bit by writing a 1 to it. This also arms the endpoint for another transfer.
  • Page 58 POSINT Meaning: The INT output pin (if set for edge output) is positive-edge active. This bit takes effect only if INTLEVEL=0 (page 45). Location: PINCTL.2 Set: The CPU sets this bit to cause the INT pin to make a 0-1 transition whenever an interrupt requires service.
  • Page 59 Any wakeup routine should clear the PWRDOWN bit to ready it for the next 0-1 transition. The CPU normally puts the MAX3420E into its power-down mode by setting PWRDOWN=1 and HOSCSTEN=1 (page 37). When the CPU sets PWRDOWN=1, the SIE takes the following actions: •...
  • Page 60 RWUDNIE Meaning: Remote Wakeup Signaling Done Interrupt Enable. Location: USBIEN.1 Set: The CPU sets this bit to enable the RWUDN Interrupt Request (page 57). Clear: The CPU clears this bit to disable the RWUDN interrupt request. POR: RWUDNIE=0 Chip Reset: RWUDNIE=0 Bus Reset: RWUDNIE=0 Pwr Down:...
  • Page 61 RWUDNIRQ Meaning: Remote Wakeup Signaling Done Interrupt Request. Location: USBIRQ.1 Set: The SIE sets this bit at the end of RWU signaling (10 ms of a K-state). Clear: The CPU clears this bit by writing a “1” to it. POR: RWUDNIRQ=0 Chip Reset: RWUDNIRQ=0 Bus Reset:...
  • Page 62 The SPI master sets this bit to initiate USB Remote Wakeup signaling on the bus. When the SPI master sets SIGRWU=1 the MAX3420E waits for 5 milliseconds of a J-state, and then drives the bus with the K-state (D+ low, D- high) for 10 milliseconds. After the 10 millisecond interval, the MAX3420E stops driving the bus and asserts the RWUDNIRQ (page 57) interrupt bit.
  • Page 63 STLEP0IN Meaning: Return the STALL handshake in response to an IN request to endpoint 0. Location: EPSTALLS.0 Set: The CPU sets this bit to instruct the SIE to return the STALL handshake for an IN request directed to endpoint 0. Clear: The SIE clears this bit whenever a SETUP token arrives.
  • Page 64 STLEP0OUT Meaning: Return the STALL handshake in response to an OUT request to endpoint 0. Location: EPSTALLS.1 Set: The CPU sets this bit to instruct the SIE to return the STALL handshake for an OUT request directed to endpoint 0. Clear: The SIE clears this bit whenever a SETUP token arrives.
  • Page 65 STLEP1OUT Meaning: Stall EP1-OUT. Return the STALL handshake in response to an OUT request to endpoint 1. Location: EPSTALLS.2 Set: The CPU sets this bit to instruct the SIE to return the STALL handshake for an OUT request directed to endpoint 1. Clear: The CPU clears this bit to return EP1-OUT to normal ACK-NAK operation.
  • Page 66 STLEP2IN Meaning: Stall EP2-IN. Return the STALL handshake in response to an IN request to endpoint 2. Location: EPSTALLS.3 Set: The CPU sets this bit to instruct the SIE to return the STALL handshake for an IN request directed to endpoint 2. Clear: The CPU clears this bit to return EP2-IN to normal ACK-NAK operation.
  • Page 67 STLEP3IN Meaning: Return the STALL handshake in response to an IN request to endpoint 3. Location: EPSTALLS.4 Set: The CPU sets this bit to instruct the SIE to return the STALL handshake for an IN request directed to endpoint 3. Clear: The CPU clears this bit when it receives a Clear_Feature(Halt) request directed to EP3-IN.
  • Page 68 STLSTAT Meaning: Return the STALL handshake in response to the STATUS stage of a CONTROL transfer. Location: EPSTALLS.5 Set: The CPU sets this bit to send the STALL handshake as the response to the status stage of a CONTROL transfer. Until the CPU either acknowledges (ACKSTAT bit=1) or stalls (STLSTAT=1) the transfer, the SIE answers the status stage of the CONTROL transfer with the NAK handshake.
  • Page 69 SUDAVIE Meaning: SETUP Data Available Interrupt Enable. Location: EPIEN.5 Set: The CPU sets this bit to enable the SUDAV Interrupt Request (page 66). Clear: The SIE clears this bit to disable the SUDAV Interrupt Request. POR: SUDAVIE=0 Chip Reset: SUDAVIE=0 Bus Reset: SUDAVIE=0 Pwr Down:...
  • Page 70 SUDAVIRQ Meaning: SETUP Data Available Interrupt Request. Location: EPIRQ.5 Set: The SIE sets this bit after error-free reception of the eight setup data bytes in a CONTROL transfer. Clear: The CPU clears this bit by writing a “1” to it. POR: SUDAVIRQ=0 Chip Reset: SUDAVIRQ=0...
  • Page 71 No read or write Programming Notes: The MAX3420E provides this separate FIFO to avoid mixing data and command bytes in the EP0FIFO (page 10). This relieves the programmer of the task of figuring out the type of data in the FIFO—the EP0FIFO (page 10) always contains data, and the SUDFIFO always contains...
  • Page 72 SUSPIE Meaning: SUSPEND Interrupt Enable. Location: USBIEN.4 Set: The CPU sets this bit to enable the SUSPEND Interrupt Request (page 69). Clear: The CPU clears this bit to disable the SUSPEND Interrupt Request. POR: SUSPIE=0 Chip Reset: SUSPIE=0 Bus Reset: SUSPIE=0 Pwr Down: Read-only...
  • Page 73 The CPU clears this bit by writing a “1” to it. POR: SUSPIRQ=0 Chip Reset: SUSPIRQ=0 Bus Reset: SUSPIRQ=0 Pwr Down: Read-only Programming Notes: The CPU responds to this interrupt by shutting down system peripherals, and then putting the MAX3420E into a low power state (PWRDOWN=1, page 55).
  • Page 74 URESDNIE Meaning: USB Bus Reset Done Interrupt Enable. Location: USBIEN.7 Set: The CPU sets this bit to enable the URESDN IRQ (page 68). Clear: The CPU clears this bit to enable the URESDN IRQ. POR: URESDNIE=0 Chip Reset: URESDNIE=0 Bus Reset: No change Pwr Down: Read-only...
  • Page 75 URESDNIRQ Meaning: USB Bus Reset Done Interrupt Request. Location: USBIRQ.7 Set: The SIE sets this bit when it has detected the end of a USB bus reset. Clear: The CPU clears this bit by writing a “1” to it. POR: URESDNIRQ=0 Chip Reset: URESDNIRQ=0 Bus Reset:...
  • Page 76 URESIE Meaning: USB Reset Interrupt Enable. Location: USBIEN.3 Set: The CPU sets this bit to enable the USB Reset Interrupt Request (page 73). Clear: The CPU clears this bit to disable the USB Reset Interrupt Request. POR: URESIE=0 Chip Reset: URESIE=0 Bus Reset: No change Pwr Down:...
  • Page 77 URESIRQ Meaning: USB bus reset interrupt request. Location: USBIRQ.3 Set: The SIE sets this bit when it detects a USB bus reset (at least 2.5 usec of the SE0 bus state). Clear: The CPU clears this bit by writing a “1” to it. POR: URESIRQ=0 Chip Reset: URESIRQ=0...
  • Page 78 VBUSIE Meaning: Detect Interrupt Enable. Location: USBIEN.6 Set: The CPU sets this bit to enable the VBUS Interrupt Request (page 74). Clear: The CPU clears this bit to disable the VBUS Interrupt Request. POR: VBUSIE=0 Chip Reset: VBUSIE=0 Bus Reset: VBUSIE=0 Pwr Down: Read-only...
  • Page 79 Chip Reset: VBUSIRQ=0 Bus Reset: VBUSIRQ=0 Pwr Down: Read-only Programming Notes: This IRQ bit provides an easy way for a self-powered device to determine that the USB peripheral implemented by the MAX3420E has just been connected to a USB host.
  • Page 80 VBGATE Meaning: Gate. Location: USBCTL.6 Set: The CPU sets this bit to make operation of the CONNECT bit (page 5) conditional on V being present on the V pin. Clear: The CPU clears this bit to make operation of the CONNECT bit independent of being valid.
  • Page 81 Index ACKSTAT ............................. 1 BUSACTIE ............................ 2 BUSACTIRQ..........................3 CHIPRES............................4 CONNECT ............................ 5 CTGEP1OUT ..........................6 CTGEP2IN ............................ 7 CTGEP3IN ............................ 8 EP0BC............................9 EP0FIFO............................10 EP0INAK............................. 11 EP1DISAB ........................... 12 EP1OUTBC ..........................13 EP1OUTFIFO ..........................14 EP2DISAB ........................... 15 EP2INAK.............................
  • Page 82 OSCOKIE............................ 48 OSCOKIRQ ..........................49 OUT0DAVIE..........................50 OUT0DAVIRQ..........................51 OUT1DAVIE..........................52 OUT1DAVIRQ..........................53 POSINT............................54 PWRDOWN ..........................55 RWUDNIE........................... 56 RWUDNIRQ ..........................57 SIGRWU............................58 STLEP0IN ........................... 59 STLEP0OUT ..........................60 STLEP1OUT ..........................61 STLEP2IN ........................... 62 STLEP3IN ........................... 63 STLSTAT ............................