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Summary of Contents for Microchip Technology Microsemi HDMI TX IP
- Page 1 UG0862 User Guide HDMI TX...
- Page 2 About Microsemi ©2019 Microsemi, a wholly owned Microsemi, a wholly owned subsidiary of Microchip Technology Inc. (Nasdaq: MCHP), offers a comprehensive portfolio of subsidiary of Microchip Technology Inc. All semiconductor and system solutions for aerospace & defense, communications, data center and industrial markets.
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Page 3: Table Of Contents
Contents 1 Revision History ........... . . 1 Revision 1.0 . - Page 4 Figures Figure 1 HDMI TX IP Block Diagram ............3 Figure 2 Creating SmartDesign Testbench .
- Page 5 Tables Table 1 Inputs and Outputs ............. . 4 Table 2 Configuration Parameters .
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Page 6: Revision History
Revision History Revision History The revision history describes the changes that were implemented in the document. The changes are listed by revision, starting with the most current publication. Revision 1.0 This is the first publication of this document. Microsemi Proprietary and Confidential UG0862 User Guide Revision 1.0... -
Page 7: Introduction
Introduction Introduction Microsemi’s High-Definition Multimedia Interface (HDMI) transmitter IP supports transmitting video data described in the HDMI standard specification. HDMI TX IP features are: • Supports HDMI 2.0 and HDMI 1.4 • Supports 1, 2, and 4 pixels per clock input •... -
Page 8: Hardware Implementation
Hardware Implementation Hardware Implementation The following figure illustrates the HDMI TX IP in 1 pixel mode for PolarFire devices: HDMI TX IP Block Diagram Figure 1 • SYS_CLK_I LANE_TX_CLK_R 10'h1F RESET_N_I LANE_CLK_TX_DATA[9:0] LANE_CLK_TXD[P,N] TMDS_R_O [9:0] LANE_R_TX_DATA[9:0] DATA_VALID_I TMDS_G_O [9:0] LANE_R_TXD[P,N] LANE_G_TX_DATA[9:0] H_SYNC_I TMDS_B_O [9:0] LANE_B_TX_DATA[9:0] LANE_G_TXD[P,N]... -
Page 9: Inputs And Outputs
Inputs and Outputs Inputs and Outputs Ports The following table describes the input and output ports of HDMI TX IP. Inputs and Outputs Table 1 • Signal Name Direction Width Description SYS_CLK_I Input 1 bit System clock, usually the same clock as the display controller RESET_N_I Input... -
Page 10: Figure 2 Creating Smartdesign Testbench
Inputs and Outputs Creating SmartDesign Testbench Figure 2 • Enter a name for the SmartDesign testbench, and click OK. Figure 3 • Naming SmartDesign Testbench SmartDesign testbench is created, and a canvas appears to the right of the Design Flow pane. In the Libero SoC Catalog (View >... -
Page 11: Figure 5 Parameter Configuration
Inputs and Outputs Parameter Configuration Figure 5 • Select all the ports. Right-click, and select Promote to Top Level, as shown in the following figure. Figure 6 • Promote to Top Level Click Generate Component from the SmartDesign toolbar, as shown in the following figure. Generate Component Figure 7 •... -
Page 12: Figure 8 Simulating Testbench
Inputs and Outputs Simulating Testbench Figure 8 • The ModelSim tool appears with the test bench file loaded on to it as shown in the following figure. ModelSim Tool with HDMI TX Testbench File Figure 9 • If the simulation is interrupted because of the runtime limit in the DO file, use the run -all command to complete the simulation. -
Page 13: Timing Diagrams
Inputs and Outputs Timing Diagrams The following timing diagram for HDMI TX IP shows video data and control data periods for 1 pixel per clock. Figure 10 • HDMI TX IP Timing Diagram of Video Data for 1 Pixel Per Clock The following diagram shows the 4 combinations of control data.
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