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Pleora Technologies iPort NTx-Pro Hardware Manual

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NTx-Pro
Hardware Guide

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Summary of Contents for Pleora Technologies iPort NTx-Pro

  • Page 1 NTx-Pro Hardware Guide...
  • Page 3 ...proven performance...
  • Page 4 These products are not intended for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Pleora Technologies Inc. (Pleora) customers using or selling these products for use in such applica- tions do so at their own risk and agree to indemnify Pleora for any damages resulting from such improper use or sale.

  • Page 5: Table Of Contents

    Contents NTx-Pro: iPORT .........................3 Introduction ..............................3 Model Numbers ...............................4 Summary of Features ..............................5 Related Documents ..............................6 Connector Summary: OEM: NTx-Pro ..................7 NTx-Pro Connectors and LEDs ..........................8 Overview: Connector Names ....................9 User Circuitry Connectors ........................... 9 Ethernet Connector ...............................10 JTAG Connector ..............................10 Power Connector ..............................10 Connector: JTAG: 2x5-pin Header..................
  • Page 6 Serial Port: Standard-Bandwidth: UART................37 Signals ..............................37 Timing for UART ............................37 Power Requirements.......................39 Signal Names ............................39 Input Power Signals ..............................39 Output Power Signals ............................40 Power Consumption ..............................41 User Circuitry Power .............................41 Status LEDs: Overview ......................43 Location of LEDs ............................43 FPGA Configuration LED ..........................

  • Page 7: Ntx-Pro: Iport

    NTx-Pro: iPORT Introduction Pleora’s iPORT NTx-Pro IP engine is a compact, low-power video transmitter that gives OEMs and systems integrators a fast, low-risk way to add real-time video connectivity to almost any system or camera. It is ideal for performance-oriented applications in the military, medical, manufacturing, and security sectors.

  • Page 8: Model Numbers

    4 NTx-Pro: iPORT Model Numbers The iPORT NTx-Pro IP engine is offered with the model numbers shown in the illustration below. NTx-Pro Product Code PT 01 - PB 0 IP 01 - 32 Pleora Technologies Speed Protocol 01: 1 GigE...

  • Page 9: Summary Of Features

    RJ45 with embedded magnetics FPGA External Static Memory 16-bit wide 2 MB SRAM Clock Generator Included Boundary Scan Chain FPGA and PHY Frame Grabber Number of Data Channels 1 (Std) Up to 4 (Opt) Copyright © 2010 Pleora Technologies Inc.

  • Page 10: Related Documents

    NRE or other charges may apply. Contact Pleora Technologies. d. Default values in the XML file. Other values are possible. Related Documents The NTx-Pro Hardware Guide is complemented by these Pleora Technologies publications: • iPORT Programmable Logic Controller Reference Guide •...

  • Page 11: Connector Summary: Oem: Ntx-Pro

    NOTE! The NTx-Pro IP Engine does not require a crossover cable to adjust the pinout signals to communicate through a switch, or to a host PC. It adjusts the data rate automatically to transmit at 10 Mbps, 100 Mbps, or 1 Gbps. Copyright © 2010 Pleora Technologies Inc.

  • Page 12: Ntx-Pro Connectors And Leds

    The figure below illustrates the location of the all connectors and LEDs for the NTx-Pro board. User Circuitry Connectors (J4/J5) JTAG Connector (J2) Ethernet Connector (J1) Network Connection Speed LED (J1) Power Connector (J3) Network Activity LED (J1) Power and Firmware Status LEDs (D2) Copyright © 2010 Pleora Technologies Inc.

  • Page 13: Overview: Connector Names

    Connector J4 has these features and functions: • 2.5V supply • 2.5V GPIOs • 2 FPGA clock buffer inputs • Serial communication interfaces • VIN filtered power pins • Ground pins • 3.3V supply Copyright © 2010 Pleora Technologies Inc.

  • Page 14: Ethernet Connector

    FPGA, debugging purposes and boundary scan tests. Power Connector The power connector receives 5V to 16V of unfiltered DC input. NOTE! The NTx-Pro power circuitry is most efficient with 5V unfiltered DC input. Copyright © 2010 Pleora Technologies Inc.

  • Page 15: Connector: Jtag: 2X5-Pin Header

    5-pin double row header; 0.050”/1.27 mm pitch Samtec CLP-105-02-G-D JTAG Header Layout The JTAG header layout indicating the JTAG receptacle pin orientation is shown in the figure below. NTx-Pro Board (Top) RJ45 Connector JTAG Header 10-Pin Receptacle FPC Connectors Copyright © 2010 Pleora Technologies Inc.

  • Page 16: Connector: J2 Jtag Connector - Detail

    Test Clock JTAG Test Clock Input; 1 Kohm Pull-down resistor. Synchro- nizes with TDI, TDO and TMS UART_TX Tx Data UART Reserved UART_RX Rx Data UART Reserved Ground Ground 3.3V Power Power Output Copyright © 2010 Pleora Technologies Inc.

  • Page 17: Connector: Ethernet

    1 Gbps. It adjusts the pinout to communicate through a switch, or to a host PC without the need for crossover cables. You can use either Category 5e cables or the superior Category 6/6a cables. Pleora Technologies Inc. recommends unshielded twisted-pair (UTP) cables. Note that at greater distances, the voltage differen- tial between the grounds at either end of the cable makes shielded cable behave like an antenna, which can cause noise or EMI issues.

  • Page 18: Pinouts

    14 Connector: Ethernet Pinouts The pinouts on the NTx-Pro IP Engine conform to both Ethernet and RJ45 Standards. Copyright © 2010 Pleora Technologies Inc.

  • Page 19: Connector: Power

    2-pin header (with pins) Tyco Electronics 644874-2 Mating Components Part Description Part Number 2-pin shell (with sockets) Molex 22-01-3027 Crimp sockets (quantity 2) Molex 08550102 Pinouts Connector Pinouts Signal Name Pinouts when looking at IP Engine Copyright © 2010 Pleora Technologies Inc.
  • Page 20 16 Connector: Power Copyright © 2010 Pleora Technologies Inc.

  • Page 21: Connector: User Circuitry: 2X 50-Pin Ffc/Fpc

    NOTE! Compatible with Hirose connector FH12-50S-0.5SV to MIL-STD-810F, Method 514.6: 5- 2000 Hz. 7.7 gs. Other types of FFC cable from other vendors are acceptable; in this case, Pleora Technologies recommends mechanical tests to ensure compatibility. Copyright © 2010 Pleora Technologies Inc.

  • Page 22: X 50-Pin Ffc/Fpc Layout

    2.5V on the NTx-Pro board. IO33_PLL_P0 Output Camera Control 3 IO33_PLL_N0 Output Camera Control 4 Ground Ground IO33_0_(B27N) PIXEL_DATA0 Input Pixel data IO33_1_(B27P) PIXEL_DATA1 Input Pixel data IO33_2_(B23N) PIXEL_DATA2 Input Pixel data Copyright © 2010 Pleora Technologies Inc.
  • Page 23 IO33_CLKBUF0 Reserved High impedance Hi-Z IO33_CLKBUF1 PIXEL_CLK Input Pixel bus input clock FPGA_SEL0 FPGA Select Pin 0 Input FPGA load selection Pin 0 FPGA_SEL1 FPGA Select Pin 1 Input FPGA load selection Pin 1 Copyright © 2010 Pleora Technologies Inc.

  • Page 24: Connector Names: J4 Connector - Detail

    Bulk interface 0 UART and USRT output or I2C SDA. IO25_18 BULK0_CLK Input/Output Bulk Interface 0 USRT output clock when the inter- face is used in USRT mode. I2C SCL when used in I2C mode. Copyright © 2010 Pleora Technologies Inc.
  • Page 25 High impedance Hi-Z Ground Ground IO25_32 Reserved High impedance Hi-Z IO25_CLKBUF0 Reserved High impedance Hi-Z IO25_CLKBUF1 Reserved High impedance Hi-Z 3.3V Power Power Output 3.3V from the NTx-Pro 3.3V Power Power Output 3.3V from the NTx-Pro Copyright © 2010 Pleora Technologies Inc.

  • Page 26: Signal Names: (J5) 50-Pin Ffc/Fpc - Detail

    Other combinations are reserved for future use. 4, 9, 18, Ground Ground 27, 36, 45 SYSTEM_CLK Output 2.5V 2.5V 33.33300 MHz +/- 50ppm system clock generator. IO33_PLL_P0 Output 3.3V Camera Control 3 IO33_PLL_N0 Output 3.3V Camera Control 4 Copyright © 2010 Pleora Technologies Inc.

  • Page 27: Signal Names: (J4) 50-Pin Ffc/Fpc - Detail

    37-44, IO25_CLKBUF0 Hi-Z High Impedance Reserved IO25_CLKBUF1 Hi-Z High Impedance Reserved 3.3V 49, 50 Power 3.3V 3.3V power output to customer Output circuitry. The current limitation is 0.4A for each pin; 1.0A in total. Copyright © 2010 Pleora Technologies Inc.

  • Page 28: Fpga Selection Pins

    1. R1, R2, internal pull -ups; 8KΩ to 61KΩ (35KΩ typical). 2. R3, R4, on-board pull -downs , 470 KΩ. 3. Option 2: Short jumpers J 1/J2 to select the backup load . 4. Use for pull-up resistors R value 1KΩ or less. Copyright © 2010 Pleora Technologies Inc.

  • Page 29: Mechanical: Oem: Ntx-Pro

    Mechanical: OEM: NTx-Pro The mechanical layout and dimensions of the NTx-Pro IP Engine are presented below. Isometric View Copyright © 2010 Pleora Technologies Inc.
  • Page 30 26 Mechanical: OEM: NTx-Pro Top View Side View Copyright © 2010 Pleora Technologies Inc.
  • Page 31 Top view Side view Top view Copyright © 2010 Pleora Technologies Inc.

  • Page 32: Notes For The Circuit Board

    The 3D draft in IGES format is available on Pleora’s Resource Center. The power connector; large transient voltage suppressor (TVS); and, the large capacitor (within the ASI-Pro and vDisplay enclosures) on VIN, are not shown. Copyright © 2010 Pleora Technologies Inc.

  • Page 33: Pixel Bus Timing

    The output of the camera must match the format of the NTx-Pro IP Engine. Select a case for your application and then refer to, “Timing Values for All Cases” on page 31. The stated timing restrictions are minimum values. Copyright © 2010 Pleora Technologies Inc.

  • Page 34: Case 1: Fval And Lval Are Level-Sensitive

    Case 3: FVAL is Edge-sensitive and LVAL is Level-sensitive FV2FV FI2FV FV2DV FV2FI FVAL LV2LI LVAL FV2LV LLI2DV LI2LV DVAL (N-1, (N-1, PIXEL_DATAx (0,0) (1,0) (N,0) (0,1) (1,1) (N,M) (0,0) (1,0) LI2DV Don’t Care Window Size = N x M LV2DV DI2LI Copyright © 2010 Pleora Technologies Inc.

  • Page 35: Timing Values For All Cases

    10/12-bit, 2-tap, unpacked, and RGB unpacked. Subtract up to 7 cycles if the image size is a multiple of 32 bytes. NOTE! The timing values stated in the table above are minimum values only. Copyright © 2010 Pleora Technologies Inc.
  • Page 36 32 Pixel Bus Timing Copyright © 2010 Pleora Technologies Inc.

  • Page 37: Serial Port: Bulk Interface: Uart, Usrt, And I2C

    8.333 4.167 2.083 1.042 1920 0.521 3840 0.260 7680 0.130 a. To obtain the exact frequency, divide the 33.333 MHz clock speed by one of: 2, 4, 8, 16, 32, 64, 128, or 256. Copyright © 2010 Pleora Technologies Inc.
  • Page 38 SCK to TXD delay -5 ns 5 ns RXD setup time 16 ns 44 ns RXD hold time 0 ns 44 ns a. Clock frequency of 16.667 MHz b. Clock frequency of 1.042 MHz Copyright © 2010 Pleora Technologies Inc.

  • Page 39: Bulk Interface: I2C

    A - not acknowledge (SDA high) R - read (SDA high) S - START Condition - from master to slave P - STOP Condition - from slave to master Sr - STOP/START or Repeated START Condition n - BufferSize Copyright © 2010 Pleora Technologies Inc.
  • Page 40 36 Serial Port: Bulk Interface: UART, USRT, and I2C Copyright © 2010 Pleora Technologies Inc.

  • Page 41: Serial Port: Standard-Bandwidth: Uart

    UART (bps) (us) 8170 122.4 9600 113.2 14400 69.4 19200 52.1 28800 34.7 38400 26.0 57600 17.4 115200 a. Baud rate is based on the inverse of the data period, or t =1/BR UART Copyright © 2010 Pleora Technologies Inc.
  • Page 42 38 Serial Port: Standard-Bandwidth: UART Copyright © 2010 Pleora Technologies Inc.

  • Page 43: Power Requirements

    PWR signal. A resident common mode filter allows the input to be unfiltered, directly from a switching wall plug power supply. NOTE! If you implement this option, do not use VIN as a supply. Ground Ground for PWR Copyright © 2010 Pleora Technologies Inc.

  • Page 44: Output Power Signals

    J4 connector. Current per pin is 0.4A. Maximum current sink by user circuitry through all VIN pins must not exceed 0.9A. Ground - - - 0 volts relative to other voltages on the NTx-Pro. Copyright © 2010 Pleora Technologies Inc.

  • Page 45: Power Consumption

    VIN (0.8A). If the NTx-Pro is powered with the J3 Molex (PWR), there are no requirements beyond those listed in the table on Page 38 (“Output Power Signals”). Copyright © 2010 Pleora Technologies Inc.
  • Page 46 42 Power Requirements Copyright © 2010 Pleora Technologies Inc.

  • Page 47: Status Leds: Overview

    The locations of the status LEDs on the NTx-Pro board are shown in the figure below. NTx-Pro Board Network Connection Speed LED (J1) Network Activity LED (J1) Power and Firmware Status LEDs (D2) FPGA Configuration LED Power/Firmware LED Action FPGA not configured. FPGA is configured. Green Copyright © 2010 Pleora Technologies Inc.

  • Page 48: Network Activity Led

    No connection, 10 Mbps connection, or 100 Mbps con- nection. Green on 1 Gbps connection. FPGA Programming LED FPGA Programming Action Power is off. Green on Power is on. Green on/Orange on Power is on and the backup load is running. Copyright © 2010 Pleora Technologies Inc.

  • Page 49: Camera Link Pixel Bus Definitions

    For all A/B, or R/G/B signals, 0 denotes the least significant bit (e.g. A0) on the IP Engine. If your camera uses 0 as the MSB, you must reverse the cabling. Port A denotes the primary image; port B, the secondary. Use port B as the second tap for two-tap cameras. Copyright © 2010 Pleora Technologies Inc.

  • Page 50: Yuv Color Bit Assignments

    46 Camera Link Pixel Bus Definitions YUV Color Bit Assignments You can inquire about YUV Color Bit Assignments for the NTx-Pro IP Engine by contacting Pleora Technologies Inc. for details. Copyright © 2010 Pleora Technologies Inc.
  • Page 51 Copyright © 2010 Pleora Technologies Inc.
  • Page 52 48 Camera Link Pixel Bus Definitions Copyright © 2010 Pleora Technologies Inc.

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