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PLX Technology PCI 6152 Series Data Book

Pci-to-pci bridge
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PCI 6152 (HB1-SE)
PCI-to-PCI Bridge
Data Book

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  • Page 1 PCI 6152 (HB1-SE) PCI-to-PCI Bridge Data Book...
  • Page 3 PCI 6152 (HB1-SE) PCI-to-PCI Bridge Data Book Version 2.0 May 2003 Website: http://www.plxtech.com Technical Support: http://www.plxtech.com/support Phone: 408 774-9060 800 759-3735 Fax: 408 774-2169...
  • Page 4 © 2003 PLX Technology, Inc. All rights reserved. PLX Technology, Inc. retains the right to make changes to this product at any time, without notice. Products may have minor variations to this publication, known as errata. PLX assumes no liability whatsoever, including infringement of any patent or copyright, for sale and use of PLX products.
  • Page 5 Supports 3.3V PCI with 5V tolerant I/O GPIO Interface PCI 6152 Primary PCI Bus Secondary PCI Bus PCI-to-PCI Bridge Up to Four Master PCI Devices PCI 6152 Data Book v2.0     2003 PLX Technology, Inc. All rights reserved.

  • Page 6: History

    Removed secondary clock information from bullet 2 and S_RST# bullets (4 and 6 from Section 13.2 Updated Master on primary and secondary response in Section 14 Removed synchronous design information from Section 16 PCI 6152 Data Book v2.0     2003 PLX Technology, Inc. All rights reserved.

  • Page 7: Table Of Contents

    ................. 57 ADDRESS DECODING ........................58 ..........................58 DDRESS ANGES I/O A ........................58 DDRESS ECODING 9.2.1 I/O Base and Limit Address Registers ..................59 PCI 6152 Data Book v2.0     2003 PLX Technology, Inc. All rights reserved.
  • Page 8 ENERAL URPOSE NTERFACE 17.3 ........................80 ITAL RODUCT PCI POWER MANAGEMENT......................81 HOT SWAP ............................82 19.1 ........................82 NSERTION 19.2 ........................82 XTRACTION PCI 6152 Data Book v2.0     2003 PLX Technology, Inc. All rights reserved.
  • Page 9 EMORY RITE TRANSACTION FOLLOWED ..........110 ECONDARY TO RIMARY EMORY RITE TRANSACTION 7 : S ............111 IGURE ECONDARY TO RIMARY EMORY RITE TRANSACTION PCI 6152 Data Book v2.0     2003 PLX Technology, Inc. All rights reserved.
  • Page 10 PCI 6152 Data Book v2.0     2003 PLX Technology, Inc. All rights reserved.

  • Page 11: Register Index

    Subsystem Vendor ID ............... 44 Interrupt Pin Register..............32 Vendor ID Register..............26 Memory Base Register ..............31 VPD Data Register..............39 Memory Limit Register...............31 VPD Register ................39 PCI 6152 Data Book v2.0     2003 PLX Technology, Inc. All rights reserved.

  • Page 12: Introduction

    160-pin PQFP Mechanical specifications for each package type can be found in the appendix. * Refer to Appendix A for detailed information about this part. PCI 6152 Data Book v2.0     2003 PLX Technology, Inc. All rights reserved.

  • Page 13: Pin Diagram

    P_PAR PCI 6152 S_RST_L P_SERR_L S_SERR_L P_PERR_L S_PERR_L P_IDSEL S_CLKRUN P_CLKRUN PVIO ENUM_L SVIO PLUG L_STAT BCCP_EN EJECT Misc. GPIO[3:0] EEPCLK EEPDATA GOZ_L NAND_O PCI 6152 Data Book v2.0     2003 PLX Technology, Inc. All rights reserved.

  • Page 14: Signal Definition

    The deassertion of P_FRAME_L indicates the final data phase requested by the initiator. Before being three-stated, it is driven to a deasserted state for one cycle. PCI 6152 Data Book v2.0     2003 PLX Technology, Inc. All rights reserved.
  • Page 15 Primary Grant: When asserted, PCI 6152 can access the primary bus. During idle and P_GNT_L asserted, PCI 6152 will drive P_AD, P_CBE and P_PAR to valid logic level. PCI 6152 Data Book v2.0     2003 PLX Technology, Inc. All rights reserved.

  • Page 16: Secondary Bus Interface Signals

    S_SERR_L Secondary System Error: Can be driven LOW by any device to indicate a system error condition. PCI 6152 Data Book v2.0     2003 PLX Technology, Inc. All rights reserved.

  • Page 17: Clock Signals

    L_STAT Hot Swap LED: Indicates the status of software connection process. Signal should be pulled down to ground if not used. PCI 6152 Data Book v2.0     2003 PLX Technology, Inc. All rights reserved.

  • Page 18: Miscellaneous Signals

    Nand tree diagnostic output. This signal is dedicated to the diagnostic Nand tree. The GOZ_L signal should be asserted when the Nand tree mechanism is used. 5.7 Power Signals Name Type Description +3.3V Ground PCI 6152 Data Book v2.0     2003 PLX Technology, Inc. All rights reserved.

  • Page 19: Pin Assignment

    GPIO1 PGNT_L PAD30 PAD27 PAD24 PIDSEL SREQ2_L SREQ3_L SGNT1_L SRST_L SCLK0 SCLK3 GOZ_L RST_L PVIO PAD31 PAD28 PAD25 GPIO2 CBE3_L PCI 6152 Top View PCI 6152 Data Book v2.0     2003 PLX Technology, Inc. All rights reserved.

  • Page 20: Pci 6152 Pinout Tables

    S_AD[14] EEPCLK S_AD[12] P_STOP_L S_AD[09] S_AD[21] S_AD[07] S_AD[22] S_AD[02] S_AD[23] P_AD[00] P_AD[02] P_AD[05] P_IRDY_L P_TRDY_L P_AD[09] P_DEVSEL_L EJECT S_CBE_L[3] S_TRDY_L S_AD[24] S_DEVSEL_L S_AD[25] S_STOP_L PCI 6152 Data Book v2.0     2003 PLX Technology, Inc. All rights reserved.
  • Page 21 S_REQ_L[3] S_GNT_L[1] P_AD[22] S_RST_L P_AD[21] S_CLK_O[0] P_AD[20] S_CLK_O[3] S_AD[31] GOZ_L S_REQ_L[0] RST_L P_VIO S_GNT_L[2] P_AD[31] S_CLK P_AD[28] S_CLK_O[1] P_AD[25] S_CLK_O[4] GPIO[2] P_CLK P_CBE_L[3] P_REQ_L PCI 6152 Data Book v2.0     2003 PLX Technology, Inc. All rights reserved.

  • Page 22: Pin Assignment Sorted By Signal Name

    P_AD[25] S_AD[24] P_AD[26] S_AD[25] P_AD[27] S_AD[26] P_AD[28] S_AD[27] P_AD[29] S_AD[28] P_AD[30] S_AD[29] P_AD[31] S_AD[30] P_CBE_L[0] S_AD[31] P_CBE_L[1] S_CBE_L[0] P_CBE_L[2] S_CBE_L[1] P_CBE_L[3] S_CBE_L[2] P_CLK S_CBE_L[3] PCI 6152 Data Book v2.0     2003 PLX Technology, Inc. All rights reserved.
  • Page 23 S_CLK_O[0] S_CLK_O[1] S_CLK_O[2] S_CLK_O[3] S_CLK_O[4] S_CLKRUN_L S_DEVSEL_L S_FRAME_L S_GNT_L[0] S_GNT_L[1] S_GNT_L[2] S_GNT_L[3] S_IRDY_L S_PAR S_PERR_L S_REQ_L[0] S_REQ_L[1] S_REQ_L[2] S_REQ_L[3] S_RST_L S_SERR_L S_STOP_L S_TRDY_L S_VIO PCI 6152 Data Book v2.0     2003 PLX Technology, Inc. All rights reserved.

  • Page 24: Configuration Registers

    Hot Swap switch 94hh Reserved 98h-9Fh VPD Register = 0000 Next Item Ptr = 00 Capability ID = 03 VPD Data Register = 0000_0000 PCI 6152 Data Book v2.0     2003 PLX Technology, Inc. All rights reserved.
  • Page 25 Control Reserved GPIO Control Miscellaneous Control EEPROM Data EEPROM Address EEPROM control Test Register Reserved Reserved D0h-EFh Subsystem ID Subsystem Vendor ID Reserved F4h-FFh PCI 6152 Data Book v2.0     2003 PLX Technology, Inc. All rights reserved.

  • Page 26: Configuration Register Description

    0=ignore VGA palette accesses on the primary interface 1=enable response to VGA palette writes on the primary interface (I/O address AD[9:0]=3C6h, 3C8h and 3C9h) Reset to 0. PCI 6152 Data Book v2.0     2003 PLX Technology, Inc. All rights reserved.
  • Page 27 0=no fast back to back transaction 1=enable fast back to back transaction Reset to 0. 10-15 Reserved Reserved. Reset to 0. PCI 6152 Data Book v2.0     2003 PLX Technology, Inc. All rights reserved.
  • Page 28 Should be set whenever a parity error is detected regardless of the Parity Error state of the bit 6 of command register. Reset to 0. PCI 6152 Data Book v2.0     2003 PLX Technology, Inc. All rights reserved.
  • Page 29 <31:16> are defined in the I/O limit address upper 16 bits register. The address bits <11:0> are assumed to be FFFh. The lower four bits (3:0) of this register set to ‘0001’ (read-only) to indicate 32-bit I/O addressing. Reset to 0. PCI 6152 Data Book v2.0     2003 PLX Technology, Inc. All rights reserved.
  • Page 30 Should be set whenever a parity error is detected regardless of the Parity Error state of the bit 6 of command register. Reset to 0. PCI 6152 Data Book v2.0     2003 PLX Technology, Inc. All rights reserved.
  • Page 31 Function Type Description ECP Pointer Enhanced capabilities port offset pointer. This register reads as 80h to indicate the offset of the power management registers. PCI 6152 Data Book v2.0     2003 PLX Technology, Inc. All rights reserved.
  • Page 32 1=forward VGA compatible memory and I/O address from primary to secondary regardless of other settings Reset to 0. Reserved Reserved (set to 0). PCI 6152 Data Book v2.0     2003 PLX Technology, Inc. All rights reserved.
  • Page 33 Memory read line and memory read multiple transactions are still prefetchable. Reset to 0. Reserved Reserved PCI 6152 Data Book v2.0     2003 PLX Technology, Inc. All rights reserved.
  • Page 34 Disable When both bits are 1, S_CLKO[3] is disabled. Clock 4 If 0, S_CLKO[3] is enabled. Disable Otherwise, it is disabled. 15:9 Reserved Reserved PCI 6152 Data Book v2.0     2003 PLX Technology, Inc. All rights reserved.
  • Page 35 1 = Stop the secondary clock whenever the secondary bus is idle and there are no requests from the primary bus. Defaults to 0 PCI 6152 Data Book v2.0     2003 PLX Technology, Inc. All rights reserved.
  • Page 36 Returns ‘1’ indicating that PCI 6152 supports the D2 device power state 11-15 PME Support Set to “F602” in Revision BA. Set to “7E02” in Revision CC. PCI 6152 Data Book v2.0     2003 PLX Technology, Inc. All rights reserved.
  • Page 37 Set to A0h. This field provides an offset into the function's PCI Configuration Space pointing to the location of next item in the function's capability list. In PCI 6152, this points to the Vital Product Data (VPD) registers. PCI 6152 Data Book v2.0     2003 PLX Technology, Inc. All rights reserved.
  • Page 38 This register is set to 03h to indicate VPD registers. Next Item Pointer (R/O) - Offset A1h Set to 00h. End of Capability list. PCI 6152 Data Book v2.0     2003 PLX Technology, Inc. All rights reserved.
  • Page 39 VPD Address register. The data read from or written to this register uses the normal PCI byte transfer capabilities. Reads to this register will return the last data read from or written to the EEPROM. PCI 6152 Data Book v2.0     2003 PLX Technology, Inc. All rights reserved.
  • Page 40 #3. If 0, the reverse is true. This order is relative to the master with the highest priority for this group, as specified in bits 11-8 of this register. PCI 6152 Data Book v2.0     2003 PLX Technology, Inc. All rights reserved.
  • Page 41 This bit enables back to back cycles on the primary interface, if bit 9 of Cycle Enable the primary command register is also enabled. PCI 6152 Data Book v2.0     2003 PLX Technology, Inc. All rights reserved.
  • Page 42 If 1, GPIO3 is configured as output. If 0, GPIO3 is an input pin Enable GPIO3 Output Value written here will be output to GPIO3 pin if configured as output Register Reserved Reserved PCI 6152 Data Book v2.0     2003 PLX Technology, Inc. All rights reserved.
  • Page 43 Contains data to be written to the EEPROM. During reads, this Data register contains data received from the EEPROM after a read cycle has completed. PCI 6152 Data Book v2.0     2003 PLX Technology, Inc. All rights reserved.
  • Page 44 Subsystem ID (Read Only) - Offset F2h This register is a nonstandard implementation of the Subsystem ID register. It is EEPROM loadable. Defaults to 0021h PCI 6152 Data Book v2.0     2003 PLX Technology, Inc. All rights reserved.

  • Page 45: Pci Bus Operation

    1011 Configuration write Type 1 Type 1 1100 Memory read multiple 1101 Dual address cycle 1110 Memory read line 1111 Memory write and invalidate PCI 6152 Data Book v2.0     2003 PLX Technology, Inc. All rights reserved.

  • Page 46: Address Phase

    IRDY# and TRDY# are asserted during the same PCI clock cycle. The last data phase of a transaction is indicated when FRAME# is de-asserted and both TRDY# and IRDY# are asserted, or when IRDY# and STOP# are asserted. PCI 6152 Data Book v2.0     2003 PLX Technology, Inc. All rights reserved.

  • Page 47: Write Transactions

    Case 4: Secondary master access device on primary bus PCI 6152 will forward address, command, byte enable, S_IRDY# to primary while forwarding data, P_DEVSEL_L, P_TRDY# and P_STOP# to secondary. PCI 6152 Data Book v2.0     2003 PLX Technology, Inc. All rights reserved.

  • Page 48: Configuration Transactions

    Type 0 configuration write and read transactions do not use data buffers; that is, these transactions are completed immediately. PCI 6152 ignores all Type 0 transactions initiated on the secondary interface. PCI 6152 Data Book v2.0     2003 PLX Technology, Inc. All rights reserved.

  • Page 49: Type 1 To Type 0 Translation

    Decodes the device number and drives the bit pattern specified in Table 4–6 on S_AD<31:16> for the purpose of asserting the device’s IDSEL signal. • Sets S_AD<15:11> to 0. • Leaves unchanged the function number and register number fields. PCI 6152 Data Book v2.0     2003 PLX Technology, Inc. All rights reserved.
  • Page 50 PCI 6152 forwards Type 1 to Type 0 configuration read or write transactions as delayed transactions. Type 1 to Type 0 configuration read or write transactions are limited to a single 32-bit data transfer. PCI 6152 Data Book v2.0     2003 PLX Technology, Inc. All rights reserved.

  • Page 51: Type 1 To Type 1 Forwarding

    PCI 6152 forwards Type 1 to Type 1 configuration write transactions as delayed transactions. Type 1 to Type 1 configuration write transactions are limited to a single data transfer. PCI 6152 Data Book v2.0     2003 PLX Technology, Inc. All rights reserved.

  • Page 52: Special Cycles

    Once the transaction is completed on the target bus, through detection of the master abort condition, PCI 6152 responds with TRDY# to the next attempt of the configuration transaction from the initiator. PCI 6152 Data Book v2.0     2003 PLX Technology, Inc. All rights reserved.

  • Page 53: Transaction Termination

    PCI 6152’s assertion of FRAME# on the target bus. PCI 6152 terminates a transaction when the target terminates the transaction with last data transfer, retry, disconnect, or target abort. PCI 6152 Data Book v2.0     2003 PLX Technology, Inc. All rights reserved.

  • Page 54: Master Abort Received By Pci 6152

    Target retry • Target disconnect • Target abort PCI 6152 handles these terminations in different ways, depending on the type of transaction being performed. PCI 6152 Data Book v2.0     2003 PLX Technology, Inc. All rights reserved.
  • Page 55 Return target abort to initiator. Set received target abort bit in target interface status register. Set signaled target abort bit in initiator interface status register. PCI 6152 Data Book v2.0     2003 PLX Technology, Inc. All rights reserved.
  • Page 56 PCI 6152 repeats a delayed read transaction until one of the following conditions is met: • PCI 6152 completes at least one data transfer. • PCI 6152 receives a master abort. • PCI 6152 receives a target abort. PCI 6152 Data Book v2.0     2003 PLX Technology, Inc. All rights reserved.

  • Page 57: Target Termination Initiated By Pci 6152

    When PCI 6152 returns a target abort to the initiator, it sets the signaled target abort bit in the status register corresponding to the initiator interface. PCI 6152 Data Book v2.0     2003 PLX Technology, Inc. All rights reserved.

  • Page 58: Address Decoding

    ISA enable bit, VGA mode bit, and VGA snoop bit before setting the I/O enable and master enable bits, and change them subsequently only when the primary and secondary PCI buses are idle. PCI 6152 Data Book v2.0     2003 PLX Technology, Inc. All rights reserved.

  • Page 59: I/O Base And Limit Address Registers

    4KB of I/O space. Write these registers with their appropriate values before setting either the I/O enable bit or the master enable bit in the command register in configuration space. PCI 6152 Data Book v2.0     2003 PLX Technology, Inc. All rights reserved.

  • Page 60: Isa Mode

    VGA mode bit before setting the memory enable and master enable bits, and change them subsequently only when the primary and secondary PCI buses are idle. PCI 6152 Data Book v2.0     2003 PLX Technology, Inc. All rights reserved.

  • Page 61: Memory-Mapped I/O Base And Limit Address Registers

    To turn off the memory-mapped I/O address range, write the memory-mapped I/O base address register with a value greater than that of the memory-mapped I/O limit address register. PCI 6152 Data Book v2.0     2003 PLX Technology, Inc. All rights reserved.

  • Page 62: Pci Bus Arbitration

    MHz, 2 clock delay is recommended. However if faster Frame propagation is desired, especially in the case of handling an aggressive PCI arbitor on the Host bus, 1 clock delay is recommended. PCI 6152 Data Book v2.0     2003 PLX Technology, Inc. All rights reserved.

  • Page 63: Transaction Delay

    If 2 clock latency mode is enabled, which is the default, then the delay for step 4 above is 2 clocks instead of 1, with everything else the same. PCI 6152 Data Book v2.0     2003 PLX Technology, Inc. All rights reserved.

  • Page 64: Error Handling

    The SERR# enable bit is set in the command register. The parity error response bit is set in the bridge control register. PCI 6152 Data Book v2.0     2003 PLX Technology, Inc. All rights reserved.

  • Page 65: Data Parity Errors

    PERR# two cycles after the data transfer occurs. It is assumed that the initiator takes responsibility for handling a parity error condition. PCI 6152 Data Book v2.0     2003 PLX Technology, Inc. All rights reserved.

  • Page 66: Data Parity Error Reporting Summary

    Upstream Primary Read Upstream Secondary Delayed write Downstream Primary Delayed write Downstream Secondary Delayed write Upstream Primary Delayed write Upstream Secondary x =don’t care PCI 6152 Data Book v2.0     2003 PLX Technology, Inc. All rights reserved.
  • Page 67 Upstream Primary Read Upstream Secondary Delayed write Downstream Primary Delayed write Downstream Secondary Delayed write Upstream Primary Delayed write Upstream Secondary x =don’t care PCI 6152 Data Book v2.0     2003 PLX Technology, Inc. All rights reserved.
  • Page 68 Upstream Primary Read Upstream Secondary Delayed write Downstream Primary Delayed write Downstream Secondary Delayed write Upstream Primary Delayed write Upstream Secondary x =dont care PCI 6152 Data Book v2.0     2003 PLX Technology, Inc. All rights reserved.

  • Page 69: System Error (Serr#) Reporting

    When S_SERR# is asserted by secondary device, PCI 6152 sets the received system error bit in the secondary status register. The PCI 6152 also conditionally asserts P_SERR# when parity error reported on target bus during write transaction. PCI 6152 Data Book v2.0     2003 PLX Technology, Inc. All rights reserved.

  • Page 70: Reset

    When S_RST# is asserted by means of the secondary reset bit, PCI 6152 remains accessible during secondary interface reset and continues to respond to accesses to its configuration space from the primary interface. PCI 6152 Data Book v2.0     2003 PLX Technology, Inc. All rights reserved.

  • Page 71: Bridge Behavior

    FRAME# with IRDY# being asserted (or remaining asserted) on the same cycle. The cycle completes when TRDY# and IRDY# are both asserted simultaneously. The target should de-assert TRDY# for one cycle following final assertion (sustained three-state signal). PCI 6152 Data Book v2.0     2003 PLX Technology, Inc. All rights reserved.

  • Page 72: Abnormal Termination (Initiated By Bridge Master)

    In the case of read, PCI 6152 will latch the data, and wait for the same type #1 configuration cycle on the primary side. PCI 6152 Data Book v2.0     2003 PLX Technology, Inc. All rights reserved.

  • Page 73: Configuration Type #1 To Type #1 By-Passing

    Likewise, all the similar cycle appearing on the secondary side is considered to have slave on the secondary side. PCI 6152 Data Book v2.0     2003 PLX Technology, Inc. All rights reserved.

  • Page 74: Secondary Master

    4 of clock run control register is set, secondary clock will be stopped when the bus is idle and there is no cycle from primary bus. PCI 6152 Data Book v2.0     2003 PLX Technology, Inc. All rights reserved.

  • Page 75: Clocks

    2ns. • Terminating or disabling unused secondary clock outputs is recommended to reduse power dissipation and noise in the system PCI 6152 Data Book v2.0     2003 PLX Technology, Inc. All rights reserved.

  • Page 76: 66-Mhz Operation

    M66EN connection when using the PCI 6152 66BC. PCI 6152 supports only 1:1 frequency ratio on the primary and secondary bus interfaces. PCI 6152 Data Book v2.0     2003 PLX Technology, Inc. All rights reserved.

  • Page 77: Miscellaneous Options

    EEPAUTO bit. Host access is allowed only after EEPAUTO status becomes '0' which means that the auto load initialization sequence is complete. PCI 6152 Data Book v2.0     2003 PLX Technology, Inc. All rights reserved.

  • Page 78: Eeprom Data Structure

    PCI 6152 only supports EEPROM Device Address 0. Write: Device Word Data (n) Data (n +1) Address Address (n) Read: Device Word Device Data (n) Data (n +1) Address Address (n) Address PCI 6152 Data Book v2.0  2003 PLX Technology, Inc. All rights reserved.

  • Page 79: Eeprom Address And Corresponding Pci 6152 Register

    14h-15h Test Register CDh Bits7-0: reserved Bits15-8:register CDh 15h-16h CEh, CFh Test Register CE/CFh Bits7-0: register CEh Bits11-8: reserved Bits15-8: register CFh, bits 7-4 PCI 6152 Data Book v2.0     2003 PLX Technology, Inc. All rights reserved.

  • Page 80: General Purpose I/O Interface

    224 bytes of VPD data in the EEPROM device. VPD related registers are located starting at offset A0h of the PCI configuration space. VPD also uses the enhanced capabilities port address mechanism PCI 6152 Data Book v2.0     2003 PLX Technology, Inc. All rights reserved.

  • Page 81: Pci Power Management

    PME# signals are routed from downstream devices around PCI-to PCI bridges. PME# signals do not pass through PCI-to-PCI bridges. PCI 6152 Data Book v2.0     2003 PLX Technology, Inc. All rights reserved.

  • Page 82: Hot Swap

    Note that Hot Swap is an independent section of PCI 6152. Its function has no impact on the rest of the chip. If Hot Swap feature is not needed, simply leave ENUM_L unconnected. PCI 6152 Data Book v2.0     2003 PLX Technology, Inc. All rights reserved.

  • Page 83: Package Specifications

    This specification outlines the mechanical dimensions for 160 pin Tiny BGA package as shown below. All dimensions are in millimeters (mm). 0.36 0.27 SIDE VIEW 15.0 13.0 13.0 15.0 BOTTOM VIEW PCI 6152 Data Book v2.0     2003 PLX Technology, Inc. All rights reserved.
  • Page 84 Ball diameter 0.35 0.40 0.45 Substrate thickness 0.36 Overall package width 15.00 Overall Encapsulation width 13.00 Overall package width 15.00 Overall Encapsulation width 13.00 PCI 6152 Data Book v2.0     2003 PLX Technology, Inc. All rights reserved.

  • Page 85: 160-Pin Standard Pqfp

    This specification outlines the mechanical dimensions for 160 pin standard PQFP (plastic quad flat pack) package as shown below. All dimensions are in millimeters (mm). PCI 6152 Data Book v2.0     2003 PLX Technology, Inc. All rights reserved.
  • Page 86 0.15 0.25 31.6 32.0 32.4 27.8 28.0 28.2 31.6 32.0 32.4 27.8 28.0 28.2 0.65 BSC 1.325 TYP 1.325 TYP θ 0° 10° 0.13 PCI 6152 Data Book v2.0     2003 PLX Technology, Inc. All rights reserved.

  • Page 87: Electrical Specifications

    21.2 Functional Operating Range Parameter Minimum Maximum Supply Voltage 3.0 V 3.6 V Operating ambient temperature 0 °C 70 °C PCI 6152 Data Book v2.0     2003 PLX Technology, Inc. All rights reserved.

  • Page 88: Dc Electrical Characteristics

    5V Signalling Output HIGH Voltage = -2 mA oh5V iout µA Input Leakage Current 0 < V < V ±2 Input Pin Capacitance 10.0 PCI 6152 Data Book v2.0     2003 PLX Technology, Inc. All rights reserved.

  • Page 89: Pci Clock Signal Ac Parameter Measurements

    V/ns Delay from PCLK to SCLK sclk PCLK rising to SCLKO rising sclkr PCLK falling to SCLKO falling sclkf SCLKO[x] to SCLKO[y] 0.500 skew PCI 6152 Data Book v2.0     2003 PLX Technology, Inc. All rights reserved.

  • Page 90: 66 Mhz Pci Clock Signal Ac Parameters

    Delay from PCLK to SCLK sclk PCLK rising to SCLKO rising sclkr PCLK falling to SCLKO falling sclkf SCLKO[x] to SCLKO[y] 0.500 skew 21.5 PCI Signal Timing Specification PCI 6152 Data Book v2.0     2003 PLX Technology, Inc. All rights reserved.

  • Page 91: 33 Mhz Pci Signal Timing

    Input setup time to CLK – bused signals Input setup time to CLK – point to su(ptp) point Input signal hold time from CLK PCI 6152 Data Book v2.0     2003 PLX Technology, Inc. All rights reserved.

  • Page 92: Appendix A: Pci 6152 33Pc Part Description

    V S S P_AD[21] S_AD[30] V S S S_AD[31] P_AD[22] S_REQ_L[0] P_AD[23] S_REQ_L[1] P_IDSEL S_REQ_L[2] P_CBE_L[3] V D D V S S Pin Diagram, Top View PCI 6152 Data Book v2.0     2003 PLX Technology, Inc. All rights reserved.

  • Page 93: Pci 6152 33Pc 160 Pin Pinout

    S_CBE_L[2] S_GNT_L[1] S_AD[16] S_GNT_L[2] S_AD[17] S_GNT_L[3] S_AD[18] S_RST_L S_AD[19] S_AD[20] S_CLK S_AD[21] S_VIO S_AD[22] S_CLK_O[0] S_AD[23] S_CLK_O[1] S_CBE_L[3] S_AD[24] S_CLK_O[2] S_AD[25] S_CLK_O[3] S_AD[26] S_CLK_O[4] PCI 6152 Data Book v2.0     2003 PLX Technology, Inc. All rights reserved.
  • Page 94 S_CBE_L[0] P_CBE_L[2] S_AD[08] P_FRAME_L P_IRDY_L S_AD[09] S_AD[10] P_TRDY_L S_AD[11] P_DEVSEL_L P_STOP_L S_AD[12] S_AD[13] P_PERR_L S_AD[14] P_SERR_L S_AD[15] P_PAR P_CBE_L[1] S_CBE_L[1] BPCCE P_AD[15] P_AD[14] P_AD[13] PCI 6152 Data Book v2.0     2003 PLX Technology, Inc. All rights reserved.

  • Page 95: Pin Assignment Sorted By Signal Name

    P_AD[30] S_AD[30] P_AD[31] S_AD[31] P_CBE_L[0] S_CBE_L[0] P_CBE_L[1] S_CBE_L[1] P_CBE_L[2] S_CBE_L[2] P_CBE_L[3] S_CBE_L[3] P_CLK S_CLK P_DEVSEL_L S_CLK_O[0] P_FRAME_L S_CLK_O[1] P_GNT_L S_CLK_O[2] P_IDSEL S_CLK_O[3] P_IRDY_L S_CLK_O[4] PCI 6152 Data Book v2.0     2003 PLX Technology, Inc. All rights reserved.
  • Page 96 S_DEVSEL_L S_FRAME_L S_GNT_L[0] S_GNT_L[1] S_GNT_L[2] S_GNT_L[3] S_IRDY_L S_PAR S_PERR_L S_REQ_L[0] S_REQ_L[1] S_REQ_L[2] S_REQ_L[3] S_RST_L S_SERR_L S_STOP_L S_TRDY_L S_VIO PCI 6152 Data Book v2.0     2003 PLX Technology, Inc. All rights reserved.

  • Page 97: Pci 6152 33Pc Vs 21152 Pinout Comparison

    This is a power pin, and has no effect on operation. N/C: No Connect. In most cases, this will not present a problem, as very few devices implement lock functionality. PCI 6152 Data Book v2.0     2003 PLX Technology, Inc. All rights reserved.

  • Page 98: Appendix B : Sample Schematics

    PLX Technology, Inc. Title PCI 6152 DEMO BOARD ORCAD Capture for Windows - Ver. 9.00.1153 Size Document Number Date: Wednesday, February 14, 2001 Sheet PCI 6152 Data Book v2.0     2003 PLX Technology, Inc. All rights reserved.
  • Page 99 P C I 6 1 5 2 D E M O B O A R D P C I 6 1 5 2 Size Document Number Date: Monday, February 26, 2001 Sheet PCI 6152 Data Book v2.0     2003 PLX Technology, Inc. All rights reserved.
  • Page 100 P C I 6 1 5 2 D E M O B O A R D Size Document Number EEPROM is optional Date: Monday, February 26, 2001 Sheet PCI 6152 Data Book v2.0     2003 PLX Technology, Inc. All rights reserved.
  • Page 101 P C I 6 1 5 2 D E M O B O A R D Size Document Number Date: Monday, February 26, 2001 Sheet PCI 6152 Data Book v2.0     2003 PLX Technology, Inc. All rights reserved.
  • Page 102 P C I 6 1 5 2 D E M O B O A R D Size Document Number Date: Monday, February 26, 2001 Sheet PCI 6152 Data Book v2.0     2003 PLX Technology, Inc. All rights reserved.
  • Page 103 PLX DOES NOT ASSUME ANY RESPONSIBILITY OR LIABILITY OUT OF THIS APPLICATION PLX Technology, Inc. Title PCI 6152 DEMO BOARD Size Document Number Date: Monday, February 26, 2001 Sheet PCI 6152 Data Book v2.0     2003 PLX Technology, Inc. All rights reserved.

  • Page 104: Appendix C: Application Notes

    AD[16] of the AGP interface. On the secondary side, this presents the same problem when connecting more than one AGP device. The solution to this issue is implementation specific, and is left to the system designer. PCI 6152 Data Book v2.0     2003 PLX Technology, Inc. All rights reserved.

  • Page 105: Appendix D: Timing Diagrams

    Appendix D: Timing Diagrams Figure 1 : Primary to Secondary Type 1 to Type 0 Configuration Cycle conversion. PCI 6152 Data Book v2.0     2003 PLX Technology, Inc. All rights reserved.
  • Page 106 Figure 2 : Primary to Secondary Type 1 to Type 1 Configuration Cycle passing. PCI 6152 Data Book v2.0     2003 PLX Technology, Inc. All rights reserved.
  • Page 107 Figure 3 : Secondary to Primary Memory Read Line transaction. PCI 6152 Data Book v2.0     2003 PLX Technology, Inc. All rights reserved.
  • Page 108 Figure 4 : Primary to Secondary Memory Read transaction. PCI 6152 Data Book v2.0     2003 PLX Technology, Inc. All rights reserved.
  • Page 109 Figure 5 : Secondary to Primary Memory Read transaction. PCI 6152 Data Book v2.0     2003 PLX Technology, Inc. All rights reserved.
  • Page 110 Figure 6 : Primary to Secondary Memory Write transaction followed by Secondary to Primary Memory Write transaction. PCI 6152 Data Book v2.0     2003 PLX Technology, Inc. All rights reserved.
  • Page 111 Figure 7 : Secondary to Primary Memory Write transaction. PCI 6152 Data Book v2.0     2003 PLX Technology, Inc. All rights reserved.

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