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Performance Technologies
205 Indigo Creek Drive
Rochester, NY 14626 USA
585.256.0248
support@pt.com
www.pt.com
© 2009 Performance Technologies, Inc.
All Rights Reserved.
PCI334A Quad Serial Communica-
tions Controller
PCI334A
Universal I/O 32-bit PCI Quad
Serial Communications Controller
Hardware Manual
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Table of Contents
Summary of Contents for Performance Technologies PCI334A Series
- Page 1 PCI334A Quad Serial Communica- tions Controller PCI334A Universal I/O 32-bit PCI Quad Serial Communications Controller Hardware Manual Performance Technologies 205 Indigo Creek Drive Rochester, NY 14626 USA 585.256.0248 support@pt.com www.pt.com © 2009 Performance Technologies, Inc. All Rights Reserved.
- Page 2 Performance Technologies Inc. does not assume any liability arising out of the application or use of any product or circuit described herein. No part of this document may be copied or reproduced in any form or by any means without the prior permission of Performance Technologies Inc.
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Page 3: Table Of Contents
C o n t e n t s Chapter 1: About This Guide Overview ..............11 Text Conventions . - Page 4 Contents Jumpers ..............25 Option Clock .
- Page 5 Contents Receive Clock Select ............46 Status Register .
- Page 6 Contents J1 - 80-pin Connector ............72 P1 - Debug Port .
- Page 7 T a b l e s Table 2-1: PCI334A Part Numbers ........... 16 Table 2-2: PCI334A to PCI334 Product Comparison .
- Page 8 Tables Table 5-6: QUICC Interrupt Register ..........48 Table 5-7: PCI Interrupt Register.
- Page 9 Tables Table B-2: Global Memory Register (GMR) Settings........78 Table B-3: Base Register 1 (BR1) Settings .
- Page 10 Tables...
- Page 11 F i g u r e s Figure 2-1: PCI334A Side View Photograph ......... . . 18 Figure 3-1: PCI334A Component Layout.
- Page 12 Figures...
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Page 13: Chapter 1: About This Guide
C h a p t e r About This Guide Overview This manual describes the operation and use of the PCI334A Universal I/O 32-bit Quad Serial Communications Controller (referred to as the PCI334A in this manual). In these chapters you will find installation and configuration information, plus a functional block description intended for the application developer of this board. -
Page 14: Text Conventions
Customer Support and Services Performance Technologies offers a variety of standard and custom support packages to ensure customers have access to the critical resources that they need to protect and maximize hardware and software investments throughout the development, integration, and deployment phases of the product life cycle. -
Page 15: Customer Support Packages
Performance Technologies within 12 months of shipment, or in the case of software and integrated circuits within ninety (90) days of shipment and provided said nonconforming products are returned F.O.B. - Page 16 THIS WARRANTY IS IN LIEU OF ALL OTHER WARRANTIES WHETHER EXPRESS, IMPLIED OR STATUTORY INCLUDING IMPLIED WARRANTIES OF MERCHANTABILITY OR FITNESS. IN NO EVENT SHALL PERFORMANCE TECHNOLOGIES BE LIABLE FOR ANY INCIDENTAL OR CONSEQUENTIAL DAMAGES DUE TO BREACH OF THIS WARRANTY...
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Page 17: Chapter 2: Introduction
This document provides information for users of the PCI334A Universal I/O 32-bit PCI Quad Serial Communications Controller. Note: Performance Technologies, Inc. has a similar product with a very similar model name, the PCI344. Ensure that you are using the correct manual for the applicable product. -
Page 18: Pci334A Models And Accessories
Chapter 2: Introduction PCI334A Models and Accessories Table 2-1, “PCI334A Part Numbers,” lists the PTI part numbers for the models and accessories available for the PCI334A. Table 2-1: PCI334A Part Numbers Item Non-RoHS Part Number RoHS Part Number PCI334A Versions Four Port Sync. -
Page 19: Product Summary
Product Summary Product Summary The PCI334A PCI Quad Communications Controller (shown in Figure 2-1, “PCI334A Side View Photograph,” on page 18) is a design update to the PCI334A, required due to components obsolescence. As part of this update, certain characteristics of the PCI334A are revised or enhanced. -
Page 20: Programming Differences
Chapter 2: Introduction Figure 2-1: PCI334A Side View Photograph Programming Differences Some modifications are necessary to the QUICC register values for proper operation of the PCI334A with the SRAM instead of the DRAM SIMM on the PCI334. These disable the DRAM controller and enable the SRAM controller. -
Page 21: Pci334A Features
PCI334A Features PCI334A Features MC68360 QUICC • CPU32+ Processor (4.5 MIPS at 25 MHz) • 32-Bit Version of the CPU32 Core (Fully Compatible with the CPU32) • Background Debug Mode • Byte-Misaligned Addressing • Four General Purpose Timers • Superset of MC68302 Timers •... -
Page 22: Pci9056 Pci Interface
Chapter 2: Introduction • Independent (can be connected to any SCC or SMC) • Allows Changes During Operation • Autobaud Support Option PCI9056 PCI Interface • PCI Compliance Revision 2.2 • 32-bit, 66 MHz operation • Register compatible with PCI9054, PCI9656, PCI9060, and PCI9080 •... -
Page 23: Glossary
Glossary Glossary Bytes per second Bits per second Central Processing Unit Direct Memory Access, hardware controller block data transfers DMAC Direct Memory Access Controller DRAM Dynamic Random Access Memory half-word In this manual, this term indicates a 16-bit value HDLC High-Level Data Link Control Lbus Local PCI334A on-board bus... - Page 24 Chapter 2: Introduction...
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Page 25: Chapter 3: Installation
C h a p t e r Installation Overview This chapter describes how to configure the PCI334A’s jumpers and install the PCI334A into the PCI slot in a PC. Topics covered in this chapter include: • “Configuring the PCI334A,” on page 24 •... -
Page 26: Configuring The Pci334A
Chapter 3: Installation Configuring the PCI334A Figure 3-1: PCI334A Component Layout High Density 80-pin Connector (J1) Burn-in LED Option Clock Debug Port QUICC Chip PLD ISP Connector PCI9056 PCI Interface SRAM Flash PROM... -
Page 27: Jumpers
Jumpers Jumpers There are several jumpers on the PCI334A, shown in Figure 3-1, “PCI334A Component Layout,” on page Table 3-1, “Jumper Settings and Functions,” shows a summary of board jumpers. No special tools are required to move jumpers. Reposition the jumpers as defined in the following table. -
Page 28: Installing The Pci334A Card Into Pc
Chapter 3: Installation Installing the PCI334A card into PC Use the following steps to install the PCI334A card into a PCI slot. See Figure 3-2, “PCI334A Installation Diagram,” on page Caution: Electronic components on printed circuit boards are extremely sensitive to static electricity. Ordinary amounts of static electricity generated by your clothing or work environment can damage the electronic equipment. -
Page 29: Pci334A Cabling
PCI334A Cabling Figure 3-2: PCI334A Installation Diagram PCI334A Cabling The PCI334A provides external connectivity through a passive cabling system. A hydra-style connector provides front panel serial port connectivity to four DB25 connectors for the RS232C and EIA530 versions, four DB37 connectors for the RS449 version, and M34 connectors for the V.35 version, in DTE configuration (pins). - Page 30 Chapter 3: Installation...
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Page 31: Chapter 4: Functional Description
C h a p t e r Functional Description Overview The PCI334A Universal I/O 32-bit Quad Serial Communications Controller provides four serial channel interfaces for high performance synchronous communications on a PCI host system. The design incorporates a Motorola MC68360 Quad Integrated Communications Controller (QUICC) and a PLX PCI9056 with DMA capability. -
Page 32: Figure 4-1: Pci334A Block Diagram
Chapter 4: Functional Description • “Clock Steering,” on page 42 • “Debug Port,” on page 42 • “Optional Logic Analyzer Connections,” on page 43 The block diagram in Figure 4-1, “PCI334A Block Diagram,” demonstrates the major components of this design. Figure 4-1: PCI334A Block Diagram... -
Page 33: Power Considerations
Power Considerations Power Considerations The PCI334A is a Universal I/O card, meaning it is compatible with either +3.3V or +5V VIO on the PCI backplane. The PLX PCI9056 interface chip can tolerate these voltages. The board is designed to operate in +5V only and mixed +5V/+3.3V powered backplanes. Typical and maximum power consumption of the PCI334A is presented in Table 4-1, “PCI334A Power Consumption in a +5V or Mixed +3.3V / +5V System,”... - Page 34 Chapter 4: Functional Description This map applies for QUICC and PCI slave accesses. A single PROM device contains the QUICC Boot Firmware as well as the PCI configuration information. The QUICC has access to the entire address range as shown in this table. The PCI Bus has access to the entire range with the exception of the local boot PROM.
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Page 35: Table 4-3: Quicc Register Addresses
MC68360 Quad Integrated Communications Controller QUICC Register Setup All internal memory and registers of the QUICC occupy a single 8-KByte memory block that is relocatable along 8-KByte boundaries. The location is fixed by writing the desired base address of the 8-KByte memory block to the Memory Base Address Register (MBAR). The MBAR resides at a fixed location in 0003.FF00. -
Page 36: Table 4-4: Quicc Access Timing
Chapter 4: Functional Description 1. MBAR is at a fixed address. The value in MBAR determines the value of DPRBASE and REGB 2. Base Address of QUICC Dual-Port RAM section. 3. Base Address of QUICC Register section 4. revised from PCI334 The base and option register settings correspond to the device address map provided in Table 4-2, “Device Address Map,”... -
Page 37: Resets
Resets Timers The QUICC has four general purpose timer modules, a periodic interrupt timer, a software watchdog timer, and a bus cycle period monitor. The software watchdog timer may be used to interrupt the CPU, or reset the PCI334A logic and CPU. -
Page 38: Endian Conversion
Chapter 4: Functional Description Endian Conversion Proper care must be taken when accessing local addresses from the PCI Bus and PCI9056 Registers from the local bus. The hardware does not handle endian conversion from the big endian local bus to the little endian PCI Bus (and interface). Accesses from the PCI Bus less than 32-bits wide must change the lower two address bits for proper data bytes to be read/ written as shown in Table 4-6, “Addressing for Endian Conversion,”... -
Page 39: Table 4-7: Pci9056 Pci Configuration Register Addresses
PCI Interface Mailbox Registers There are eight 32-bit mailbox registers in the PCI9056. These registers are used to pass command and status information between the PCI Host and the QUICC. Table 4-7: PCI9056 PCI Configuration Register Addresses Register Local Address Width in Bits Setting Device ID... -
Page 40: Table 4-9: Pci9056 Shared Run Time Register Addresses
Chapter 4: Functional Description Table 4-9: PCI9056 Shared Run Time Register Addresses Register Local Address Width in Bits Setting Mailbox Reg 0 0010.00c0h Mailbox Reg 1 0010.00c4h Mailbox Reg 2 0010.00c8h Mailbox Reg 3 0010.00cch Mailbox Reg 4 0010.00d0h Mailbox Reg 5 0010.00d4h Mailbox Reg 6 0010.00d8h... -
Page 41: Modes Of Operation
PCI Interface Modes of Operation Direct Master The PCI334A does not support direct access to the PCI bus by the QUICC. Only DMA accesses may be sourced to the PCI bus as discussed below. Direct Slave The PCI334A supports both memory mapped (Memory Read, Memory Read Multiple, Memory Read Line) and I/O mapped (I/O Read) accesses to the Local bus from the PCI bus. -
Page 42: Local Bus Arbitration Priority
Chapter 4: Functional Description Local bus Arbitration Priority QUICC internal masters have highest priority during arbitration requests, followed by PCI accesses via the PCI9056. The QUICC’s CPU32 core has the lowest priority. The arbitration between the CPU32 and QUICC internal masters (such as IDMA or SDMA) is handled internal to the QUICC. -
Page 43: Sram Array
SRAM Array SRAM Array The SRAM array has a 32-bit data width and is implemented using four micro ball grid array surface mount components. SRAM control is embedded in the QUICC chip and it provides 1 Wait State (2 clocks @ 25MHz) Read and Write cycle period for MC68360 accesses (for 70-ns SRAM). -
Page 44: Rs422 (Eia530 Or Rs449 Cabling)
DB25 connector for the debug port. This console cable (part number 11-160Q053310) is available by special order from Performance Technologies. Please see “Customer Support and Services,” on page During SMC1 initialization, a break sequence can be enabled to generate an interrupt. If the debug port is left unconnected to a terminal, the QUICC’s SMC1 port will receive all 0s, thus... -
Page 45: Optional Logic Analyzer Connections
Optional Logic Analyzer Connections Optional Logic Analyzer Connections Locations have been provided for the optional user installation of through-hole header strips for the connection of external test equipment. These are installed on the bottom side of the board. The pinouts and suggested vendor part numbers for these connectors are shown in Table A-6, “Logic Analyzer Connectors Summary,”... - Page 46 Chapter 4: Functional Description...
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Page 47: Chapter 5: Registers
C h a p t e r Registers Overview Topics covered in this chapter include: • “TCSL Register,” on page 46 • “RCSL Register,” on page 46 • “Status Register,” on page 47 • “QUICC Interrupt Register,” on page 48 •... -
Page 48: Tcsl Register
Chapter 5: Registers TCSL Register The TCSL (transmit clock select) Register provides the PCI334A with control of the source of the transmit clocks for each serial port. The TCSL Register is a 32-bit register located at local address 0011.0200h. The TCSL Register is readable and writable. The TCSL Register is described in Table 5-1, “TCSL Register,”... -
Page 49: Status Register
Status Register Status Register The Status Register provides status of on-board signals for monitoring The Status Register is a read only, 32-bit register located at local address 0010.1000h. The Status Register is described Table 5-3, “Status Register,” below. Table 5-3: Status Register Mnemonic Function Reset Value... -
Page 50: Pci User Out
Chapter 5: Registers PCI User Out The PCI User Out bit indicates the status of the PCI9056 User Out pin. This is a general purpose output of the PCI9056 that is controlled from the PCI9056 “EEPROM Control, PCI Command Codes, User I/O Control, Init Control Register” (PCI9056 configuration space, PCI6Ch, LOC ECh). -
Page 51: Pci Interrupt
Misc. Register PCI Interrupt The PCI Interrupt (PINT) bit causes a PCI Interrupt when set. Clearing this bit removes the interrupt. The PCI Interrupt is mapped to PCI INTA#, INTB#, INTC#, or INTD# through the PCI9056 PCI Interrupt Pin Register (PCI9056 configuration space, offset 3Dh). Hardware requires this register must map the PCI Interrupt to INTA#. -
Page 52: Board Configuration Register
Chapter 5: Registers Board Configuration Register The Board Configuration Register is a read only register that includes information on the configuration of the PCI334A. The Board Configuration register is a 32-bit register located at local address 0010.1600h. The Board Configuration is described in Table 5-9, “Board Configuration Register,”... -
Page 53: Prom Write Enable Register
PROM Write Enable Register PROM Write Enable Register The PROM Write Enable Register contains the protection bit for enabling/disabling writing to the PROM. This register also contains the Software ID field. The PROM Write Enable Register is a 32-bit register located at local address 0010.1700h. The PROM Write Enable Register is readable and writable. - Page 54 Chapter 5: Registers...
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Page 55: Chapter 6: Quicc I/O Ports
C h a p t e r QUICC I/O Ports Overview The QUICC has three general-purpose I/O ports A, B and C. Each pin in I/O ports may be configured as a general-purpose I/O pin or as a dedicated peripheral interface pin. The PCI334A design uses these ports as described below. -
Page 56: Quicc Port A
Chapter 6: QUICC I/O Ports QUICC Port A Assignment of Port A pins including their direction is accomplished by configuring the PAPAR, PADIR, and PAODR registers on the QUICC. An example configuration for Port A is shown in Table 6-1, “Port A Configuration Settings,” below. -
Page 57: Quicc Port B
QUICC Port B QUICC Port B Assignment of Port B pins including their direction is accomplished by configuring the PBPAR, PBDIR, and PBODR registers on the QUICC. An example configuration for Port B is shown in Table 6-3, “Port B Configuration Settings,” below. -
Page 58: Quicc Port C
Chapter 6: QUICC I/O Ports QUICC Port C Assignment of Port C pins including their direction is accomplished by configuring the PCPAR, PCDIR, PCSO, and PCINT registers on the QUICC. An example configuration for Port C is shown in Table 6-5, “Port C Configuration Settings,” below. -
Page 59: Chapter 7: Connector And Cabling
C h a p t e r Connector and Cabling Overview All versions of the PCI334A have an 80-pin Amplimite connector providing the signals for all four serial ports. The pinout of the Amplimite connector is described in the cabling sections below. -
Page 60: Rs232C Cabling
Chapter 7: Connector and Cabling RS232C Cabling A shielded, hydra-style breakout cable providing four 25-pin, D-shell (DB25) DTE (pins) connectors is available for the PCI334A-11890 (RS232C) version. The pin assignments for the cabling and connectors are shown in Table 7-1, “RS232C Connector Pin Assignments,” below. - Page 61 RS232C Cabling Table 7-1: RS232C Connector Pin Assignments (Continued) 80-Pin Signal RS232C RS232C DB25 Description Name Mnemonic Pin No. GND2 Port 2 Signal Ground RXC2 Port 2 Receive Clock RXD3 Port 3 Receive Data DTR3 Port 3 Data Terminal Ready TXD3 Port 3 Transmit Data RTS3...
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Page 62: Rs449 Cabling
Chapter 7: Connector and Cabling RS449 Cabling A shielded, hydra-style breakout cable providing four 37-pin, D-shell (DB37) DTE (pins) with male connectors are supplied with the PCI334A-11891 (RS449) version. Since there were not enough wires to create the SG (Pin 19) connections please use Shield Ground (Pin 1) of the DB37 connector for this signal. - Page 63 RS449 Cabling Table 7-2: RS449 Connector Pin Assignments (Continued) 80-Pin Signal RS449 RS449 DB37 Description Name Mnemonic Pin No. TXCI2(B) ST(B) Port 2 Transmit Clock In DCD2(A) RR(A) Port 2 Data Carrier Detect DCD2(B) RR(B) Port 2 Data Carrier Detect DSR2(A) DM(A) Port 2 Data Set Ready...
- Page 64 Chapter 7: Connector and Cabling Table 7-2: RS449 Connector Pin Assignments (Continued) 80-Pin Signal RS449 RS449 DB37 Description Name Mnemonic Pin No. RTS4(B) RS(B) Port 4 Request To Send TXC4(A) TT(A) Port 4 Transmit Clock TXC4(B) TT(B) Port 4 Transmit Clock TXCI4(A) ST(A) Port 4 Transmit Clock In...
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Page 65: Eia530 Cabling
EIA530 Cabling EIA530 Cabling The following EIA530 (RS530) pinout table is provided so that the user can configure their own cable if they need to connect to another EIA530 device. This information is for reference only since the EIA530 cable is not available as a standard product. The pin assignments for a possible shielded, hydra-style breakout cable providing four 25-pin, D-shell (DB25) DTE (pins) connectors are shown in Table 7-3, “EIA530 Connector Pin Assignments,”... - Page 66 Chapter 7: Connector and Cabling Table 7-3: EIA530 Connector Pin Assignments (Continued) 80-Pin Signal EIA530 EIA530 DB25 Description Name Mnemonic Pin No. DCD2+ CF(B) Port 2 Data Carrier Detect DSR2- CC(A) Port 2 Data Set Ready DSR2+ CC(B) Port 2 Data Set Ready CTS2- CB(A) Port 2 Clear To Send...
- Page 67 EIA530 Cabling Table 7-3: EIA530 Connector Pin Assignments (Continued) 80-Pin Signal EIA530 EIA530 DB25 Description Name Mnemonic Pin No. DCD4+ CF(B) Port 4 Data Carrier Detect DSR4- CC(A) Port 4 Data Set Ready DSR4+ CC(B) Port 4 Data Set Ready CTS4- CB(A) Port 4 Clear To Send...
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Page 68: V.35 Cabling
Chapter 7: Connector and Cabling V.35 Cabling A shielded, hydra-style breakout cable providing four M-34, DTE (pins) connectors is available for the PCI334A-11892 (V.35) version. The pin assignments for the cabling and connector are shown in Table 7-4, “V.35 Connector Pin Assignments,” below. - Page 69 V.35 Cabling Table 7-4: V.35 Connector Pin Assignments 80-Pin Signal V.35 M-34 Pin No. Description Name Mnemonic Port 2 Line Test CTS2 Port 2 Clear To Send RXC2(A) Port 2 Receive Clock RXC2(B) Port 2 Receive Clock RXD3(A) Port 3 Receive Data RXD3(B) Port 3 Receive Data DTR3...
- Page 70 Chapter 7: Connector and Cabling Table 7-4: V.35 Connector Pin Assignments 80-Pin Signal V.35 M-34 Pin No. Description Name Mnemonic Port 4 Line Test CTS4 Port 4 Clear To Send RXC4(A) Port 4 Receive Clock RXC4(B) Port 4 Receive Clock...
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Page 71: Appendix A: Connector Pinouts
A p p e n d i x Connector Pinouts Overview This appendix presents the pin assignments for the various factory-installed and optional PCI334A connectors. See Figure 3-1, “PCI334A Component Layout,” on page 24 for connector location. Topics covered in this chapter include: Factory-Installed Connectors •... -
Page 72: Factory-Installed Connectors
Appendix A: Connector Pinouts Factory-Installed Connectors P4 - PCI Connector Table A-1: P4 - PCI Connector Pin Assignments Pin Number Side B Signal Name Side A Signal Name nc {-12V} nc {TRST#} nc {TCK} nc {+12V} nc {TMS} INTA# nc {INTB#} nc {INTC#} nc {INTD#} PRSNT1#... - Page 73 Factory-Installed Connectors Table A-1: P4 - PCI Connector Pin Assignments (Continued) Pin Number Side B Signal Name Side A Signal Name DEVSEL# PCIXCAP {GND} STOP# LOCK# +3.3V PERR# nc {SDONE} +3.3V nc {SBO#} SERR# +3.3V C/BE[1]# AD[15] AD[14] +3.3V AD[13] AD[12] AD[11] AD[10]...
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Page 74: J1 - 80-Pin Connector
Appendix A: Connector Pinouts J1 - 80-pin Connector Table A-2: J1 - High Density 80-pin Connector Pin Assignments Signal Name Pin Number Signal Name RXC4+ RXC2+ RXC4- RXC2- CTS4+ CTS2+ CTS4- CTS2- DSR4+ DSR2+ DSR4- DSR2- DCD4+ DCD2+ DCD4- DCD2- TXCI4+ TXCI2+ TXCI4-... -
Page 75: P1 - Debug Port
Logic Analyzer Connectors P1 - Debug Port Table A-3: P1 - Debug Port Pin Assignments Signal Name Header Pin No. DB25 Pin No. GROUND P2 - BDM Connector Table A-4: P2 - BDM Connector Pin Assignments Pin Number Signal Name Signal Name Pin Number -QDS... -
Page 76: P5 - Control
Appendix A: Connector Pinouts P5 - Control Table A-7: P5 - Control Connector Pin Assignments Pin Number Signal Name Signal Name Pin Number -QCS0 -RESETS -QCS1 +HOLD -QCS2 +HOLDA -RAS3 -PADS -RAS4 -READY -QCS5 -PREAD -QCS6 -WAIT -QCS7 -LBE0 -QAS -LBE1 -QDSAK0 -LBE2... -
Page 77: P6 - Data
Logic Analyzer Connectors P6 - Data Table A-9: P6 - Data Connector Pin Assignments Pin Number Signal Name Signal Name Pin Number +LD00 +LD16 +LD01 +LD17 +LD02 +LD18 +LD03 +LD19 +LD04 +LD20 +LD05 +LD21 +LD06 +LD22 +LD07 +LD23 +LD08 +LD24 +LD09 +LD25 +LD10... - Page 78 Appendix A: Connector Pinouts...
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Page 79: Appendix B: Register Value Changes For Sram
A p p e n d i x Register Value Changes for SRAM Overview This appendix presents recommended register settings for the following SRAM registers, as shown in Table B-1, “SRAM Registers,” below. Table B-1: SRAM Registers Register Link 0004.1040h 0x00000000 “Global Memory Register (GMR),”... -
Page 80: Global Memory Register (Gmr)
Appendix B: Register Value Changes for SRAM Global Memory Register (GMR) Table B-2: Global Memory Register (GMR) Settings Recommended Bit Position Field Description Setting 31-24 RCNT7-RCNT0 0000.0000 Leave refresh counter period at default value of all zeroes since DRAM is not used RFEN DRAM refresh is disabled 22-21... -
Page 81: Option Register 1 (Or1)
Overview Option Register 1 (OR1) Table B-4: Option Register 1 (OR1) Settings Recommended Bit Position Field Description Setting 31-28 TCYC3-TCYC0 0010 One SRAM wait state (TCYC = 2) 27-11 AM27-AM11 1111.1110.0000. Address mask – 2 Megabyte window 0000.0000.0 10-7 FCM3-FCM0 0000 Ignore function codes BCYC1-BCYC0... -
Page 82: Option Register 2 (Or2)
Appendix B: Register Value Changes for SRAM Option Register 2 (OR2) Table B-6: Option Register 2 (OR2) Settings Recommended Bit Position Field Description Setting 31-28 TCYC3-TCYC0 0010 One SRAM wait state (TCYC = 2) 27-11 AM27-AM11 1111.1110.0000. Address mask – 2 Megabyte window 0000.0000.0 10-7 FCM3-FCM0... -
Page 83: Appendix C: Agency Approvals
Universal I/O 32-bit Quad Serial Communications Controller. The PCI334A is certified as indicated in the following sections. If a certification is not listed below, the PCI334A may still comply. Contact Performance Technologies for current product certifications and availability. Topics covered in this chapter include: •... -
Page 84: Ce Certification
2. This device must accept any interference received, including interference that may cause undesired operation. Note: Modifications made to this device that are not approved by Performance Technologies, Inc. may void the authority granted to the user by the FCC to operate this equipment. -
Page 85: Industry Canada Class A Notice
Safety Information This section is provided as a summary of the safety recommendations throughout this manual. Performance Technologies, Incorporated (PTI) recommends that all safety precautions are followed to prevent harm to yourself or the equipment. Please follow all warnings marked on the equipment. -
Page 86: Compliance With Rohs And Weee Directives
Directive 2002/96/EC on Waste Electrical and Electronic Equipment (WEEE). This product is compliant with Directive 2002/95/EC. It may also fall under the Directive 2002/ 96/EC. Performance Technologies' complete position statements on the RoHS and WEEE Directives can be viewed on the Web at: http://pt.com/page/about-us/ehsms/. -
Page 87: Index
I n d e x addressing for endian conversion doorbell registers ....36 ....... . . 36 altera ISP connector pinouts . - Page 88 Index modes of operation ......39 direct master ......39 direct slave .
- Page 89 Index port B pin mapping (18-bit) ..... . .55 port C configuration settings ..... .56 port C pin mapping (12-bit) .
- Page 90 Index...