BBK PV420S Service Manual
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BBK PV420S Service Manual

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SERVICE MANUAL
PV420S
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  • Page 1 SERVICE MANUAL PV420S WWW.BBK.RU...
  • Page 2 CONTENTS PROJECT STRUCTURE … … … … … … … … … … … … … … ..1 SCHEMATIC DIAGRAM STRUCTUR … … … … … … … … ..2 3. KSM1000BBC TECHNICAL DATA … … … … … … … … … … .3 MM1538 DATA BOOK (instead of FAN8038) …...

  • Page 3: Project Structure

    (with Lcd display) (Filter) HEADPHONE (Converter) PV420S Project Structure Diagram Briefness introduce main part of system Pickup KSM-1000BBC CD-deck compatible with CD, CD-R, CD-RW,Can be playing 12 cm & 8cm Discs. 3-Beam Head Amp IC RF AMP The CXA2550N is of SONY, Compatible with CD, CD-R.
  • Page 4 VCC3 R122 R121 POW_DCIN 3904 R119 WM8714 4.7K BH3544 AUD_DEM LOUT L_PHONE L_PHONE AUD_BLCK AUD_BLCK AUD_LRCK AUD_LRCK ROUT R_PHONE R_PHONE AUD_DATA AUD_DATA SERVO AUD_XCLK AUD_XCLK SERVO PART AUD_DEM POW_STB POW_STB CD_XRST CD_XRST SPCA717 CD_SCOR CD_SCOR CD_C2PO CD_C2PO VID_RST VID_RST CD_SENS CD_SENS VID_P/N VID_P/N...
  • Page 5 MODEL: KSM1000BBC PAGE: 1 技 術 資 料  TECHNICAL  DATA KSM1000BBC M O D E L   : ＊ 当該モデルの参考資料であり、この資料の内容は将来変更する   可能性があります Sony reserves the right to change specification of products and  discontinue products without notice. 担 当 者 印  ソニー株式会社 光デバイス事業部 S O N Y   C O R P O R A T I O N   O P T I C A L   D E V I C E   D I V I S I O N...
  • Page 6 MODEL:KSM1000BBC PAGE: − 目 次 − CONTENTS １）適 用 Scope Of  Document General Specifications ２）仕 様 Optical Specifications     2-1. 光学的仕様 Mechanical Specifications     2-2. 機械的仕様 Electrical Specifications Of Pick-up     2-3. ピックアップ部電気的仕様 Evaluation Conditions ３）評価条件 Position     3-1. 姿勢 Environment     3-2. 環境 Equipment     3-3. 機器 Disc     3-4. ディスク Voltage     3-5. 電圧 Characteristics Specifications ４）特性規格 Absolute Maximum Rating     4-1. 絶対最大定格       4-2. 使用電圧範囲 Operating Voltage Range       4-3. 性能規格 Performance Specifications Reliability Standard ５）信頼性保証基準 Reliability Standard     5-1. 信頼性保証基準 Reliability Specifications     5-2. 信頼性保証規格 Markings ６）表 示...
  • Page 7 MODEL:KSM1000BBC PAGE: １）適 用 Scope of Document ◆ 本仕様書は、コンパクトディスク用光学ドライブユニットＫＳＭ１０００ＢＢＣに     ついて規定します。なお、業務用には使用できません。 This document describes the specification of drive unit KSM1000BBC, for use  in compact disc player.  This model is not for professional use. ◆ 本仕様書の内容において改善の為、双方事前に協議して変更することが     あります。 The provisions of this document may be altered upon agreement between both  parties. ◆ 不都合事項発生時は、本仕様書記載事項にもとづき双方協議の上、解決   実施するものとします。 If any disagreement should arise, these two parties shall meet in good faith to resolve the problem. ◆ 本仕様書を満足する範囲内において、改良・性能の向上の為、部品等の   一部を変更する場合がありますので御了承下さい。 Within the range of these specifications, parts are subject to change without notice for technical improvement. ◆ 次の事項をお守りの上で、当デバイスを組み込んだセット商品あるいは   半完成品を市場に出荷して下さい。お守り頂けない場合、当社では責任を     負うことが出来ません。 Please be sure to observe the following each time you deliver your finished and  /or semi-finished products containing the device(s). Otherwise, SONY may not be  able to assume the responsibility for things to happen.           ・本仕様書に定めた条件以内で使用して下さい。                 Always use the device(s) within conditions given in the specifications.    ・当デバイスに追加工を行わないで下さい。       Never given additional process to the device(s).    ・セットと一体で不要輻射を測定して、規制値を満足していることを...
  • Page 8 MODEL:KSM1000BBC PAGE: ２）仕 様 General Specifications 2-1. 光学的仕様 Optical Specifications ◆  対物レンズ Objective lens 焦点距離 Effective focal length (f)  3.85 mm 開口数 Numerical aperture (NA)  0.45 作動距離 Working distance (WD)  1.8 mm ◆  半導体レーザー Semiconductor laser Laser wavelength(λ) レーザー波長 775 〜 815 nm ◆  サーボエラー信号の検出法 Servo error detection methods フォーカスエラー                ：ＳＳＤ法 Focus error SSD method トラッキングエラー              ：３スポット法 Tracking error 3-SPOT method 2-2. 機械的仕様 Mechanical Specifications Figure 2 ◆  外形寸法 Dimensions ◆  質 量 Mass （標準値）...
  • Page 9 MODEL:KSM1000BBC PAGE: ◆  送り動作 Slide direction 送りモータ端子 ① にプラス電圧が印加された場合、ピックアップはディスクの 外周方向へ動く。 A positive voltage applied to pin ① of sled motor moves the objective lens toward  the outer of the disc.  ◆  ピックアップ可動範囲  Pick-up movable distance 機械的内周位置        Mechanical center position              ≦ 24 mm 機械的最外周位置  Mechanical the most periphery position        ＞ 58 mm （ターンテーブルセンターから対物レンズセンターまでの距離） Length between the center of turntable and objective lens ◆  ターンテーブル動作 Direction of  turntable movement スピンドルモータ端子⑤にプラス電圧が印加された場合、ターンテーブルは 時計方向に回転する。 A positive voltage applied to pin ⑤ of spindle motor rotates the turntable clockwise. 2-3. ピックアップ部電気的仕様 Electrical Specifications of Pick-up    仕   様 項   目 Item Specifications 片 電 源  レーザー部電源 Power supply for LD Single power supply 電圧出力 フォトディテクタ部信号出力...
  • Page 10 MODEL:KSM1000BBC PAGE: ３）評価条件 Evaluation Conditions Position 3-1. 姿 勢 重力方向が、図１のＺ軸（−）方向にて規定します。 The negative Z axis is defined as the direction of gravity as shown in  Figure 1. Environment 3-2. 環 境 ◆ 温 度 Temperature 22 ± 2  ℃ 50 ± 5  % RH ◆ 湿 度  Relative Humidity 但し、判定に疑義が生じない場合には、下記条件で評価してよい。 If no errors occur in evaluation, the following range of conditions is acceptable.  温 度 Temperature 15 〜 35 ℃  湿 度  Relative Humidity 45 〜 85 % RH 3-3. 機 器 Equipment ◆ 測定用標準基台          Standard cabinet for measurement ◆ ＡＰＣ回路  (Figure 4)       APC circuit ◆ 標準評価回路  (Figure 5)       Standard measurement circuit ◆ ジッターメーター Jitter meter                                                  (菊水電子工業製，KJM-6235SA)    (KJM-6235SA, KIKUSUI ELE.CO.) ◆ デジタルマルチメータ...
  • Page 11 MODEL:KSM1000BBC PAGE: ４）特性規格 Characteristics Specifications 4-1. 絶対最大定格 Absolute Maximum Rating ◆ ２軸部 Actuator  項    目 規  格 備  考 Item Standard value Remarks フォーカス 但しﾌｫｰｶｽ＋ﾄﾗｯｷﾝｸﾞの総電流が Focus コイル許容電流 150mAを越えないこと 150 mA RMS Coil current トラッキング Focus ＋Tracking total current Tracking must be less than 150mA RMS Laser diode  ◆ レーザーダイオード部 項    目 規  格 備  考 Item Standard value Remarks レーザーダイオード逆電圧 2 V Laser diode inverse voltage ﾓﾆﾀｰ用ﾋﾟﾝﾌｫﾄﾀﾞｲｵｰﾄﾞ逆電圧 15 V Monitor pin photo diode  inverse voltage ◆ ＰＤＩＣ部...

  • Page 12: Fo-Op

    MODEL:KSM1000BBC PAGE: 4-3. 性能規格 Performance Specifications 4-3-1. 光学ピックアップ部 Optical Pick-up 低温，高温動作規格は、常温常湿における実測値からの変化量 ２軸部 Actuator （但し、*は変化率）を示す。 Temperature deviation from room temperature and humidity measurement. (* : Deviation percentage) 規  格 温 度 変 化 項    目 Standard value Temperature Deviation 備   考 常 温 常 湿 Remarks Item - 5℃ + 55℃ Room temperature and humidity 直流抵抗 フ 6 ± 1Ω DC resistance ォ ｜ within within 低域感度 ５Ｈｚにて規定 ＋0.65 mm/V 1.5  カ Specified at 5Hz ±35%以内 ±35%以内...
  • Page 13 MODEL:KSM1000BBC PAGE: 低温，高温動作規格は、常温常湿における実測値からの変化量 光学部 Optics （但し、*印は変化量、**印は実測値）を示す。 Temperature deviation from room temperature and humidity measurement. (* : Deviation percentage  ** : Actually measured value) ◆ ＲＦ信号 RF signal 規  格 温 度 変 化 Standard value Temperature Deviation 項  目 備   考 常 温 常 湿 Item Remarks   - 5℃ + 55℃ Room temperature and humidity ＡＰＣの温特は含まず within within RF 信号振幅 1.0 ± 0.2 Vp-p APC temperature  ±20%以内 ±20%以内 RF signal amplitude characteristics excluded ジッター 26ns RMS以下 34ns RMS以下         32.5ns RMS以下         Jitter  or less or less or less within ...
  • Page 14 MODEL:KSM1000BBC PAGE: ◆ トラッキングエラー信号 Tracking error signal 規  格 温 度 変 化 項  目 備   考 Standard value Temperature Deviation 常 温 常 湿 Item Remarks - 5℃ + 55℃ Room temperature   and humidity within within  ﾄﾗｯｷﾝｸﾞｴﾗｰ信号振幅 14.5±7.5Vp-p ± 30% 以内 ± 30% 以内 Tracking error signal amplitude ＴＰＰバランス＝  × 100% TPP balance EFバランス within within within  EF balance 0±35% 以内 0±35% 以内 0±30% 以内 ★ ★トラッキングエラー信号の中心 The center of tracking error signal within within within ...
  • Page 15 MODEL:KSM1000BBC PAGE: 4-3-2. ターンテーブル部 Turntable unit 項    目 規   格 備  考 Item Standard value Remarks ターンテーブル高さ インシュレーター取り付け面より 6.1±0.2  mm Height of turntable From insulator fixing surface ターンテーブル面振れ 0.07 mm 以下 or less Surface vibrations of turntable ターンテーブル最大耐圧荷重 98 N 以上 or more Maximum load of turntable 4-3-3. 送り機構部 Sled mechanism 規  格 温 度 変 化 Standard value Temperature Deviation 備  考 項   目 常 温 常 湿 Remarks Item - 5℃ + 55℃ Room temperature   and humidity 最低起動電圧 1.0 V 以下...
  • Page 16 MODEL:KSM1000BBC PAGE: ５）信頼性保証基準 Reliability Standard 5-1. 信頼性保証基準 Reliability Standard ◆ 動作温度 Operating Temperature 温 度    Temperature  ： -5 〜 55 ℃ 高温又は低温時に於ける動作特性は、性能規格に示す。 非動作にて４ｈ放置後、測定する。 但し、結露させないこと。 The operating characteristics at -5℃ and 55℃ are expressed as deviations from standard values as shown in the performance specifications. Leave the  pick-up in the idle state within the above temperature range for four hours.   Do not let condensation to form on the mechanism. ◆ 保存温度 Storage Temperature 温 度    Temperature  ： -30 〜 60 ℃ 上記環境に２４ｈ放置し、常温に戻して１６ｈ以上放置後の初期値に対する 特性変化は、信頼性保証規格の範囲内とする。 但し、結露させないこと。 Leave the pick-up at temperatures in the above range for 24 hours and then at room temperature for over 16 hours.  After the test, the deviation of characteristics from the standard values must be within the tolerance specified in the reliability  specifications.   Do not let condensation to form on the mechanism. Storage in hot and humid conditions ◆ 高温高湿保存 温 度    Temperature  ： 60 ℃ 湿 度    Humidity     ： 90％ 上記環境に４８ｈ放置し、常温に戻して１６ｈ以上放置後の初期値に対する 特性変化は、信頼性保証規格の範囲内とする。 但し、結露させないこと。 Leave the pick-up at temperatures in the above range for 48 hours and then at room temperature for over 16 hours.  After the test, the deviation of characteristics from the standard values must be within the tolerance specified in the reliability  specifications.   Do not let condensation to form on the mechanism. Vibration ◆ 単体振動 振 動 ： 23.6m/s   ｛ 2.4G｝ , 7〜30Hz 直線スイープ, ３方向 linear sweep, three directions Conditions 上記振動を各方向１５分（スイープ時間は往復で５分）印加後の初期値に...
  • Page 17 MODEL:KSM1000BBC PAGE: Impact ◆ 単体衝撃 衝 撃 ： 2,940m/s   ｛ 300G｝   1.6mSec, ±Ｘ ， ±Ｙ ， ±Ｚ 方向 directions Conditions 上記振動を各方向１回印加後の初期値に対する特性変化は、信頼性保証規格の 範囲内とする。  Subject the drive unit to above impact in each direction.   After the test, the deviation  of characteristics from the standard values must be within the tolerance specified in  the reliability specifications.    ◆ レーザーダイオードの寿命 Service life of laser diode ２５℃，３,０００ｈ動作にて、不良率０.１％以下。 （但し、静電破壊等による事故を除く） Percent defective : 0.1% max after 3,000 hours operation at 25℃                     (excluding damage due to electrostatic discharge)    ◆ スピンドルモータ寿命 Service life of spindle motor 再生時間１,０００ｈ経過後、スピンドルモータの消費電流は、...
  • Page 18 MODEL:KSM1000BBC PAGE: 5-2. 信頼性保証規格 Reliability Specifications 信頼性保証条件で評価後の変化量；動作試験は除く。 但し、＊印は実測値を表わす。 Deviations after evaluation tests under the conditions specified on reliability  test except operating temperature test.(＊: Actually measured value)  ２軸可動部 Actuator 項     目 規   格 Item Standard value 低域感度 Sensitivity ± 25 % 以内 within ± 25 %  フォ−カス 共振周波数 (fo) ± 6 Hz 以内 within ± 6 Hz  Resonant frequency Focus Ｑ  値 Q-value ± 6 dB 以内 within ± 6 dB  低域感度 Sensitivity ± 25 % 以内 within ± 25 %  トラッキング ± 7 Hz 以内 within ± 7 Hz  共振周波数 (fo) Resonant frequency Tracking Ｑ  値 Q-value ± 6 dB 以内...
  • Page 19 MODEL:KSM1000BBC PAGE: 送り機構部 Sled mechanism 項    目 規  格 備  考 Item Standard value Remarks 最低起動電圧 1.2 V 以下 ＊ Minimum starting voltage or less 送り時間 ＊ 3 sec  以下 Sled time or less 印加電圧 1.5 V Applied voltage 1.5V 消費電流 ＊ 210 mA 以下 Current consumption or less FO-OP-94094...
  • Page 20 MODEL:KSM1000BBC PAGE: ６）表 示 Markings Stamp 6-1. 捺 印 日 月 西暦年号の末尾 品質管理No. 英字又は数字 Alphabet Last digit Quality ○○○○○○ ○○ Month of year control No. Number Lot No. ○ ○ ○ ○ ○ ○ ○ ○ 但し、月表示の10, 11, 12はX, Y, Zで表わす。 X,Y and Z signify October, November and December respectively. 末尾の英字は、製造所の管理に用いる場合がある。 但し、桁数は０〜３桁迄とする。 The last alphabet is for management purposes in the factory.  Use up to three characters. Position of label 6-2. 表示場所 Fig.1の各部名称参照。 Refer to Fig 1. Description of components. FO-OP-94094...
  • Page 21 MODEL:KSM1000BBC PAGE: ７）梱包仕様 Package Specifications ＭＤカバー MD cover ① 本機種を保護シートに入れる。 Set into protection sheet. ＭＤケース MD case 保護シート Protection sheet ② ＭＤケースに１００個(50×2列)収納する。 Set into MD case.  50 pcs×2 lines (Total 100 pcs) マスターカートン Master carton ＭＤカバー ＰＰテープ MD cover PP tape ＭＤケース MD case 出荷ラベル Shipping label FO-OP-94094...
  • Page 22 MODEL:KSM1000BBC PAGE: ８）付 図 Attachment Figure 1. 各部の名称 Description of components ターンテーブル Turntable 光学ピックアップ Optical pick-up ＭＤシャーシ MD chassis 機種名 Lot No.捺印箇所 Stamping area of  Model name and Lot NO. Z軸 (＋）  axis      X軸 (＋）  axis   Y軸 (＋）  axis FO-OP-94094...
  • Page 23 MODEL:KSM1000BBC PAGE: Figure 2. 外形図 Appearance Drawing Note 1) To the bottom of chassis 一般公差：±０．３ To the bottom of motor General Tolerance : ±0.3 注１)推奨フレキ位置 Note 1) Recommended FPC position   FO-OP-94094...
  • Page 24 MODEL:KSM1000BBC PAGE: Figure 3. コネクター結線図 Pin connection diagram １.フレキ端子 FPC Terminal ﾎﾛｸﾞﾗﾑﾕﾆｯﾄ ピンNo. 端子名称 Hologram Unit Pin No. Terminal  GND (Vcc) GND (LD) Mon out GND (PDIC) FCS+ TRK- TRK+ FCS- 推奨コネクター：エルコインターナショナル  6224シリーズ Recommended connector : Product of ELCO INTERNATIONAL CO., LTD. Series 6224 フォーカスエラー 信号：PD1 - PD2 トラッキングエラー信号：E - F RF        信号：PD1 + PD2 Housing Terminal ２.ハウジング端子 ピンNo. 端子名称 Pin No. Terminal  １ SLED + SLED - ２ ３ LIMIT SW ４ LIMIT SW   SLD Mo.
  • Page 25 MODEL:KSM1000BBC PAGE: Figure 4. ＡＰＣ回路参考図 APC Circuit diagram (Reference) ＩＣ ： ＣＸＡ−１０８１Ｍ ＴＲ１：２ＳＢ７３１ Ｄ１ ：１Ｓ１５５５ FO-OP-94094...
  • Page 26 MODEL:KSM1000BBC PAGE: Figure 5. 標準評価回路図 Standard test circuit diagram (PD1) (PD2) 470k 150k 150k 470k 470k 150k 150k 470k PD1 + PD2 PD1 - PD2 FO-OP-94094...
  • Page 27 MODEL:KSM1000BBC PAGE: Figure 6. スピンドルモータ代表特性（三洋精密製モータ） Major characteristics of Spindle motor (Made by SANYO SEIMITSU)  ◆ 標準使用状態及び電気的特性（参考値） Standard operating conditions and electrical characteristics (for reference) 定格電圧（ＤＣ） Rated voltage (DC) 2.0  V 標準使用状態 使用電圧範囲（モータ端子間：ＤＣ） Standard  1.0 〜 3.0  V Used voltage range (between motor terminals : DC) operating  conditions 定格負荷 Rated load 0.49 mN・ m  定格負荷回転数 定格電圧，定格負荷にて 2300 ± 345 r/min Speed At rated voltage and load 定格負荷電流 定格電圧，定格負荷にて 145  mA 以下 電気的特性 Current At rated voltage and load or less Electrical  characteristics 始動トルク 定格電圧，巻き上げ法にて 1.37 mN・ m 以上 Initial torque or more At rated voltage and by winding-up method 始動電流...
  • Page 28 MODEL:KSM1000BBC PAGE: Figure 7.    送りモータ代表特性（マブチ製モータ） Major characteristics of Sled motor  (Made by MABUCHI) ◆ 標準使用状態及び電気的特性（参考値） Standard operating conditions and electrical characteristics (for reference) 定格電圧（ＤＣ） Rated voltage (DC) 1.5 VDC 標準使用状態 使用電圧範囲（モータ端子間：ＤＣ） 1.5 〜 3.0  V Standard  Used voltage range (between motor terminals :DC) operating  conditions 定格負荷 Rated load 0.0981 mN・ m 定格負荷回転数 定格電圧，定格負荷にて 7550 ± 2300 min Speed At rated voltage and load 定格負荷電流 定格電圧，定格負荷にて 180  mA 以下 電気的特性 Current At rated voltage and load or less Electrical  characteristics 始動トルク 定格電圧，２点法 0.196 mN・ m 以上 Initial torque or more At rated voltage and by 2points 始動電流...
  • Page 29 MODEL:KSM1000BBC PAGE: ９）その他 Others 9-1. 使用上の注意 Precautions in use ◆ ＡＰＣ回路 APC Circuit レーザーダイオード（ＬＤ）は、温度により光出力が大きく変化しますので、 ＬＤに内蔵のモニターフォトダイオードを使用し、光出力の補正を行って下さい。 モニターフォトダイオードのバラツキを無くすため、ピックアップに付属する ＶＲは、光出力とモニターフォトダイオードの関係をＲＦ出力一定になるように 調節して有ります。 付属の標準評価回路を用いた時、ＲＦレベルは１ Vp-pになります。 The output laser power must be controlled with the built-in monitor photodiode, since laser power changes with temperature.   To prevent the characteristics  dispersion of the monitor photodiode, the relation between the potentiometer (VR)  attached to the pick-up and the monitor photodiode is factory adjusted so that the  RFoutput will be constant. RF level will be 1 Vp-p when the attached standard test circuit is used. ◆ 結 線 Connections 結線は、必らず指定形状のフレキシブル基板を使用してください。 フォトダイオードからのハーネス近くにマイコン等のデジタルノイズ源が 有りますと、アイパターンが劣化することが有りますので注意して下さい。 ２軸，レーザーダイオードコネクターに関する結線に接触不良が有りますと、 レーザー劣化の原因となりますので、コネクター等のゆるみがないように して下さい。 Use the specified connectors for electrical connections. The eye pattern may deteriorate if a digital noise source such as a microcomputer is positioned near the harness from the photodiode.   The laser may deteriorate if  the actuator or laser diode connection is poor; securely connect these connecters. Short - circuit of GND ◆ ＧＮＤ の短絡 ピンNo.3（ GND(Vcc)） 、 ピンNo.6（ GND(LD)） 、 ピンNo.12（ GND(PDIC)） は ピックアップ内でオープン（開放）となっているため、必ずセット回路内で...
  • Page 30 MODEL:KSM1000BBC PAGE: 9-2. 取り扱い注意事項 Handling instructions 本機種は、当社の専門工場にて組立調整されております。 安易に分解、調整等を行わないで下さい。 取り扱いに関して次の点に注意して下さい。 又、サービス，ユーザー等にも 注意する措置をお願い致します。 This model is assembled and precisely adjusted in our special plant. Never attempt to disassemble or readjust it. Pay attention to the following instructions when handling this model.  Please inform service personnel and users about it. General ◆ 一 般 Storage 保 管 高温高湿下， ホコリ の多い所での保存は避けて下さ い。 Avoid storing this model in hot, humid or dusty conditions. Handling 取り扱い 精密に調整されていますので、落下や不用意な取り扱いによる衝撃が 加わらないようにして下さい。 This model is a precise unit.  Be careful not to subject it to shocks by dropping  or rough handling. ◆ レーザーダイオード Laser diode レーザー光に対する目の保護 Shield your eyes from the laser beam ＬＤの出力は、対物レンズ出射出力でMAX１ ｍＷですが、集光された所では 2  約0.7×10  W/cm に達します。  動作中のＬＤを直視したり、あるいは他の レンズやミラーを介して光束を観察すると危険ですから、絶対に行わないで 下さい。  もし観察するときは、赤外線ビューアーかＩＴＶカメラを使用して下さい。 The output from the LD is only 1mW maximum after going through the objective ...
  • Page 31 MODEL:KSM1000BBC PAGE: サージ電流，静電気による破壊 Avoid current surges and electrostatic discharges ＬＤに大電流を流すと、きわめて短時間であっても自身が発する強い光によって 劣化が促進され、或いは破壊します。 ＬＤ駆動回路には、スイッチ，その他に よるサージ電流が流れないようにして下さい。 又、不注意に扱うと人体からの 静電気が加わって瞬時に破壊されてしまいます。 ＬＤの端子は、出荷時に輸送 による静電気破壊防止のため、ショートされています。 更に安全を期するため 取り付け時、人体アース，計測器及び治工具のアースを必ず行って下さい。 又、作業台や床等にアースマットを用いて接地することが望ましい。 ショート部の解放は、コネクター差し込み後、半田ゴテで行って下さい。 使用する半田ゴテは、金属部分が接地されたもの、或いは通電５分後の絶縁抵抗が 10MΩ以上(DC 500V)のもので、半田ゴテ先温度が320℃以下(30W)のものを使用し、 すみやかに行って下さい。 The LD may deteriorated if its output is too high and damage may occur if it is exposed  to large currents for even a short time.   Protect the LD drive circuit from current surges  caused by switches or other sources.   An electrostatic discharge from the human body  may destroy the LD instantaneously if it is handled carelessly.   LD terminals are factory -strapped before shipment to protect LD from electrostatic discharges during transportation.    For safe handling of the LD, ground your body, measuring equipment, jigs, and tools during  installation.   Use of a grounding mat on the workbench and floor is recommended.   After  connector insertion, unstrap the LD terminal with a soldering iron with its metallic tip  grounded or worse insulation resistance is 10 megohms or more (at 500V DC) five minutes after it is tuned on.   The temperature of the soldering iron tip must be 320℃ or below (30W) and the unstrapping should be performed quickly. Vcc無通電状態でのLD通電による破損 Avoid the application of current to LD in the case when voltage is not applied to Vcc Vccに規定の電圧が通電されていない状態でLDに通電しますと、素子の回路が 動作せず、LDに過電流が流れてLD劣化を引き起こします。 Vccに無通電の状態でLDに通電することが無きよう、ご注意願います。 LD may deteriorate if the current is applied to LD in the case when the regulated voltage  is not applied to Vcc, because the circuit of element does not operate and LD is applied  over current.  Do not apply the current to LD with voltage is not applied to Vcc.  ◆ ２軸部 Actuator アクチュエータ Actuator アクチュエータ部は強力な磁気回路を有していますので、磁性体が近づきすぎ ますと特性が変化します。 又、すきまから異物が入ることの無いようにして 下さい。...
  • Page 32 MODEL:KSM1000BBC PAGE: 9-3. 安全規格対象部品 Conformity of main parts to safety standards(UL standard) 本機種は、各国安全規格に準じて設計されておりますが、使われ方により承認が決まるめ、 単体での承認はされておりません。 安全規格については、セットでの承認申請及び確認を お願い致します。 This model is designed to conform with the safety standards of various countries.   Since approval  depends on the mode of use, however, it is not approved as a unit.   Therefore, apply for approval  after mounting the optical drive unit in a player and check it for safety after mounting, too.  ◆  光学ピックアップ部  Optical Pick-up Generic  Parts Name Material Manufacturer Grade Type No.  ID Mark   Name HOEﾌﾚｷｼﾌﾞﾙ基板 SI FLEX CO LTD 94V-0 F5a▲ HOE FPC DAINIPPON INK &  94V-0 FZ-3000-X0                CHEMICALS INC スライドベ−ス Slide base SUMITOMO BAKELITE CO LTD 94V-0 FM-MK113 ◆ ドライブユニット部 Drive unit Generic  Parts Name Material Manufacturer Grade Type No. ...
  • Page 33 4ch Moter driver IC for Portable CD Player MITSUMI 4-ch Motor Driver for Portable CD Players Monolithic IC MM1538 Outline This driver IC contains a 4ch H bridge driver and DC-DC converter control circuit on one chip, and was developed for use in portable CD players. QFP-44 is used for the package, making it ideal for smaller sets. Features (1) Built-in 4ch H bridge driver, and PWM control of load drive voltage is made possible by external components.

  • Page 34: Reset

    4ch Moter driver IC for Portable CD Player MITSUMI Block Diagram RCHG OUTIR OUT1F OUT2R OUT2F POWGND OUT3F OUT3R OUT4F OUT4R BRAKE1 BRAKE1 AMUTE MUTE2 HVcc MUTE34 MAXIMUM DETECTION START Vref VSYS2 CHGVcc OVER-VOLTAGE TRIANGLE WAVE PRE-DRIVER POWER SUPPLY PREGND VSYS1 PWMFIL BSEN...

  • Page 35: Table Of Contents

    4ch Moter driver IC for Portable CD Player MITSUMI Pin Assignment RCHG OUT1R OUT1F OUT2R OUT2F POWGND OUT3F OUT3R OUT4F OUT4R BRAKE1 AMUTE MUTE2 MUTE34 MM1538XQ START Vref CHGV VSYS2 PREGND OPOUT PWMFIL VSYS1 BSEN BATT RESET DEAD SPRT N.C. BSEN BRAKE1 BATT...
  • Page 36 4ch Moter driver IC for Portable CD Player MITSUMI Pin Description Pin No. Pin Name Input/Output Function Internal Equivalent Circuit BSEN Input Battery Voltage Monitor 16.5kΩ 71kΩ 20kΩ 10.5kΩ 14.85kΩ BATT Input Battery Power Supply Input Power Supply RESET Output Reset Detect Output VSYS1 90kΩ...
  • Page 37 4ch Moter driver IC for Portable CD Player MITSUMI Pin Description Pin No. Pin Name Input/Output Function Internal Equivalent Circuit Input Error Amplifier Input VSYS1 35kΩ 21.6kΩ SPRT Output Short Circuit Protection VSYS1 Setting 220kΩ Output Triangular-Wave Output BATT VSYS1 2kΩ...
  • Page 38 4ch Moter driver IC for Portable CD Player MITSUMI Pin Description Pin No. Pin Name Input/Output Function Internal Equivalent Circuit VSYS2 Input Driver Pre-step Power Supply Pre-Drive Power Supply Vref Input Reference Voltage Input 200Ω 24kΩ 50kΩ Input ch3 Control Signal Input ch4 Control Signal Input 11kΩ...
  • Page 39 4ch Moter driver IC for Portable CD Player MITSUMI Pin Description Pin No. Pin Name Input/Output Function Internal Equivalent Circuit AMUTE Output Reset Invert Output BATT 95kΩ Output Empty Detect Output Output PWM Transistor Drive BATT 50Ω Input External Clock Synchronizing VSYS1 Input 2kΩ...
  • Page 40 4ch Moter driver IC for Portable CD Player MITSUMI Pin Description Pin No. Pin Name Input/Output Function Internal Equivalent Circuit CHGV Input Charging Circuit Power Supply Charging Circuit Power Supply Input Input Empty Detect Level Switch BATT 200kΩ Output 130kΩ 15kΩ...
  • Page 41 4ch Moter driver IC for Portable CD Player MITSUMI Absolute Maximam Ratings (Ta=25°C) Item Symbol Rating Unit Supply Voltage 13.5 Driver Output Current 625 *2 Power Dissipation –30 ~ +85 °C Operating Temperature –55 ~ +150 °C Storage Temperature *1 Vcc shows input voltage of VSYS1,VSYS2,HVcc,BATT,and CHGVcc. *2 Reduced by 5mW for each increase in Ta of 1°C over 25°C.

  • Page 42: Sprt

    4ch Moter driver IC for Portable CD Player MITSUMI (unless otherwise specified, Ta=25°C , BATT=2.4V, VSYS1=VSYS2=3.2V,Vref=1.6V, Electrical Characteristics CHGVcc=0V,fCLK=88.2kHz) Item Symbol Measurement Conditions Min. Typ. Max. Unit <H-Bridge Driver Part> IN2=1.8V MUTE2 OFF Threshold Voltage M2OFF IN3=IN4=1.8V MUTE34 ON Threshold Voltage M34ON IN3=IN4=1.8V MUTE34 OFF Threshold Voltage...

  • Page 43: Amute

    4ch Moter driver IC for Portable CD Player MITSUMI (unless otherwise specified, Ta=25°C , BATT=2.4V, VSYS1=VSYS2=3.2V,Vref=1.6V, Electrical Characteristics CHGVcc=0V,fCLK=88.2kHz) Item Symbol Measurement Conditions Min. Typ. Max. Unit <Interface> START=0V µA START Pin Bias Current START CLK Pin Threshold Voltage"H" CLKTHH CLK Pin Threshold Voltage"L"...

  • Page 44: Opout

    4ch Moter driver IC for Portable CD Player MITSUMI (unless otherwise specified, Ta=25°C , BATT=2.4V, VSYS1=VSYS2=3.2V,Vref=1.6V, Electrical Characteristics CHGVcc=0V,fCLK=88.2kHz) Item Symbol Measurement Conditions Min. Typ. Max. Unit <Battery Charging Circuit> CHGV =4.5V, RCHG=0.5 and 0.6V 0.75 0.95 1.20 kΩ RCHG Pin Output Resistance RCHG CHGV =4.5V, RCHG=OPEN, BATT=4.5V...
  • Page 45 4ch Moter driver IC for Portable CD Player MITSUMI Switching Position Table SW No. Item BATT Stand-by Current BATT Supply Current (No load) VSYS1 Supply Current (No load) VSYS2 Supply Current (No load) CHGVcc Supply Current (Noload) VSYS1 Threshold Voltage EO Pin Output Voltage "H"...

  • Page 46: Vsys2

    4ch Moter driver IC for Portable CD Player MITSUMI Switching Position Table SW No. Item DEAD Pin Impedance DEAD Pin Output Voltage OFF Pin Threshold Voltage OFF Pin Bias Current START Pin ON Threshold Voltage START Pin OFF Threshold Voltage START Pin Bias Current CLK Pin Threshold Voltage"H"...
  • Page 47 4ch Moter driver IC for Portable CD Player MITSUMI Switching Position Table SW No. Item EMP Detection Voltage 1 EMP Detection Voltage 2 EMP Detection Hysteresis Voltage 1 EMP Detection Hysteresis Voltage 2 EMP Pin Output Voltage EMP Pin Output Leak Current BSEN Pin Input Resistance BSEN Pin Leak Current SEL Pin Detection Voltage...
  • Page 48 4ch Moter driver IC for Portable CD Player MITSUMI Switching Position Table SW No. Item ch1R ch2R Voltage Gain ch3R ch4R Gain Error By Polarity Input pin resistance ch1R ch2R Maximum Output Voltage ch3R ch4R ch1F ch1R ch2F ch2R Saturation Voltage (Lower) ch3F ch3R ch4F...

  • Page 49: Vref

    4ch Moter driver IC for Portable CD Player MITSUMI Switching Position Table SW No. Item BRAKE1 ON Voltage BRAKE1 OFF Voltage MUTE2 ON Voltage MUTE2 OFF Voltage MUTE34 ON Voltage MUTE34 OFF Voltage Vref ON Voltage Vref OFF Voltage BREAK1 Brake Current PWM Sink Current Level Shift Voltage Leak Current...
  • Page 50 4ch Moter driver IC for Portable CD Player MITSUMI Switching Position Table Dead Zone Output Offset Voltage Output voltage:V (mV) Voltage Gain (+)=20 log VO1-VO2 (-)=20 log VO3-VO4 Gain Error By Polarity (+)-G Dead Zone XC-XC'= 2·VO1-V 1·VO2 3·VO4-V 4·VO3 VO1-VO2 VO3-VO4...

  • Page 51: Hvcc

    4ch Moter driver IC for Portable CD Player MITSUMI Application Circuit TRAVERSE SPINDLE FOCUS TRACKING 1.8k BRAKE1 AMUTE MUTE2 HVcc 33µ 0.1µ 47µ MUTE34 MAXIMUM DETECTION START 0.1µ Vref 100k VSYS2 CHGVcc OVER-VOLTAGE PRE-DRIVER POWER SUPPLY TRIANGLE WAVE OPOUT PREGND VSYS1 PWMFIL 100k...

  • Page 52: Pwmfil

    4ch Moter driver IC for Portable CD Player MITSUMI Circuit operation 1 H-bridge driver block (1) Gain setting · The driver input resistance (ch 1,3 and 4) are 11kΩ typ. ,ch2 is 7.5kΩ typ. . Set the gain according to the following formula.
  • Page 53 4ch Moter driver IC for Portable CD Player MITSUMI 3 DC-DC converter block (1) Output voltage · 3.2V typ. voltage multiplier circuit can be constructed using external components. This voltage can be varied with the addition of an external resistor. The setting method is as follows. R1 ·...

  • Page 54: Bsen(

    4ch Moter driver IC for Portable CD Player MITSUMI (5) Over voltage protection circuit · When the voltage applied to BSEN(1PIN)reaches 8.4V typ. , SPRT(8PIN)is charged, and when the voltage reaches 1.2V typ. , theSW(5PIN)switching stops. The time until switching stops is set by the capacitor connected to SPRT(8PIN)according to the following formula.
  • Page 55 4ch Moter driver IC for Portable CD Player MITSUMI Characteristics Input Load Fluctuation =∞ 4Ω 8Ω 20Ω Ta=normal temperature • BATT=HV • 8Ω 4Ω VSYS1=VSYS2=3.2V • Vref=1.6V • ∞ 20Ω -0.8 -0.6 -0.4 -0.2 Input voltage:V Input Load Fluctuation (ch2) =∞...
  • Page 56 4ch Moter driver IC for Portable CD Player MITSUMI Characteristics Error Amp Output Voltage Ta=normal temperature EO PIN BATT=2.4V DAED PIN Control Circuit Power Supply voltage:VSYS1(V) Resete Pin Voltage Ta=normal temperature BATT=2.4V Control Circuit Power Supply voltage:VSYS1(V)
  • Page 57 CXA2550M/N RF Amplifier for CD Players Description CXA2550M CXA2550N The CXA2550M/N is an IC developed for compact 20 pin SOP (Plastic) 20 pin SSOP (Plastic) disc players. This IC incorporates an RF amplifier, focus error amplifier, tracking error amplifier, APC circuit and RF level control circuit.
  • Page 58 CXA2550M/N Pin Description Symbol Description Equivalent circuit 50µ Reference level variable pin for RF level control. AGCVTH — The reference level can be varied by the external resistor. 13.4k 10µ APC amplifier output pin. 20µ 8µ APC amplifier input pin. Inversion input pin for RF I-V amplifiers.
  • Page 59 CXA2550M/N Symbol Equivalent circuit Description 260k Inversion input pin for F and E I-V amplifiers. Connect these pins to the photodiodes F and E respectively. The current is supplied. 10µ 260k — Gain adjustment pin for I-V amplifier. 200µ DC voltage output pin of (Vcc + V )/2.
  • Page 60 CXA2550M/N Symbol Equivalent circuit Description 164k Bias adjustment pin for inverted side FE_BIAS of focus error amplifier. 174k 10µ Focus error amplifier output pin. 174k 300µ RF amplifier inverted side input pin. RF amplifier gain is determined by the resistor connected between this pin and RFO pin.
  • Page 61 CXA2550M/N Symbol Equivalent circuit Description The RF amplifier output RFO is input RF I with its capacitance coupled. 20µ 50µ External time-constant pin for RF RFTC — level control. 50µ 10µ 15µ 15µ RF level control ON (limit level of 50%/30%)/OFF switching pin.
  • Page 62 CXA2550M/N –59 –...
  • Page 63 CXA2550M/N –60 –...
  • Page 64 CXA2550M/N – 61 –...
  • Page 65 CXA2550M/N Description of Functions RF Amplifier The photodiode current input to the input pins (PD1, PD2) are current-to-voltage (I-V) converted by the equivalent resistance of 58kΩ at PD I-V amplifiers, respectively. The signal is added by the RF summing amplifier and then the I-V converted output voltage of the photodiode (A + B + C + D) is output to RFO pin. This pin is used check the eye pattern.
  • Page 66 CXA2550M/N Tracking Error Amplifier Each signal current from the photodiodes E and F is I-V converted and input to Pins 7 and 8 via a resistor which determines the gain. The signal is amplified by the gain amplifier, operated by the tracking error amplifier and then the (F-E) signal is output to Pin 11.
  • Page 67 CXA2550M/N Center Voltage Generation Circuit This circuit provides the center potential when this IC is used at single power supply. The maximum current is approximately ±3mA. The output impedance is approximately 50Ω. APC & Laser Power Control 100µ 130mV 10µH LD_ON MICRO- COMPUTER...
  • Page 68 CXA2550M/N Application Circuit • For single power supply +3.5V 33µ/6.3V 5.5k 0.01µ 100µ/6.3V 10µH TRK E GAIN • For dual power supply ±1.75V 33µ/6.3V 0.01µ 5.5k 100µ/6.3V 10µH TRK E GAIN Application circuits shown are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same.
  • Page 69 CXA2550M/N • LASER POWER CONTROL (LPC) The RF level is stabilized by attaching an offset to the APC V and controlling the laser power in sync with the RF level fluctuations. The RF O and RF I levels are compared and the larger of the two is smoothed by the RFTC's external CR. This signal is then compared with the reference level.
  • Page 70 CXA2550M/N Package Outline Unit: mm CXA2550M 20PIN SOP (PLASTIC) 300mil + 0.4 + 0.4 12.45 – 0.1 1.85 – 0.15 0.15 + 0.2 0.1 – 0.05 + 0.1 0.45 ± 0.1 1.27 0.2 – 0.05 ± 0.12 PACKAGE STRUCTURE PACKAGE MATERIAL EPOXY / PHENOL RESIN LEAD TREATMENT SOLDER PLATING...
  • Page 71 CXD3068Q CD Digital Signal Processor with Built-in Digital Servo Preliminary Description The CXD3068Q is a digital signal processor LSI for 80 pin QFP (Plastic) CD players. This LSI incorporates a digital servo. Features • All digital signal processings during playback are performed with a single chip •...
  • Page 72 CXD3068Q Block Diagram – 69 –...
  • Page 73 CXD3068Q Pin Configuration – 70 –...
  • Page 74 CXD3068Q Pin Description Symbol Description Digital power supply. — System reset. Reset when low. XRST Mute input (low: off, high: on) MUTE Serial data input from CPU. DATA Latch input from CPU. Serial data is latched at the falling edge. XLAT Serial data transfer clock input from CPU.
  • Page 75 CXD3068Q Symbol Description FRDR 1, 0 Focus drive output. — — Digital GND. TEST Test. Normally, GND. TES1 Test. Normally, GND. Center voltage input. Focus error signal input. Sled error signal input. Tracking error signal input. Center servo analog input. RFDC RF signal input.
  • Page 76 CXD3068Q Symbol Description Outputs a high signal when the playback disc has emphasis, and a low EMPH 1, 0 signal when there is no emphasis. Crystal selection input. Low when the crystal is 16.9344MHz; high when it is XTSL 33.8688MHz. —...
  • Page 77 CXD3068Q Electrical Characteristics 1. DC Characteristics = AV = 3.3 ± 0.3V, Vss = AVss = 0V, Topr = –20 to +75°C) Applicable Unit Item Conditions Min. Typ. Max. pins High level 0.7V ∗ , ∗ Input voltage (1) Low level 0.2V High level 0.8V...
  • Page 78 CXD3068Q 2. AC Characteristics (1) XTAI pin (a) When using self-excited oscillation (Topr = –20 to +75°C, V = AV = 3.3 ± 0.3V) Item Symbol Min. Typ. Max. Unit Oscillation frequency (b) When inputting pulses to XTAI pin (Topr = –20 to +75°C, V = AV = 3.3 ±...
  • Page 79 CXD3068Q (2) CLOK, DATA, XLAT, SQCK and EXCK pins = AV = 3.3 ± 0.3V, V = AV = 0V, Topr = –20 to +75°C) Item Symbol Min. Typ. Max. Unit Clock frequency 0.65 Clock pulse width Setup time Hold time Delay time Latch pulse width Note)
  • Page 80 CXD3068Q (3) SCLK pin Item Symbol Min. Typ. Max. Unit SCLK frequency SCLK SCLK pulse width 31.3 Delay time µs (4) COUT, MIRR and DFCT pins Operating frequency = AV = 3.3 ± 0.3V, V = AV = 0V, Topr = –20 to +75°C) Signal Symbol Min.
  • Page 81 CXD3068Q Contents [1] CPU Interface § 1-1. CPU Interface Timing ........................12 § 1-2. CPU Interface Command Table ....................12 § 1-3. CPU Command Presets ........................ 23 § 1-4. Description of SENS Signals ......................30 [2] Subcode Interface § 2-1. P to W Subcode Readout ......................58 §...

  • Page 82: Cpu Interface

    CXD3068Q [1] CPU Interface § 1-1. CPU Interface Timing • CPU interface This interface uses DATA, CLOK and XLAT to set the modes. The interface timing chart is shown below. • The internal registers are initialized by a reset when XRST = 0. Note) Be sure to set SQCK to high when XLAT is low.
  • Page 83 Command Table ($0X to 1X) Address Data 1 Data 2 Data 3 Data 4 Data 5 Reg- Command ister D23 to D20 D19 D18 D17 D16 D15 D14 D13 D12 D11 D10 FOCUS SERVO ON — — — — — —...
  • Page 84 Command Table ($2X to 3X) Address Data 1 Data 2 Data 3 Data 4 Data 5 Reg- Command ister D23 to D20 D19 D18 D17 D16 D15 D14 D13 D12 D11 D10 — — — — — — — — —...
  • Page 85 Command Table ($340X) Address 1 Address 2 Address 3 Address 4 Data 1 Data 2 Reg- Command ister D23 to D20 D19 to D16 D15 to D12 D11 D10 KRAM DATA (K00) SLED INPUT GAIN KRAM DATA (K01) SLED LOW BOOST FILTER A-H KRAM DATA (K02) SLED LOW BOOST FILTER A-L KRAM DATA (K03)
  • Page 86 Command Table ($341X) Address 1 Address 2 Address 3 Address 4 Data 1 Data 2 Reg- Command ister D23 to D20 D19 to D16 D15 to D12 D11 D10 KRAM DATA (K10) FOCUS PHASE COMPENSATE FILTER B KRAM DATA (K11) FOCUS OUTPUT GAIN KRAM DATA (K12) ANTI SHOCK INPUT GAIN...
  • Page 87 Command Table ($342X) Address 1 Address 2 Address 3 Address 4 Data 1 Data 2 Reg- Command ister D23 to D20 D19 to D16 D15 to D12 D11 D10 KRAM DATA (K20) TRACKING PHASE COMPENSATE FILTER A KRAM DATA (K21) TRACKING PHASE COMPENSATE FILTER B KRAM DATA (K22) TRACKING OUTPUT GAIN...
  • Page 88 Command Table ($343X) Address 1 Address 2 Address 3 Address 4 Data 1 Data 2 Reg- Command ister D23 to D20 D19 to D16 D15 to D12 D11 D10 KRAM DATA (K30) SLED INPUT GAIN (when TGup2 is accessed with SFSK = 1) KRAM DATA (K31) ANTI SHOCK LOW PASS FILTER B KRAM DATA (K32)
  • Page 89 Command Table ($344X) Address 1 Address 2 Address 3 Address 4 Data 1 Data 2 Reg- Command ister D23 to D20 D19 to D16 D15 to D12 D11 D10 KRAM DATA (K40) TRACKING HOLD FILTER INPUT GAIN KRAM DATA (K41) TRACKING HOLD FILTER A-H KRAM DATA (K42) TRACKING HOLD FILTER A-L...
  • Page 90 Command Table ($348X to 34FX) Address 1 Address 2 Data 1 Data 2 Data 3 Reg- Command ister D23 to D20 D19 D18 D17 D16 D14 D13 D12 D11 D10 PGFS1 PGFS0 PFOK1 PFOK0 MRT1 MRT0 PGFS, PFOK, RFAC SFBK1 SFBK2 Booster Surf Brake THBON...
  • Page 91 Command Table ($35X to 3FX) Address 1 Address 2 Data 1 Data 2 Data 3 Register Command D23〜D20 D19 D18 D17 D16 D15 D14 D13 D12 D11 D10 0011 SYG3 SYG2 SYG1 SYG0 System GAIN FZB3 FZB2 FZB1 FZB0 FZA3 FZA2 FZA1 FZA0...
  • Page 92 Command Table ($4X to EX) Address Data1 Data2 Data3 Data4 Register Command Auto sequence LSSL − − − − Blind (A, E), Brake (B), − − − − Overflow (C, G) Sled KICK, BRAKE (D), − − − − KICK (F) Auto sequence (N) track jump count 32768...

  • Page 93: Cpu Command Presets

    Command Table ($4X to EX) cont. Data 5 Data 6 Data 7 Reg- Command Address Data 1 Data 2 Data 3 Data 4 ister SCOR MODE 1 0 0 0 ERC4 SCSY SOCT1 TXON TXOUT OUTL1 OUTL0 — — — —...
  • Page 94 Command Preset Table ($348X to 34FX) Address 1 Address 2 Data 1 Data 2 Data 3 Reg- Command ister D23 to D20 D19 D18 D17 D16 D14 D13 D12 D11 D10 PGFS, PFOK, RFAC Booster Surf Brake Booster SELECT 0 0 1 1 Address 2 Data 1 Data 2...
  • Page 95 Command Preset Table ($35X to 3FX) Address1 Address2 Data1 Data2 Data3 Reg- Command ister D23〜D20 D19 D18 D17 D16 D15 D14 D13 D12 D11 D10 0011 System GAIN Address Data1 Data2 Data3 Data4 D23〜D20 D19 D18 D17 D16 D15 D14 D13 D12 D11 D10 FCS search, AGF TRK jump, AGT...
  • Page 96 Command Preset Table ($4X to EX) Address Data1 Data2 Data3 Data4 Reg- Command ister Auto sequence − − − − Blind (A, E), Brake (B), − − − − Overflow (C, G) Sled KICK, BRAKE (D), − − − − KICK (F) Auto sequence(N) track jump...
  • Page 97 Command Preset Table ($4X to EX) Data 7 Data 5 Data 6 Reg- Command Address Data 1 Data 2 Data 3 Data 4 ister MODE 1 0 0 0 — — — — specification Function — — — — 1 0 0 1 specification 0 0 ∗...
  • Page 98 CXD3068Q <Coefficient ROM Preset Values Table (1)> ADDRESS DATA CONTENTS SLED INPUT GAIN SLED LOW BOOST FILTER A-H SLED LOW BOOST FILTER A-L SLED LOW BOOST FILTER B-H SLED LOW BOOST FILTER B-L SLED OUTPUT GAIN FOCUS INPUT GAIN SLED AUTO GAIN FOCUS HIGH CUT FILTER A FOCUS HIGH CUT FILTER B FOCUS LOW BOOST FILTER A-H...
  • Page 99 CXD3068Q <Coefficient ROM Preset Values Table (2)> ADDRESS DATA CONTENTS SLED INPUT GAIN (Only when TRK Gain Up2 is accessed with SFSK = 1.) ANTI SHOCK LOW PASS FILTER B NOT USED ANTI SHOCK HIGH PASS FILTER B-H ANTI SHOCK HIGH PASS FILTER B-L ANTI SHOCK FILTER COMPARATE GAIN TRACKING GAIN UP2 HIGH CUT FILTER A TRACKING GAIN UP2 HIGH CUT FILTER B...

  • Page 100: Description Of Sens Signals

    CXD3068Q § 1-4. Description of SENS Signals SENS output Microcomputer ASEQ = 0 ASEQ = 1 Output data length serial register (latching not required) — AS (Anti Shock) — — $30 to 37 SSTP — AGOK ∗ — XAVEBSY ∗ —...
  • Page 101 CXD3068Q Description of SENS Signals SENS output The SENS pin is high impedance. XBUSY Low while the auto sequencer is in operation, high when operation terminates. Outputs the same signal as the FOK pin. High for "focus OK". High when the regenerated frame sync is obtained with the correct timing. Counts the number of tracks set with Reg.B.
  • Page 102 CXD3068Q The meaning of the data for each address is explained below. $4X commands Data 1 Data 2 Data 3 Register name Command MAX timer value Timer range LSSL Command Cancel Fine Search Focus-On 1 Track Jump 10 Track Jump 2N Track Jump M Track Move RXF = 0 Forward...
  • Page 103 CXD3068Q $6X commands Register name Data 1 Data 2 KICK (D) KICK (F) Timer 23.2ms 11.6ms 5.8ms 2.9ms When executing KICK (D) $44 or $45 11.6ms 5.8ms 2.9ms 1.45ms When executing KICK (D) $4C or $4D Timer 0.09ms KICK (F) 0.72ms 0.36ms 0.18ms...
  • Page 104 CXD3068Q $8X commands Data 1 Data 2 Command MODE DOUT DOUT WSEL ASHS SOCT0 specification Mute Mute-F SEL1 SEL2 Command bit C2PO timing Processing CDROM = 1 CDROM mode; average value interpolation and pre-value hold are not performed. CDROM = 0 Audio mode;...
  • Page 105 CXD3068Q Command bit Sync protection window width Application WSEL = 1 ±26 channel clock Anti-rolling is enhanced. WSEL = 0 ±6 channel clock Sync window protection is enhanced. ∗ In normal-speed playback, channel clock = 4.3218MHz. Command bit Function The command transfer rate to DSSP block from auto sequencer is set to normal speed. ASHS = 0 The command transfer rate to DSSP block from auto sequencer is set to half speed.
  • Page 106 CXD3068Q Command bit Processing VCOSEL2 = 0 Wide-band PLL VCO2 is set to normal speed. VCOSEL2 = 1 Wide-band PLL VCO2 is set to approximately twice the normal speed. Command bit Processing KSL1 KSL0 Output of wide-band PLL VCO2 is 1/1 frequency-divided. Output of wide-band PLL VCO2 is 1/2 frequency-divided.
  • Page 107 CXD3068Q Command bit Processing SCSY = 0 No processing. SCSY = 1 GRSCOR (protected SCOR) synchronization is applied again. ∗ Used to resynchronize GRSCOR. The rising edge signal of this commnd bit is used internally. Therefore, when resynchronizing GRSCOR, first return the setting to 0 and then set to 1.
  • Page 108 CXD3068Q Command bit Processing VCO1CS0 = 0 Multiplier PLL VCO1 low speed is selected. VCO1CS0 = 1 Multiplier PLL VCO1 high speed is selected. ∗ The CXD3068Q has two VCO1s, and this command selects one of these VCO1s. ∗ Block Diagram of VCO Internal Path VCO1 Internal Path –...
  • Page 109 CXD3068Q $9X commands Data 1 Data 2 Command Function DSPB A.SEQ BiliGL BiliGL FLFC specification ON-OFF ON-OFF MAIN Command bit Processing DSPB = 0 Normal-speed playback, C2 error quadruple correction. DSPB = 1 Double-speed playback, C2 error double correction. (quadruple correction when ERC4 = 1) FLFC is normally 0.
  • Page 110 CXD3068Q $AX commands Data 1 Data 2 Command VARI VARI Audio CTRL Mute PCT1 PCT2 SOC2 Command bit Processing VARION = 0 Variable pitch mode is turned off. (The crystal is the reference to the internal clock.) VARION = 1 Variable pitch mode is turned on.
  • Page 111 CXD3068Q Description of peak meter mode (see Timing Chart 1-5.) • When the LSI is set to this mode, the maximum PCM data value is detected regardless of if it comes from the left or right channel. The 96-bit clock must be input to SQCK to read out this data. •...
  • Page 112 CXD3068Q $AC commands (preset: $AC0C) Data 1 Data 2 Data 3 Command Sync expanding bit SFP5 SFP4 SFP3 SFP2 SFP1 SFP0 Command bit Processing AVW = 0 Automatic expanding function of sync protection window width is turned off. AVW = 1 Automatic expanding function of sync protection window width is turned on.
  • Page 113 CXD3068Q $AD commands (preset: $AD0) Data 1 Data 2 Command DSSP ASYM ADCPS (Sleep setting) SLEEP SLEEP SLEEP ADCPS: This bit sets the operating mode of the DSSP block A/D converter. When 0, the operating mode of the DSSP block A/D converter is set to normal. (default) When 1, the operating mode of the DSSP block A/D converter is set to power saving.
  • Page 114 CXD3068Q $AE commands (preset: $AE0) Data 1 Data 2 Command VARI VARI Audio CTRL Command bit Processing VARION = 0 Variable pitch mode is turned off. (The crystal is the reference to the internal clock.) VARION = 1 Variable pitch mode is turned on. (The VCO2 is the reference to the internal clock.) Command bit Processing VARIUSE = 0...
  • Page 115 CXD3068Q $CX commands Data 1 Data 2 Command Gain Gain Spindle servo Gain Gain Gain Gain PCC1 PCC0 coefficient setting MDP1 MDP0 MDS1 MDS0 DCLV0 DCLV1 Gain CLV CTRL ($DX) CLVS • CLVS mode gain setting: GCLVS Gain Gain Gain GCLVS MDS1 MDS0...
  • Page 116 CXD3068Q Data 3 Data 4 Command Spindle servo SFP3 SFP2 SFP1 SFP0 SRP3 SRP2 SRP1 SRP0 coefficient setting Command bit Processing SFP3 to 0 Sets the frame sync forward protection times. The setting range is 1 to F (Hex). Command bit Processing SRP3 to 0 Sets the frame sync backward protection times.
  • Page 117 CXD3068Q Error monitor commands Command bit Processing EDC7 = 0 EDC6 The [No C1 errors, pointer reset] count is output when 0. EDC5 The [One C1 error corrected, pointer reset] count is output when 0. EDC4 The [No C1 errors, pointer set] count is output when 0. EDC3 The [One C1 error corrected, pointer set] count is output when 0.
  • Page 118 CXD3068Q Data 2 Data 3 Data 4 Command CLV CTRL CTL1 CTL0 The settings are as follows in CAV-W mode. Command bit Processing VP0 to 7 The spindle rotational velocity is set. Command bit Processing VPCTL1 VPCTL0 The setting of VP0 to 7 is multiplied by 1. The setting of VP0 to 7 is multiplied by 2.
  • Page 119 CXD3068Q The setting in variable pitch mode is as shown below. Command bit Processing VPCTL1 to 0, VP7 to 0 The pitch of variable pitch mode is set. The setting of the pitch can be expressed with the equation below. P: Setting value of pitch –n n: Setting value for VPCTL1, VPCTL0 and VP7 to VP0 (two's complementary,...
  • Page 120 CXD3068Q $EX commands Data 1 Data 2 Data 3 Command SPD mode EPWM SPDC ICAP SFSL VC2C HIFC LPWR VPON Command bit Mode Description Spindle stop mode. ∗ STOP Spindle forward rotation mode. ∗ KICK Spindle reverse rotation mode. Valid only when LPWR = 0 BRAKE in any mode.
  • Page 121 CXD3068Q Mode LPWR Command Timing chart KICK 1-6 (a) CLV-N BRAKE 1-6 (b) STOP 1-6 (c) KICK 1-7 (a) BRAKE 1-7 (b) STOP 1-7 (c) CLV-W KICK 1-8 (a) BRAKE 1-8 (b) STOP 1-8 (c) KICK 1-9 (a) BRAKE 1-9 (b) STOP 1-9 (c) CAV-W...
  • Page 122 Timing Chart 1-3...
  • Page 123 Timing Chart 1-4...
  • Page 124 Timing Chart 1-5...
  • Page 125 CXD3068Q Timing Chart 1-6 CLV-N mode LPWR = 0 Timing Chart 1-7 CLV-W mode (when following the spindle rotational velocity) LPWR = 0 Timing Chart 1-8 CLV-W mode (when following the spindle rotational velocity) LPWR = 1 Timing Chart 1-9 CAV-W mode LPWR = 0 Timing Chart 1-10 CAV-W mode LPWR = 1...
  • Page 126 CXD3068Q Timing Chart 1-11 CLV-N mode LPWR = 0 Timing Chart 1-12 CLV-W mode LPWR = 0 Timing Chart 1-13 CLV-W mode LPWR = 1 Timing Chart 1-14 CAV-W mode EPWM = LPWR = 0 Timing Chart 1-15 CAV-W mode EPWM = LPWR = 1 –...
  • Page 127 CXD3068Q Timing Chart 1-16 CAV-W mode EPWM = 1, LPWR = 0 Timing Chart 1-17 CAV-W mode EPWM = LPWR = 1 – 124 –...

  • Page 128: Subcode Interface

    CXD3068Q [2] Subcode Interface There are two methods for reading out a subcode externally. The 8-bit subcodes P to W can be read out from SBSO by inputting EXCK. Sub-Q can be read out after checking CRC of the 80 bits in the subcode frame. Sub-Q can be read out from the SQSO pin by inputting 80 clock pulses to the SQCK pin when SCOR comes correctly and CRCF is high.
  • Page 129 CXD3068Q Timing Chart 2-1 – 126 –...
  • Page 130 Block Diagram 2-2...
  • Page 131 Timing Chart 2-3...
  • Page 132 Timing Chart 2-4 Signal Description PER0 to 7 RF jitter amount (used to adjust the focus bias). 8-bit binary data in PER0 = LSB, PER7 = MSB. Focus OK. High when the frame sync and the insertion protection timing match. LOCK GFS is sampled at 460Hz;...
  • Page 133 CXD3068Q Timing Chart 2-5 The relative velocity of the disc can be obtained with the following equation. (m + 1) (R: Relative velocity, m: Measurement results) VF0 to 9 is the result obtained by counting V16M/2 pulses while the reference signal (132.2kHz) generated from XTAL (XTAI, XTAO) (384Fs) is high.
  • Page 134 Timing Chart 2-6...

  • Page 135: Description Of Modes

    CXD3068Q [3] Description of Modes This LSI has three basic operating modes using a combination of spindle control and the PLL. The operations for each mode are described below. § 3-1. CLV-N Mode This mode is compatible with the CXD2510Q, and operation is the same as for conventional control. The PLL capture range is ±150kHz.

  • Page 136: Vco-C Mode

    CXD3068Q § 3-4. VCO-C Mode This is VCO control mode. In this mode, the V16M oscillation frequency can be controlled by setting $D commands VP0 to VP7 and VPCTL0, 1. The V16M oscillation frequency can be expressed by the following equation.
  • Page 137 CXD3068Q Fig. 3-1. Disc Stop to Regular Playback in CLV-W Mode CLV-W Mode Fig. 3-2. CLV-W Mode Flow Chart – 134 –...
  • Page 138 CXD3068Q VCO-C Mode Fig. 3-3. Access Flow Chart Using VCO Control – 135 –...

  • Page 139: Description Of Other Functions

    CXD3068Q [4] Description of other functions § 4-1. Channel Clock Regeneration by Digital PLL Circuit • The channel clock is necessary for demodulating the EFM signal regenerated by the optical system. Assuming T as the channel clock cycle, the EFM signal is modulated in an integer multiple of T from 3T to 11T. In order to read the information in the EFM signal, this integer value must be read correctly.
  • Page 140 CXD3068Q Block Diagram 4-1 – 137 –...

  • Page 141: Frame Sync Protection

    CXD3068Q § 4-2. Frame sync protection • In normal speed playback, a frame sync is recorded approximately every 136µs (7.35kHz). This signal is used as a reference to recognize the data within a frame. Conversely, if the frame sync cannot be recognized, the data is processed as error data because the data cannot be recognized.

  • Page 142: Da Interface

    CXD3068Q Timing Chart 4-3 § 4-4. DA Interface • The CXD3068Q supports the 48-bit slot interface as the DA interface. 48-bit slot interface This interface includes 48 cycles of the bit clock within one LRCK cycle, and is MSB first. When LRCK is high, the data is for the left channel.
  • Page 143 Timing Chart 4-4...

  • Page 144: Digital Out

    CXD3068Q § 4-5. Digital Out There are three Digital Out: the type 1 format for broadcasting stations, the type 2 form 1 format for home use, and the type 2 form 2 format for the manufacture of software. The CXD3068Q supports type 2 form 1. The channel status clock accuracy is automatically set to level II when using the crystal clock and to level III in CAV-W mode or variable pitch mode.

  • Page 145: Servo Auto Sequence

    CXD3068Q § 4-6. Servo Auto Sequence This function performs a series of controls, including auto focus and track jumps. When the auto sequence command is received from the CPU, auto focus, 1-track jump, 2N-track jump, fine search and M-track move are executed automatically.
  • Page 146 CXD3068Q • 2N-track jump When $4C ($4D for REV) is received from the CPU, a FWD (REV) 2N-track jump is performed in accordance with Fig. 4-9. The track jump count N is set with register 7. Although N can be set to 2 tracks, note that the setting is actually limited by the actuator.
  • Page 147 CXD3068Q Fig. 4-6-(a). Auto Focus Flow Chart Fig. 4-6-(b). Auto Focus Timing Chart – 144 –...
  • Page 148 CXD3068Q Fig. 4-7-(a). 1-Track Jump Flow Chart Fig. 4-7-(b). 1-Track Jump Timing Chart – 145 –...
  • Page 149 CXD3068Q Fig. 4-8-(a). 10-Track Jump Flow Chart Fig. 4-8-(b). 10-Track Jump Timing Chart – 146 –...
  • Page 150 CXD3068Q Fig. 4-9-(a). 2N-Track Jump Flow Chart Fig. 4-9-(b). 2N-Track Jump Timing Chart –147 –...
  • Page 151 CXD3068Q Fig. 4-10-(a). Fine Search Flow Chart Fig. 4-10-(b). Fine Search Timing Chart – 148 –...
  • Page 152 CXD3068Q Fig. 4-11-(a). M-Track Move Flow Chart Fig. 4-11-(b). M-Track Move Timing Chart – 149 –...

  • Page 153: Digital Clv

    CXD3068Q § 4-7. Digital CLV Fig. 4-12 shows the block diagram. Digital CLV outputs MDS error and MDP error signals with PWM, with the sampling frequency increased up to 130kHz during normal-speed playback in CLVS, CLVP and other modes. In addition, the digital spindle servo gain is variable. CLVS U/D: Up/down signal from CLVS servo MDS error:...

  • Page 154: Playback Speed

    CXD3068Q § 4-8. Playback Speed In the CXD3068Q, the following playback modes can be selected through different combinations of XTAI, XTSL pin, double-speed command (DSPB), VCO1 selection command (VCOSEL1), VCO1 frequency division commands (KSL3, KSL2) and command transfer rate selector (ASHS) in CLV-N or CLV-W mode. Playback Error correction ∗...

  • Page 155: Asymmetry Correction

    CXD3068Q § 4-9. Asymmetry Correction Fig. 4-13 shows the block diagram and circuit example. Fig. 4-15. Asymmetry Correction Application Circuit – 152 –...

  • Page 156: Cd Text Data Demodulation

    CXD3068Q §4-10. CD TEXT Data Demodulation • In order to demodulate the CD TEXT data, set the command $8 Data 6 D3 TXON to 1. During TXON = 1, connect EXCK to low and do not use the data output from SBSO because the CD TEXT demodulation circuit uses EXCK and the SBSO pin exclusively.
  • Page 157 Fig. 4-15. CD TEXT Data Timing Chart...

  • Page 158: Description Of Servo Signal Processing System Functions And Commands

    CXD3068Q [5] Description of Servo Signal Processing System Functions and Commands §5-1. General Description of Servo Signal Processing System (V : Supply voltage) Focus servo Sampling rate: 88.2kHz (when MCK = 128Fs) Input range: 1／4V to 3／4V Output format: 7-bit PWM Other: Offset cancel Focus bias adjustment...

  • Page 159: Digital Servo Block Master Clock (Mck)

    CXD3068Q §5-2. Digital Servo Block Master Clock (MCK) The clock with the 2/3 frequency of the crystal is supplied to the digital servo block. XT4D and XT2D are $3F commands, and XT1D is $3E command. (Default = 0) The digital servo block is designed with an MCK frequency of 5.6448MHz (128Fs) as typical. Mode XTAI FSTO...

  • Page 160: Dc Offset Cancel [Avrg Measurement And Compensation]

    CXD3068Q § 5-3. DC Offset Cancel [AVRG (Average) Measurement and Compensation] (See Fig. 5-3.) The CXD3068Q can measure the average of RFDC, VC, FE and TE and compensate these signals using the measurement results to control the servo effectively. This AVRG measurement and compensation is necessary to initialize the CXD3068Q, and is able to cancel the DC offset.

  • Page 161: E: F Balance Adjustment Function

    CXD3068Q § 5-4. E:F Balance Adjustment Function (See Fig. 5-3.) When the disc is rotated with the laser on, and with the FCS (focus) servo on via FCS Search (focus search), the traverse waveform appears in the TE signal due to disc eccentricity. In this condition, the low-frequency component can be extracted from the TE signal using the built-in TRK hold filter by setting D5 (TBLM) of $38 to 1.
  • Page 162 CXD3068Q Fig. 5-3a. Fig. 5-3b. – 159 –...

  • Page 163: Agcntl Function

    CXD3068Q § 5-6. AGCNTL (Automatic Gain Control) Function The AGCNTL function automatically adjusts the filter internal gain in order to obtain the appropriate servo loop gain. AGCNTL not only copes with the sensitivity variation of the actuator and photo diode, etc., but also obtains the optimal gain for each disc.
  • Page 164 CXD3068Q AGCNTL and default operation have two stages. In the first stage, rough adjustment is performed with high sensitivity for a certain period of time (select 256/128ms with AGHT, when MCK = 128Fs), and the AGCNTL coefficient approaches the appropriate value. The sensitivity at this time can be selected from two types with AGV1.

  • Page 165: Fcs Servo And Fcs Search

    CXD3068Q § 5-7. FCS Servo and FCS Search (Focus Search) The FCS servo is controlled by the 8-bit serial command $0X. (See Table 5-6.) Register D19 to D16 D23 to D20 Command name 1 0 ∗ ∗ FOCUS SERVO ON (FOCUS GAIN NORMAL) 1 1 ∗...

  • Page 166: Trk And Sld Servo Control

    CXD3068Q § 5-8. TRK (Tracking) and SLD (Sled) Servo Control The TRK and SLD servos are controlled by the 8-bit command $2X. (See Table 5-9.) When the upper 4 bits of the serial data are 2 (Hex), TZC is output to the SENS pin. Register Command D23 to D20...

  • Page 167: Mirr And Dfct Signal Generation

    CXD3068Q § 5-9. MIRR and DFCT Signal Generation The RF signal obtained from the RFDC pin is sampled at approximately 1.4MHz (when MCK = 128Fs) and loaded. The MIRR and DFCT signals are generated from this RF signal. MIRR Signal Generation The loaded RF signal is applied to peak hold and bottom hold circuits.

  • Page 168: Dfct Countermeasure Circuit

    CXD3068Q § 5-10. DFCT Countermeasure Circuit The DFCT countermeasure circuit maintains the directionality of the servo so that the servo does not become easily dislocated due to scratches or defects on discs. Specifically, these operations are achieved by detecting scratches and defects with the DFCT signal generation circuit, and when DFCT goes high, applying the low frequency component of the error signal before DFCT went high to the FCS and TRK servo filter inputs.

  • Page 169: Brake Circuit

    CXD3068Q § 5-12. Brake Circuit Immediately after a long distance track jump it tends to be hard for the actuator to settle and for the servo to turn on. The brake circuit prevents these phenomenon. In principle, the brake circuit uses the tracking drive as a brake by cutting the unnecessary portions utilizing the 180°...

  • Page 170: Cout Signal

    CXD3068Q § 5-13. COUT Signal The COUT signal is output to count the number of tracks during traverse, etc. It is basically generated by loading the MIRR signal at both edges of the TZC signal. The used TZC signal can be selected from among three different phases according to the COUT signal application.

  • Page 171: Writing To Coefficient Ram

    CXD3068Q § 5-15. Writing to Coefficient RAM The coefficient RAM can be rewritten by $34. All coefficients have default values in the built-in ROM, and transfer from the ROM to the RAM is completed approximately 40µs (when MCK = 128Fs) after the XRST pin rises.

  • Page 172: Servo Status Changes Produced By Lock Signal

    CXD3068Q § 5-17. Servo Status Changes Produced by LOCK Signal When the LOCK signal becomes low, the TRK servo switches to the gain-up mode and the SLD servo turns off in order to prevent SLD free-running. Setting D6 (LKSW) of $38 to 1 deactivates this function. In other words, neither the TRK servo nor the SLD servo change even when the LOCK signal becomes low.
  • Page 173 CXD3068Q MRT1, 0: These commands limit the time while MIRR = high. MRT1 MRT0 MIRR maximum time [ms] ∗ No time limit 1.10 2.20 4.00 ∗: preset – 170 –...
  • Page 174 CXD3068Q $34B (preset: $34B000) SFBK1 SFBK2 The low frequency can be boosted for brake operation. See "§ 5-12 for brake operation". SFBK1: When 1, brake operation is performed by setting the LowBooster-1 input to 0. This is valid only when TLB1ON = 1. The preset is 0. SFBK2: When 1, brake operation is performed by setting the LowBooster-2 input to 0.
  • Page 175 CXD3068Q HighBooster setting HBST1 HBST0 — –120/128 96/128 –124/128 112/128 –126/128 120/128 Fig. 5-24a. Table 5-25a. LowBooster-1 setting LB1S1 LB1S0 — –255/256 1023/1024 –511/512 2047/2048 –1023/1024 4095/4096 Table 5-25b. Fig. 5-24b. LowBooster-2 setting LB2S1 LB2S0 — –255/256 1023/1024 –511/512 2047/2048 –1023/1024 4095/4096 Fig.
  • Page 176 CXD3068Q Fig. 5-26a. Servo HighBooster Characteristics [FCS, TRK] (MCK = 128Fs) HBST1 = 0 HBST1 = 1, HBST0 = 0 HBST1 = 1, HBST0 = 1 – 173 –...
  • Page 177 CXD3068Q Fig. 5-26b. Servo LowBooster1 Characteristics [FCS, TRK] (MCK = 128Fs) LB1S1 = 0 LB1S1 = 1, LB1S0 = 0 LB1S1 = 1, LB1S0 = 1 – 174 –...
  • Page 178 CXD3068Q Fig. 5-26c. Servo LowBooster2 Characteristics [FCS, TRK] (MCK = 128Fs) LB2S1 = 0 LB2S1 = 1, LB2S0 = 0 LB2S1 = 1, LB2S0 = 1 – 175 –...
  • Page 179 CXD3068Q $34E (preset: $34E000) IDFSL3 IDFSL2 IDFSL1 IDFSL0 IDFT1 IDFT0 IDFSL3: The new DFCT detection is output. When IDFSL3 = 0, only DFCT in §5-9 is detected and the signal is output from the DFCT pin. (default) When IDFSL3 = 1, DFCT in §5-9 and new DFCT are switched and the resulting signal is output from the DFCT pin.
  • Page 180 CXD3068Q $34F FBL9 FBL8 FBL7 FBL6 FBL5 FBL4 FBL3 FBL2 FBL1 — When D15 = D14 = D13 = D12 = D11 = 1 ($34F) D10 = 0 FBIAS LIMIT register write FBL9 to FBL1: Data; data compared with FB9 to FB1, FBL9 = MSB. When using the FBIAS register in counter mode, counter operation stops when the value of FB9 to FB1 matches with FBL9 to FBL1.
  • Page 181 CXD3068Q $35 (preset: $35 58 2D) FG6 FG5 FG4 FG3 FG2 FG1 FG0 FT1, FT0, FTZ: Focus search-up speed Default value: 010 (0.673 × V V/s) Focus drive output conversion Focus search speed [V/s] 1.35 × V ∗ 0.673 × V 0.449 ×...
  • Page 182 CXD3068Q $37 (preset: $37 50 BA) FZSH FZSL SM5 SM4 SM3 SM2 SM1 SM0 AGS AGJ AGGF AGGT AGV1 AGV2 AGHS AGHT FZSH, FZSL: FZC (Focus Zero Cross) slice level Default value: 01 (1/8 × V /2, V : supply voltage); FE input conversion FZSH FZSL Slice level...
  • Page 183 CXD3068Q $38 (preset: $38 00 00) VCLM VCLC FLM FLC0 RFLM RFLC AGF AGT DFSW LKSW TBLM TCLM FLC1 TLC2 TLC1 TLC0 DC offset cancel. See §5-3. ∗ VCLM: VC level measurement (on/off) VCLC: VC level compensation for FCS In register (on/off) ∗...
  • Page 184 CXD3068Q $39 (preset: $39 0000) DAC SD6 SD5 SD4 SD3 SD2 SD1 SD0 DAC: Serial data readout DAC mode (on/off) SD6 to SD0: Serial readout data select Readout data length Readout data 8 bits Coefficient RAM data for address = SD5 to SD0 16 bits Data RAM data for address = SD4 to SD0 SD3 to SD0...
  • Page 185 CXD3068Q $3A (preset: $3A 00 00) FBON FBSS FBUP FBV1 FBV0 TJD0 FPS1 FPS0 TPS1 TPS0 SJHD INBK MTI0 FIFZC FBON: FBIAS (focus bias) register addition (on/off) The FBIAS register value is added to the signal loaded into the FCS In register by setting FBON = 1 (on).
  • Page 186 CXD3068Q FIFZC: This selects the FZC slice level setting command. When 0, the FZC slice level is determined by the $37 FZSH and FZSL setting values. (default) When 1, the FZC slice level is determined by the $3F8 FIFZB3 to FIFZB0 and FIFZA3 to FIFZA0 setting values.
  • Page 187 CXD3068Q $3B (preset: $3B E0 50) SFO2 SFO1 SDF2 SDF1 MAX2 MAX1 SFOX BTF D2V2 D2V1 D1V2 D1V1 RINT SFOX, SFO2, SFO1: FOK slice level Default value: 011 (28/256 × V /2, V = supply voltage) RFDC input conversion SFOX SFO2 SFO1 Slice level...
  • Page 188 CXD3068Q D2V2, D2V1: Peak hold 2 for DFCT signal generation Count-down speed setting Default value: 01 (0.086 × V /ms, 44.1kHz) [V/ms] unit items indicate RFDC input conversion; [kHz] unit items indicate the operating frequency of the internal counter. Count-down speed D2V2 D2V1 [V/ms]...
  • Page 189 CXD3068Q $3C (preset: $3C 00 80) COSS COTS CETZ CETF COT2 COT1 MOT2 BTS1 BTS0 MRC1 MRC0 COSS, COTS: This selects the TZC signal used when generating the COUT signal. Preset = HPTZC. COSS COTS — STZC ∗ HPTZC DTZC ∗: preset, —: don't care STZC is the TZC generated by sampling the TE signal at 700kHz.
  • Page 190 CXD3068Q $3D (preset: $3D 00 00) SFID SFSK THID THSK TLD2 TLD1 TLD0 SFID: SLED servo filter input can be obtained not from SLD in Reg, but from M0D, which is the TRK filter second-stage output. When the low frequency component of the tracking error signal obtained from the RF amplifier is attenuated, the low frequency can be amplified and input to the SLD servo filter.
  • Page 191 CXD3068Q • Input coefficient sign inversion when SFID = 1 and THID = 1 The preset coefficients for the TRK filter are negative for input and positive for output. With this, the CXD3068Q outputs the servo drives which have the reversed phase to the error inputs.. When SFID = 1, the TRK filter negative input coefficient is applied to the SLD filter, so invert the SLD input coefficient (K00) sign.
  • Page 192 CXD3068Q $3E (preset: $3E 00 00) F1NM F1DM F3NM F3DM T1NM T1UM T3NM T3UM DFIS TLCD LKIN COIN MDFI MIRI XT1D F1NM, F1DM: Quasi double accuracy setting for FCS servo filter first-stage On when 1; default when 0. F1NM: Gain normal F1DM: Gain down T1NM, T1UM: Quasi double accuracy setting for TRK servo filter first-stage On when 1;...
  • Page 193 CXD3068Q $3F (preset: $3F 00 00) AGG4 XT4D XT2D DRR2 DRR1 DRR0 ASFG FTQ AGHF Note) Be sure to set D4 of $3F to 1 for CXD3068Q. AGG4: This varies the amplitude of the internally generated sine wave using the AGGF and AGGT commands during AGC.
  • Page 194 CXD3068Q DRR2 to DRR0: Partially clears the Data RAM values (0 write). The following values are cleared when 1 (on) respectively; default = 0 DRR2: M08, M09, M0A DRR1: M00, M01, M02 DRR0: M00, M01, M02 only when LOCK = low Note) Set DRR1 and DRR0 on for 50µs or more.
  • Page 195 CXD3068Q $3F8 (preset: $3F8800) SYG3 SYG2 SYG1 SYG0 FIFZB3 FIFZB2 FIFZB1 FIFZB0 FIFZA3 FIFZA2 FIFZA1 FIFZA0 SYG3 to SYG0: These simultaneously set the focus drive, tracking drive and sled drive output gains. See the $CX command for the spindle drive output gain setting. SYG3 SYG2 SYG1...
  • Page 196 CXD3068Q Description of Data Readout – 193 –...

  • Page 197: List Of Servo Filter Coefficients

    CXD3068Q § 5-19. List of Servo Filter Coefficients <Coefficient Preset Value Table (1)> ADDRESS DATA CONTENTS SLED INPUT GAIN SLED LOW BOOST FILTER A-H SLED LOW BOOST FILTER A-L SLED LOW BOOST FILTER B-H SLED LOW BOOST FILTER B-L SLED OUTPUT GAIN FOCUS INPUT GAIN SLED AUTO GAIN FOCUS HIGH CUT FILTER A...
  • Page 198 CXD3068Q <Coefficient Preset Value Table (2)> ADDRESS DATA CONTENTS SLED INPUT GAIN (Only when TRK Gain Up2 is accessed with SFSK = 1.) ANTI SHOCK LOW PASS FILTER B NOT USED ANTI SHOCK HIGH PASS FILTER B-H ANTI SHOCK HIGH PASS FILTER B-L ANTI SHOCK FILTER COMPARATE GAIN TRACKING GAIN UP2 HIGH CUT FILTER A TRACKING GAIN UP2 HIGH CUT FILTER B...
  • Page 199 CXD3068Q – 196 –...
  • Page 200 CXD3068Q – 197 –...
  • Page 201 CXD3068Q – 198 –...
  • Page 202 CXD3068Q – 199 –...
  • Page 203 CXD3068Q SLD Servo fs = 345Hz Note) Set the MSB bit of the K02 and K04 coefficients to 0. HPTZC/Auto Gain fs = 88.2kHz – 200 –...
  • Page 204 CXD3068Q Anti Shock fs = 88.2kHz Note) Set the MSB bit of the K34 coefficient to 0. The comparator level is 1/16 the maximum amplitude of the comparator input. AVRG fs = 88.2kHz TRK Hold fs = 345Hz Note) Set the MSB bit of the K42 and K44 coefficients to 0. FCS Hold fs = 345Hz Note) Set the MSB bit of the K4A and K4C coefficients to 0.

  • Page 205: Tracking And Focus Frequency Response

    CXD3068Q § 5-21. TRACKING and FOCUS Frequency Response When using the preset coefficients with the boost function off. When using the preset coefficients with the boost function off. – 202 –...
  • Page 206 CXD3068Q – 203 –...
  • Page 207 CXD3068Q Package Outline Unit: mm – 204 –...
  • Page 208 This data sheet has been made from recycled paper to help protect the environment.
  • Page 209 2 Megabit (256K x 8) Multi-Purpose Flash SST39VF020 Preliminary Specifications FEATURES: • Organized as 256K X 8 • Fast Sector Erase and Byte Program: – Sector Erase Time: 18 ms typical • Single 2.7-3.6V Read and Write Operations – Chip Erase Time: 70 ms typical •...
  • Page 210 2 Megabit Multi-Purpose Flash SST39VF020 Preliminary Specifications keeping CE# low. The address bus is latched on the Chip Erase Operation falling edge of WE# or CE#, whichever occurs last. The The SST39VF020 device provides a Chip Erase opera- data bus is latched on the rising edge of WE# or CE#, tion, which allows the user to erase the entire memory whichever occurs first.
  • Page 211 2 Megabit Multi-Purpose Flash SST39VF020 Preliminary Specifications Toggle Bit (DQ the inclusion of six byte load sequence. The During the internal Program or Erase operation, any SST39VF020 device is shipped with the software data consecutive attempts to read DQ will produce alternat- protection permanently enabled.
  • Page 212 2 Megabit Multi-Purpose Flash SST39VF020 Preliminary Specifications Standard Pinout Top View V DD V SS Die Up 336 ILL F01.0 1: P TSOP P (8mm x 14mm) IGURE SSIGNMENTS FOR ACKAGE V DD 32 31 30 32-Pin PDIP 32-Lead PLCC Top View Top View 14 15 16 17 18 19 20...
  • Page 213 2 Megabit Multi-Purpose Flash SST39VF020 Preliminary Specifications 2: P ABLE ESCRIPTION Symbol Pin Name Functions Address Inputs To provide memory addresses. During sector erase A address lines will select the sector. Data Input/output To output data during read cycles and receive input data during write cycles.
  • Page 214 2 Megabit Multi-Purpose Flash SST39VF020 Preliminary Specifications 4: S ABLE OFTWARE OMMAND EQUENCE Command 1st Bus 2nd Bus 3rd Bus 4th Bus 5th Bus 6th Bus Sequence Write Cycle Write Cycle Write Cycle Write Cycle Write Cycle Write Cycle Addr Data Addr Data...
  • Page 215 2 Megabit Multi-Purpose Flash SST39VF020 Preliminary Specifications Absolute Maximum Stress Ratings (Applied conditions greater than those listed under “Absolute Maximum Stress Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these conditions or conditions greater than those defined in the operational sections of this data sheet is not implied.
  • Page 216 2 Megabit Multi-Purpose Flash SST39VF020 Preliminary Specifications 5: DC O = 2.7-3.6V ABLE PERATING HARACTERISTICS Limits Symbol Parameter Units Test Conditions Power Supply Current CE#=OE#=V WE#=V , all I/Os open, Read Address input = V , at f=1/T Min., Write CE#=WE#=V OE#=V Max.
  • Page 217 2 Megabit Multi-Purpose Flash SST39VF020 Preliminary Specifications AC CHARACTERISTICS 9: R = 2.7-3.6V ABLE YCLE IMING ARAMETERS SST39VF020-70 SST39VF020-90 Symbol Parameter Units Read Cycle time Chip Enable Access Time Address Access Time Output Enable Access Time CE# Low to Active Output OE# Low to Active Output CE# High to High-Z Output OE# High to High-Z Output...
  • Page 218 2 Megabit Multi-Purpose Flash SST39VF020 Preliminary Specifications T RC T AA ADDRESS A 17-0 T CE T OE T OHZ T OLZ V IH T CHZ T OH T CLZ HIGH-Z HIGH-Z DQ 7-0 DATA VALID DATA VALID 336 ILL F03.0 3: R IGURE YCLE...
  • Page 219 2 Megabit Multi-Purpose Flash SST39VF020 Preliminary Specifications INTERNAL PROGRAM OPERATION STARTS T BP 5555 2AAA 5555 ADDR ADDRESS A 17-0 T AH T DH T CP T AS T DS T CPH T CH T CS DQ 7-0 DATA BYTE 336 ILL F05.0 (ADDR/DATA) 5: CE# C...
  • Page 220 2 Megabit Multi-Purpose Flash SST39VF020 Preliminary Specifications ADDRESS A 17-0 T CE T OES T OE T OEH DQ 6 TWO READ CYCLES WITH SAME OUTPUTS 336 ILL F07.1 7: T IGURE OGGLE IMING IAGRAM T SE SIX-BYTE CODE FOR SECTOR ERASE 5555 2AAA 5555...
  • Page 221 2 Megabit Multi-Purpose Flash SST39VF020 Preliminary Specifications T SCE SIX-BYTE CODE FOR CHIP ERASE 5555 2AAA 5555 5555 2AAA 5555 ADDRESS A 17-0 T WP DQ 7-0 336 ILL F17.0 Note: The device also supports CE# controlled chip erase operation. The WE# and CE# signals are interchangeable as long as minimum timings are met.
  • Page 222 2 Megabit Multi-Purpose Flash SST39VF020 Preliminary Specifications THREE-BYTE SEQUENCE FOR SOFTWARE ID EXIT AND RESET 5555 2AAA 5555 ADDRESS A 14-0 DQ 7-0 T IDA T WP T WHP 336 ILL F10.0 11: S ID E IGURE OFTWARE XIT AND ESET ©...
  • Page 223 2 Megabit Multi-Purpose Flash SST39VF020 Preliminary Specifications V IHT V HT V HT INPUT REFERENCE POINTS OUTPUT V LT V LT V ILT 336 ILL F11.1 AC test inputs are driven at V (2.4 V) for a logic “1” and V (0.4 V) for a logic “0”.
  • Page 224 2 Megabit Multi-Purpose Flash SST39VF020 Preliminary Specifications Start Write data: AA Address: 5555 Write data: 55 Address: 2AAA Write data: A0 Address: 5555 Load Byte Address/Byte Data Wait for end of Program (T BP , Data# Polling bit, or Toggle bit operation) Program Completed...
  • Page 225 2 Megabit Multi-Purpose Flash SST39VF020 Preliminary Specifications Toggle Bit Data# Polling Internal Timer Byte Byte Byte Program/Erase Program/Erase Program/Erase Initiated Initiated Initiated Read DQ 7 Read byte Wait T BP , T SCE, or T SE Read same Is DQ 7 = byte true data? Program/Erase...
  • Page 226 2 Megabit Multi-Purpose Flash SST39VF020 Preliminary Specifications Software Product ID Entry Software Product ID Exit & Command Sequence Reset Command Sequence Write data: AA Write data: AA Write data: F0 Address: 5555 Address: 5555 Address: XX Write data: 55 Write data: 55 Wait T IDA Address: 2AAA Address: 2AAA...
  • Page 227 2 Megabit Multi-Purpose Flash SST39VF020 Preliminary Specifications Chip Erase Sector Erase Command Sequence Command Sequence Write data: AA Write data: AA Address: 5555 Address: 5555 Write data: 55 Write data: 55 Address: 2AAA Address: 2AAA Write data: 80 Write data: 80 Address: 5555 Address: 5555 Write data: AA...
  • Page 228 2 Megabit Multi-Purpose Flash SST39VF020 Preliminary Specifications Device Speed Suffix1 Suffix2 SST39VF020 - XXX Package Modifier H = 32 leads Numeric = Die modifier Package Type P = PDIP N = PLCC W = TSOP (die up) (8mm x 14mm) U = Unencapsulated die Temperature Range C = Commercial = 0°...
  • Page 229 2 Megabit Multi-Purpose Flash SST39VF020 Preliminary Specifications PACKAGING DIAGRAMS pin 1 index Optional Ejector Pin Indentation Shown for .600 Conventional Mold Only .625 .530 .550 1.645 .065 7˚ 1.655 .075 4 PLCS. .170 Base Plane .200 Seating Plane .015 0˚ .050 15˚...
  • Page 230 2 Megabit Multi-Purpose Flash SST39VF020 Preliminary Specifications 1.05 1.10 0.95 0.90 PIN # 1 IDENT. DIA. 1.00 .270 8.10 .170 7.90 0.15 12.50 0.05 12.30 0.70 0.50 14.20 13.80 Note: 1. Complies with JEDEC publication 95 MO-142 BA dimensions, although some dimensions may be more stringent. 2.
  • Page 231 Contact Information (Waslin Group . since 1992) Website: http://www.waslin.cn, http://www.metatech.com.tw HongKong Tel: 852-24212379 Fax: 852-24212479 Address: Unit 3503, Metroplaza Tower II, 223 Hing Fong Rd., Kwai Fong, Hong Kong. Email: service@meta.com.hk Beijing Tel: 86-10-68582188 Fax: 86-10-68583188 Address: Rm. 210, China Hall of Science & Technology, No. 3 FuXing Road, Beijing, China 100038 Shanghai Tel: 86-21-64857530...
  • Page 232 Digital Video Encoder for Video CD NOV. 11, 2002 Version 0.1 SUNPLUS TECHNOLOGY CO. reserves the right to change this documentation without prior notice. Information provided by SUNPLUS TECHNOLOGY CO. is believed to be accurate and reliable. However, SUNPLUS TECHNOLOGY CO. makes no warranty for any errors which may appear in this document. Contact SUNPLUS TECHNOLOGY CO.
  • Page 233 SPCA717A Table of Contents PAGE 1. GENERAL DESCRIPTION..................................3 2. FEATURES........................................3 3. APPLICATIONS ......................................3 4. BLOCK DIAGRAM ....................................4 5. SIGNAL DESCRIPTIONS ..................................5 5.1. PIN D ....................................5 ESCRIPTION 5.2. PIN M ......................................6 6. FUNCTIONAL DESCRIPTIONS ................................7 6.1. M ....................................7 ELECTION 6.2. C .....................................7 LOCK IMING...

  • Page 234: General Description

    SPCA717A DIGITAL VIDEO ENCODER FOR VIDEO CD 1.GENERAL DESCRIPTION 2.FEATURES The SPCA717A is designed specifically for VideoCD, video games n 8-bit 4:2:2 YCrCb inputs for glue-less interface to and other digital video systems, which require the conversion of digital YCrCb (MPEG) data to analog NTSC/PAL video. MPEG decoders n NTSC/PAL/PAL-M/PAL-Nc composite video outputs device supports a glue-less interface to most popular MPEG...

  • Page 235: Block Diagram

    SPCA717A 4.BLOCK DIAGRAM VBIAS VREFOUT FSADJUST COMP Internal Generator VREF CLKOUT CVBS/Y P[7:0] Mod. Upsample Mixer HSYNC* Latch 1.3MHz VSYNC* MODEA TEST SLEEP MODEB LUMA MASTER CBSWAP © Sunplus Technology Co., Ltd. NOV. 11, 2002 Proprietary & Confidential Preliminary Version: 0.1...

  • Page 236: Signal Descriptions

    SPCA717A 5.SIGNAL DESCRIPTIONS 5.1. PIN Description Mnemonic PIN No. Type Description DATA[7:0] 17 - 24 YCrCb pixel inputs. They are latched on the rising edge of CLK. YCrCb input data conform to CCIR 601. CLKOUT Pixel clock output VSYNC Vertical sync input/output. VSYNC is latched/output following the rising edge of CLK. HSYNC Horizontal sync input/output.

  • Page 237: Pin Map

    SPCA717A 5.2. PIN Map DATA7 FSADJUST DATA6 COMP DATA5 VREFOUT DATA4 DATA3 VREFIN DATA2 VBIAS DATA1 DATA0 AGND © Sunplus Technology Co., Ltd. NOV. 11, 2002 Proprietary & Confidential Preliminary Version: 0.1...

  • Page 238: Functional Descriptions

    SPCA717A 6.FUNCTIONAL DESCRIPTIONS Note: 6.1. Mode Selection The term “common operating mode” refers to North American NTSC and Master mode is selected when MASTER = 1; slave mode is Western European PAL Table 1 illustrates the multi-functionality of the mode pins during master and slave mode. To access the more exotic selected when MASTER = 0.

  • Page 239: Video Timing

    SPCA717A CBSWAP HSYNC* P[7:0] Yn + 1 Cbn+2 P[7:0] Yn + 1 Crn+2 Figure 1. Pix Sequence Note1: CBSWAP is pin 11. Note2: Pixel transitions must occur observing setup and hold timing about the rising edge of CLK. Note3: Pixel sequence will beging with Cbn at 4 x m clock periods following the falling edge of HSYNC*, when m is an integer. 6.4.

  • Page 240: Slave Mode

    SPCA717A 6.4.3. Slave mode 6.5. Vertical Blanking Intervals Horizontal sync (HSYNC*) and vertical sync (VSYNC*) are inputs For NTSC, scan lines 1 -9 and 263-272, inclusive, are always that are registered on the rising edge of CLOCK. The horizontal blanked. T here is no setup on scan lines 10-21 and 273-284 counter is incremented on the rising edge of CLOCK.
  • Page 241 SPCA717A Start Analog YSYNC Field 1 Burst Phase Analog Field 2 Analog Field 3 Burst Phase Analog Field 4 Burst Begins with Positive Half-Cycle Burst Phase = Reference Phase = 180 Relative to B-Y Burst Begins with Negative Half-Cycle Burst Phase = Reference Phase = 180 Relative to B-Y Figure 2.
  • Page 242 SPCA717A Start VSYNC Analog Field 1 -U Phase Analog Field 2 Analog Field 3 Analog Field 4 Field One Burst Field Two Blanking Field Three Intervals Field Four Burst Phase = Reference Phase = 135 Relative to U PAL Switch = 0, + V Component Burst Phase = Reference Phase + 90 = 225 Relative to U...
  • Page 243 SPCA717A Start VSYNC Analog Field 5 -U Phase Analog Field 6 Analog Field 7 Analog Field 8 Field Five Burst Field Six Blanking Field Seven Intervals Field Eight Burst Phase = Reference Phase = 135 Relative to U PAL Switch = 0, + V Component Burst Phase = Reference Phase + 90 = 225 Relative to U...

  • Page 244: Pixel Input Ranges And Colorspace Conversion

    SPCA717A 6.9. Pixel Input Ranges And Colorspace Conversion 6.12. Outputs 6.10. YC inputs (4:2:2 YCRCB) All digital-to-analog converters are designed to drive standard video levels into an equivalent 37.5 Ω load. Either tone composite Y has a nominal range of 16-235; Cb and Cr have a nominal video outputs or Y outputs are available (selectable by range of 16-240, with 128 equal to zero.

  • Page 245: Electrical Specifications

    SPCA717A 7.ELECTRICAL SPECIFICATIONS 7.1. Absolute Maximum Rating Parameter Symbol Min. Tpy. Max. Unit Power Supply (Measured to ground) °C Ambient Operating temperature +125 Voltage on Any Signal Pin GND-0.5 VAA+0.5 °C Storage Temperature +150 °C Junction Temperature +150 Note: This device employs high-impedance CMOS devices on all signal pins. It should be handled as an ESD -sensitive device. Voltage on any pin that exceeds the power supply voltage by more than +0.5V can cause destructive latchup.

  • Page 246: Ac Characteristics

    SPCA717A 7.4. AC Characteristics DATA[7:0] HSYNC*. VSYNC* (Master Mode) CVBS/Y, CVBS/C Pipeline Master Description Symbol Min. Typ. Max. Units Pixel/Control Setup Time Pixel/Control Hold Time Control Output Hold Time Control Output Delay Time HSYNC* to Analog Output (Master Mode) CLK Periods CLK Frequency 24.54 29.5...

  • Page 247: Application Circuits

    SPCA717A 8.APPLICATION CIRCUITS 8.1. PC Board Considerations 8.3. Power And Ground Planes The layout should be optimized for lowest noise on the power and For optimum performance, a common digital and analog ground ground planes by providing good decoupling. The trace length plane is recommended.
  • Page 248 SPCA717A Table 6. Typical Parts List (Internal Voltage Reference) Locations Description Vendor Part Number 0.1 µF Ceramic Capacitor C1 - 5, C7 Erie RPE112Z5U104M50V 47 µF Capacitor Mallory CSR13F476KM Ferrite Bead - Surface Mount Fair-Rite 2743021447 L2, L3 Ferrite Bead (z < 300Ω @ 5MHz) ATC LCB0805, Taiyo Yuden BK2125LM182 470 or 560 Ω...

  • Page 249: Package/Pad Locations

    SPCA717A 9.PACKAGE/PAD LOCATIONS 9.1. Package Type: 32 pin LQFP Note: Ambient temperature range: 0°C - 70°C © Sunplus Technology Co., Ltd. NOV. 11, 2002 Proprietary & Confidential Preliminary Version: 0.1...

  • Page 250: Outline Dimensions

    SPCA717A 9.2. Outline Dimensions MILLIMETER Symbol Min. Nom. Max. 1.60 0.05 0.15 1.35 1.40 1.45 9.00BSC. 7.00BSC. 9.00BSC. 7.00BSC. 0.08 0.20 0.08 θ θ1 θ2 θ3 0.09 0.20 0.45 0.60 0.75 1.00REF 0.20 © Sunplus Technology Co., Ltd. NOV. 11, 2002 Proprietary &...
  • Page 251 SPCA717A 10. DISCLAIMER The information appearing in this publication is believed to be accurate. Integrated circuits sold by Sunplus Technology are covered by the warranty and patent indemnification provisions stipulated in the terms of sale only. SUNPLUS makes no warranty, express, statutory implied or by description regarding the information in this publication or regarding the freedom of the described chip(s) from patent infringement.
  • Page 252 SPCA713A Digital to Audio Converter GENERAL DESCRIPTION The SPCA713A is a low cost stereo digital to analog converter for driver, MIDI applications, Karaoke system, and set-top box etc. consumer electronic applications such as MP3 player, Mini Disk, The SPCA713A provides, not only the latest technology, but also audio or video CD player, SVCD, DVD player, CD/DVD- ROM the full commitment and technical support of Sunplus.
  • Page 253 SPCA713A FUNCTION DESCRIPTION 1. SYSTEM CLOCK The system clock is either 256fs or 384fs where fs is the standard system clock is used to operate the digital filter and delta sigma audio frequency including 32Khz, 44.1Khz, and 48KhZ. The modulator. The system clock is input through SCKIN (pin14). TSCIH System Clock TSCI=1/256fs...
  • Page 254 SPCA713A 3. INTERNAL RESET 4. MODE CONTROL When the power supply voltage V reaches 2.2V, the internal The SPCA713A provides two control functions – Input Format reset function is initialized. The power-on reset initialization period Select and De-emphasis through FORMAT (pin 13) and DM is 1,024 SCKIN cycles during which the analog out puts are forced (pin12).
  • Page 255 SPCA713A ELECTRICAL CHARACTERISTICS At 25 C, VCC=VDD=5V/3.3V, fs=44.1kHz, 16Bit input data, System Clock = 384/256fs Parameter Conditions Min. Type Max. Unit Resolution Bits Sampling Frequency 44.1 System Clock Frequency 256/384fs Audio Data Format Normal/IIS Data Bit Length Power Supply Voltage Range: VDD VDD=5V VDD=3.3V Supply Current: IDD...
  • Page 256 SPCA713A TIMING CHARACTERISTICS TIMING DIAGRAM At 25 C, VCC = VDD = 5V/3.3V, fs = 44.1kHz, 16Bit input data, DATA INPUT TIMING System Clock = 384/256fs Parameter Symbol Value Unit Data Input Timing DIN setup time >30 BCKIN DIN hold time >30 BCKIN high-level, low-level Tbcwh,...

  • Page 257: Disclaimer

    SPCA713A PACKAGE DRAWING NO. 114-S Model Package Package Drawing No. SPCA713A 14 pin SOP 114-S Package outline drawing is shown below: SRCIN SCKIN FORMAT BCKIN VOUTR VOUTL Symbols Dimensions In Milimeters Dimensions In Inches Min. Nom. Max. Min. Nom. Max. 1.47 1.60 1.73...
  • Page 258 SPCA713A REVISION HISTORY Date Revision # Description Page APR. 03, 2001 Original © Sunplus Technology Co., Ltd. APR. 03, 2001 Version: 1.0...

  • Page 259: Revision Histroy

    SPCA717A 11. REVISION HISTROY Date Revis ion # Description Page NOV. 11, 2002 Original © Sunplus Technology Co., Ltd. NOV. 11, 2002 Proprietary & Confidential Preliminary Version: 0.1...
  • Page 260 BH3541F / BH3544F 光ディスク IC CD-ROM 用ヘッドホンアンプ BH3541F / BH3544F BH3541F、BH3544F はデジタルソース向けのデュアルヘッドホンアンプです。BH3541F はゲイン 0dB、BH3544F は ゲイン 6dB 固定で、外付けゲイン設定が不要です。BH3541F、BH3544F ともミュート機能を内蔵することによって 電源 ON-OFF 時のボツ音防止対策が簡単に行えます。また、サーマルシャットダウン回路の内蔵により、短絡などに よる IC 破壊を防止します。 品 名 固定ゲイ ン BH3541F BH3544F ! ! ! ! 用途 用途 用途 用途 CD-ROM、CD、MD、パソコン、ノートパソコン、カムコーダなどヘッドホン出力を有する機器 ! ! ! ! 特長 特長...
  • Page 261 BH3541F / BH3544F 光ディスク IC ! ! ! ! ブロックダイアグラム ブロックダイアグラム ブロックダイアグラム ブロックダイアグラム OUT2 BIAS BIAS 180k (90k) (6dB) 180k (90k) (6dB) MUTE OUT1 MUTE )は、BH3544の値...
  • Page 262 BH3541F / BH3544F 光ディスク IC ! ! ! ! 各端子説明 各端子説明 各端子説明 各端子説明 機 能 Pin No. 端子名 I / O 端子電圧 内部等価回路図 出力端子 2.1V OUT1 OUT2 2.1V = 5V） （V ミュートコントロール端子 （電源ON・OFF時はボツ  音対策としてLoにする。） 動作 ：Hi 0.1V MUTE ：Lo（Open） MUTE （Open時） 190k 入力端子...
  • Page 263 BH3541F / BH3544F 光ディスク IC ! ! ! ! 電気的特性 電気的特性（特に指定のない限り Ta = 25°C, V = 5.0V, R = 32Ω, f = 1kHz, 電気的特性 電気的特性 = −6dBV） BH3541F : V = 0dBV, BH3544F : V Parameter Symbol Min. Typ. Max. Unit Conditions =0Vrms...
  • Page 264 BH3541F / BH3544F 光ディスク IC ! ! ! ! 測定条件表 測定条件表 測定条件表 測定条件表 SW表 記号 Monitor Conditions SW1 SW3 SW5 SW7 SW8A SW8B − − − − − − − − − f=1kHz, V 1/2=0dBV (V 1/2=−6dBV), V1AC, V2AC VTM=1.6V −...
  • Page 265 BH3541F / BH3544F 光ディスク IC ! ! ! ! 応用例 応用例 応用例 応用例 330µ 1µ 47µ OUT2 BIAS BIAS 180k (90k) (6dB) 180k (90k) (6dB) MUTE 330µ OUT1 MUTE 1µ VMUTE 100k 1µ H : Active L : Mute )は、BH3544の値 Fig.2 ! ! ! ! 外付け部品の説明...
  • Page 266 BH3541F / BH3544F 光ディスク IC ! ! ! ! 電気的特性曲線 電気的特性曲線 電気的特性曲線 電気的特性曲線 Ta=25 °C Ta=25 °C Ta=25 °C =32Ω =32Ω =32Ω −10 =0dBV f=1kHz MUTE : OFF −20 −30 −40 −50 −60 MUTE : ON −70 −80 −90 SUPPLY VOLTAGE : V SUPPLY VOLTAGE : V MUTE CONTROL VOLTAGE : VTM (V) Fig.4 端子直流電圧ー電源電圧特性...
  • Page 267 BH3541F / BH3544F 光ディスク IC Ta=25 °C Ta=25 °C C-BIAS:47µF =−20dBV =−20dBV C-BIAS:33µF =32Ω =32Ω C-BIAS:100µF Rg=0Ω Rg=0Ω =100H = OPEN = 32Ω = 0dBV = 5V 100k 100k FREQUENCY : f (H FREQUENCY : f (H SUPPLY VOLTAGE : V Fig.13 リップルリジェクション...
  • Page 268 bq24010, bq24012, bq24013, bq24014 www.ti.com SLUS530D − SEPTEMBER 2002 − REVISED SEPTEMBER 2003 SINGLE CHIP, LI ION CHARGE MANAGEMENT IC FOR HANDHELD APPLICATIONS (bqTINYt) FEATURES DESCRIPTION Small 3 mm × 3 mm MLP (QFN) Package The bqTINYt series are highly integrated Li-Ion and Ideal for Low-Dropout Designs for Single-Cell Li-Pol linear charge management devices targeted at Li−Ion or Li−Pol Packs in Space Limited...
  • Page 269 bq24010, bq24012, bq24013, bq24014 www.ti.com SLUS530D − SEPTEMBER 2002 − REVISED SEPTEMBER 2003 These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. ORDERING INFORMATION CHARGE OPTIONAL...
  • Page 270 bq24010, bq24012, bq24013, bq24014 www.ti.com SLUS530D − SEPTEMBER 2002 − REVISED SEPTEMBER 2003 ELECTRICAL CHARACTERISTICS over 0_C ≤ T J ≤ 125_C and recommended supply voltage, unless otherwise noted PARAMETER TEST CONDITIONS UNIT INPUT CURRENT VCC current, I CC(VCC) V CC > V CC(min) , STATx pins in OFF state Sum of currents into OUT and BAT pins, µA Sleep current, I CC(SLP)
  • Page 271 bq24010, bq24012, bq24013, bq24014 www.ti.com SLUS530D − SEPTEMBER 2002 − REVISED SEPTEMBER 2003 ELECTRICAL CHARACTERISTICS (continued) over 0_C ≤ T J ≤ 125_C and recommended supply voltage, unless otherwise noted PARAMETER TEST CONDITIONS UNIT BATTERY RECHARGE THRESHOLD V O( V O( V O( Recharge threshold, V (RCH) −0.135...
  • Page 272 bq24010, bq24012, bq24013, bq24014 www.ti.com SLUS530D − SEPTEMBER 2002 − REVISED SEPTEMBER 2003 DRC PACKAGE DRC PACKAGE (TOP VIEW) (TOP VIEW) STAT2 STAT1 STAT2 STAT1 bq24010DRC bq24012DRC ISET ISET DRC PACKAGE DRC PACKAGE (TOP VIEW) (TOP VIEW) STAT2 STAT1 STAT2 STAT1 bq24014DRC bq24013DRC...
  • Page 273 bq24010, bq24012, bq24013, bq24014 www.ti.com SLUS530D − SEPTEMBER 2002 − REVISED SEPTEMBER 2003 − Ground input There is an internal electrical connection between the exposed thermal pad Exposed and V SS pin of the device. The exposed thermal pad must be connected to the Thermal −...
  • Page 274 bq24010, bq24012, bq24013, bq24014 www.ti.com SLUS530D − SEPTEMBER 2002 − REVISED SEPTEMBER 2003 FUNCTIONAL BLOCK DIAGRAM V I(BAT) ISET V O(REG) I (DETECT) I (FAULT) CHG ENABLE V (ISET) ENABLE ENABLE VSET REFERENCE CHG ENABLE V O(REG) AND BIAS V I(BAT) DEGLITCH V (SLP) I (FAULT) ENABLE...
  • Page 275 bq24010, bq24012, bq24013, bq24014 www.ti.com SLUS530D − SEPTEMBER 2002 − REVISED SEPTEMBER 2003 TYPICAL CHARACTERISTICS DROPOUT VOLTAGE JUNCTION TEMPERATURE I O(OUT) = 1000 mA I O(OUT) = 750 mA I O(OUT) = 500 mA I O(OUT) = 250 mA −50 T J −...
  • Page 276 bq24010, bq24012, bq24013, bq24014 www.ti.com SLUS530D − SEPTEMBER 2002 − REVISED SEPTEMBER 2003 FUNCTIONAL DESCRIPTION The bqTINYt supports a precision Li-Ion, Li-Pol charging system suitable for single-cells . Figure 2 shows a typical charge profile, application circuit and Figure 5 shows an operational flow chart. BATTERY PACK bq24010DRC...
  • Page 277 bq24010, bq24012, bq24013, bq24014 www.ti.com SLUS530D − SEPTEMBER 2002 − REVISED SEPTEMBER 2003 SLEEP MODE > V I(BAT) checked at Indicate SLEEP all times MODE Regulate O(PRECHG) Reset and Start < V I(BAT) (LOWV) timer (PRECHG) Indicate Charge-in-Progress Reset all timers start t (CHG) timers...
  • Page 278 bq24010, bq24012, bq24013, bq24014 www.ti.com SLUS530D − SEPTEMBER 2002 − REVISED SEPTEMBER 2003 FUNCTIONAL DESCRIPTION TEMPERATURE QUALIFICATION NOTE:The temperature qualifications apply only to versions with temperature sense input (TS) pin option (bq24010 and bq24014). Versions of the bqTINY with the TS pin option, continuously monitor battery temperature by measuring the voltage between the TS and VSS pins.
  • Page 279 bq24010, bq24012, bq24013, bq24014 www.ti.com SLUS530D − SEPTEMBER 2002 − REVISED SEPTEMBER 2003 FUNCTIONAL DESCRIPTION BATTERY PRE-CONDITIONING During a charge cycle if the battery voltage is below the V threshold, the bqTINY applies a precharge current, (LOWV) , to the battery. This feature revives deeply discharged cells. The resistor connected between the ISET O(PRECHG) and V , determines the precharge rate.
  • Page 280 bq24010, bq24012, bq24013, bq24014 www.ti.com SLUS530D − SEPTEMBER 2002 − REVISED SEPTEMBER 2003 FUNCTIONAL DESCRIPTION After charge termination, the bqTINY restarts the charge once the voltage on the BAT pin falls below the V (RCH) threshold. This feature keeps the battery at full capacity at all times. Please see Battery Absent Detection section for additional details.
  • Page 281 bq24010, bq24012, bq24013, bq24014 www.ti.com SLUS530D − SEPTEMBER 2002 − REVISED SEPTEMBER 2003 FUNCTIONAL DESCRIPTION BATTERY ABSENT DETECTION For applications with removable battery packs, bqTINY provides a battery absent detection scheme to reliably detect insertion and/or removal of battery packs. The voltage at the BAT pin is held above the battery recharge threshold, V , by the charged battery following (RCH)
  • Page 282 bq24010, bq24012, bq24013, bq24014 www.ti.com SLUS530D − SEPTEMBER 2002 − REVISED SEPTEMBER 2003 FUNCTIONAL DESCRIPTION TIMER FAULT RECOVERY As shown in Figure 5, bqTINY provides a recovery method to deal with timer fault conditions. The following conditions summarize this method. Condition #1: Charge voltage above recharge threshold (V ) and timeout fault occurs (RCH)
  • Page 283 bq24010, bq24012, bq24013, bq24014 www.ti.com SLUS530D − SEPTEMBER 2002 − REVISED SEPTEMBER 2003 APPLICATION INFORMATION SELECTING INPUT CAPACITOR In most applications, all that is needed is a high-frequency decoupling capacitor. A 0.47-µF ceramic, placed in close proximity to V and V pins, works well.
  • Page 284 bq24010, bq24012, bq24013, bq24014 www.ti.com SLUS530D − SEPTEMBER 2002 − REVISED SEPTEMBER 2003 APPLICATION INFORMATION PCB LAYOUT CONSIDERATIONS It is important to pay special attention to the PCB layout. The following provides some guidelines: To obtain optimal performance, the decoupling capacitor from V to V and the output filter capacitors from BAT to ISET should be placed as close as possible to the bqTINY, with short trace runs to both signal and V...
  • Page 285 bq24010, bq24012, bq24013, bq24014 www.ti.com SLUS530D − SEPTEMBER 2002 − REVISED SEPTEMBER 2003 DRC (S−PDSO−N10) CUSTOM DEVICE PLASTIC SMALL OUTLINE 3,25 2,75 3,25 2,75 PIN 1 INDEX AREA TOP AND BOTTOM 1,00 0,80 0,20 REF. 0,08 SEATING PLANE 0,05 0,00 2,48 2,23 0,50...
  • Page 286 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete.
  • Page 287 Si2323DS New Product Vishay Siliconix P-Channel 20-V (D-S) MOSFET FEATURES PRODUCT SUMMARY D TrenchFETr Power MOSFET APPLICATIONS DS(on) 0.039 @ V = -4.5 V -4.7 D Load Switch 0.052 @ V = -2.5 V - 4.1 D PA Switch 0.068 @ V = -1.8 V - 3.5 TO-236...
  • Page 288 Si2323DS New Product Vishay Siliconix SPECIFICATIONS (T = 25_C UNLESS OTHERWISE NOTED) Limits Parameter Symbol Test Conditions Unit Static = -250 mA Drain-Source Breakdown Voltage = 0 V, I (BR)DSS = -250 mA Gate-Threshold Voltage -1.0 -0.40 GS(th) = "8 V "100 Gate-Body Leakage = 0 V, V...
  • Page 289 Si2323DS New Product Vishay Siliconix TYPICAL CHARACTERISTICS (25_C UNLESS NOTED) Output Characteristics Transfer Characteristics = 5 thru 2.5 V = -55_C 25_C 125_C 1.5 V - Drain-to-Source Voltage (V) - Gate-to-Source Voltage (V) On-Resistance vs. Drain Current Capacitance 0.15 1800 1500 0.12 1200...
  • Page 290 Si2323DS New Product Vishay Siliconix TYPICAL CHARACTERISTICS (25_C UNLESS NOTED) Source-Drain Diode Forward Voltage On-Resistance vs. Gate-to-Source Voltage 0.15 0.12 = 150_C 0.09 = 4.7 A = 25_C = 2 A 0.06 0.03 0.00 - Source-to-Drain Voltage (V) - Gate-to-Source Voltage (V) Threshold Voltage Single Pulse Power = 140 mA...
  • Page 291 P_VDD3 /MUTE CD_SCOR P_VDD3 CD_SENS 1N4148 SMD CD_CLOK CD_XLAT CD_DDAT LOW_POWER BATT_DET CD_XRST RF_SPEED P_GND VCC25 2.2K SCLK CD_SQCK IR_IN 8050 SOT23 CD_DATA AUD_BLCK 4 CD_LRCK AUD_LRCK 4 VCC3 CD_BLCK AUD_DATA 4 FCM1608-601 AUD_XCK 4 100uF/6.3V C130 C131 C132 VID_P/N 3 (27MHz) VID_CLK 3 10uF/6.3V/1206...
  • Page 292 RAM_A[0..11] RAM_D[0..15] R124 ROM_A[0..17] ROM_D[0..7] RAM_A0 RAM_D0 RAM_D1 RAM_A1 RAM_D2 RAM_A2 ROM_A0 ROM_D0 RAM_A3 RAM_D3 ROM_A1 ROM_D1 RAM_A4 RAM_D4 ROM_A2 ROM_D2 RAM_D5 RAM_A5 ROM_A3 ROM_D3 RAM_D6 RAM_A6 ROM_A4 ROM_D4 RAM_A7 RAM_D7 ROM_A5 ROM_D5 RAM_A8 RAM_D8 ROM_A6 ROM_D6 RAM_A9 RAM_D9 ROM_A7 ROM_D7 RAM_A10 RAM_D10...
  • Page 293 VID_VCC3 VID_VCC3 22pF VID_D[0..7] VID_D7 VID_VSYNC VSYNC VID_VSYNC 1 VID_D6 VID_HSYNC HSYNC VID_HSYNC 1 VID_D5 VID_CVBSY CVBS/Y VID_D4 MMBD4148SE SOT-23 VID_D3 1.8uH CVBS/C VID_D2 VID_VBIAS VBIAS VID_D1 VID_FSAD FSADJUST VID_D0 VID_COMP COMP MODEA VREF_OUT VID_P/N VID_VREF VID_P/N MODEB VREF_IN VID_CLK VID_CLK VID_GND XTALO...
  • Page 294 AUD_XCK AUD_LRCK LRCK SCKI AUD_DATA DATA P_VDD3 AUD_BLCK AUD_DEM 6 P_VDD3 ROUT LOUT R121 AUD_VCC3 ROUT LOUT /MUTE 220uF/6.3V WM8714 SOP 10uF/6.3V/1206 /OFF AUD_GND R112 AUD_GND 150K CVBS VID_GND MMBD4148CA OUT1 C148 R132 CVBS AUD_GND 220uF/6.3V AUD_GND BH3544 SOP AUD_VCC3 CVBS 220uF/6.3V R110...
  • Page 295 START P_VDD3 ROM/RW R163 ROM/RW HOLD P_VDD3 MMBD4148CC (RE2) C139 VDD3 C138 C137 CDD2 CDD1 C136 (RC0) (VDD) 10uF/6.3V/1206 3.3K XOUT1 P_VDD3 XIN1 OPEN /RES (RA2) C126 GR2003/SMD PCB R164 P_VDD3 VOL+ PLAY/PAUSE ROM/RW K1-1 IT1207 SMD SLLB120200 100K 100K VOL- FF/NEXT K1-2...
  • Page 296 MOT_FRDR 7 MOT_FFDR 7 CD_VC MOT_TRDR 7 MOT_TFDR 7 RF_FE MOT_SRDR 7 RF_SE MOT_SFDR 7 RF_TE MOT_LIM 7 MOT_MDP 7 R115 P_VDD3 D_GND D_VDD3 FCM2012K-601B P_VDD3 A_GND C125 FCM2012K-601B 10uF/6.3V/1206 PLL_VDD D_GND MIRR COUT RF_DC RFDC DVSS0 RF_AC ADIO WDCK AVSS0 CD_SCOR 1 IGEN...
  • Page 297 8.2K D_VDD3 6P1.5 卧式 MOT_MDP 6 CD_VC 6,8 MOT_LIM 6 CD_VC 6,8 7.5K D_GND C149 7.5K MOT_TFDR 6 P_VDD3 MOT_TRDR 6 MOT_GND D_GND R109 NJM2100 SOP-8 D_VDD3 CD_VC R106 AMUTE BATT_DET MUTE2 MOT_VDD HVCC D_VDD3 MUTE34 P_VDD CLKIN START D_GND CD_VC 6,8 VREF FAN8038 QFP...
  • Page 298 RF_VDD P_VDD3 RF_VDD FCM2012K-601B FCM2012K-601B 2N3906 C106 C107 C104 C105 1N4148 SMD C121 C103 47uF/6.3V 47uF/6.3V 47uF/6.3V A_GND A_GND RF_VDD R130 C150 RF_VDD AGCVTH 100uF/6.3V LD_ON RF_LDON 1 7.5K R134 8.2K AGCCONT C153 105 A_GND RFTC A_GND 7.5K R135 8.2K RF_I CD_VC R129...
  • Page 299 S8520/1x31MC S8520/1x30MC 1.2K R1224N102 2.7K P_VDD SI2305DS SOT23 47uH DCR 0.1 P_VDD3 C100 220uF/6.3V POW_DCIN 1N5819 SMD 1.2K 1% 220uF/6.3V 1N4001 DO-41 P_GND P_GND DS-336-113 R1224N102M/S8520D30MC SOT-23-5 VOUT P_GND 1N5819 DO-41 R119 CHG_VCC P_GND R107 P_VDD3 P_VDD 33K 1% P_GND SI2305DS SOT23 P_VDD3 P_GND...

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