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Table of Contents
Summary of Contents for Hifn 9155
- Page 1 9150, 9155 Evaluation Card User Guide Hifn Confidential...
- Page 2 04/10 No part of this publication may be reproduced, transmitted, transcribed, stored in a retrieval system, or translated into any language in any form by any means without the written permission of Hi/fn, Inc. (“Hifn”) Licensing and Government Use Any Hifn software (“Licensed Programs”) described in this document is furnished under a license and may be used and copied only in accordance with the terms of such license and with the inclusion of this copyright notice.
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Page 3: Table Of Contents
Block Diagram ........2.2.2 Hifn Security Processor Chip ......2.2.3 Gigabit Ethernet Interfaces . - Page 4 Environmental ..........37 Addendum I Document Changes/Revisions ....38 9150, 9155 Evaluation Card User Guide, UG-0210-00 Page 4...
- Page 5 Figure 4-7. JP41 Flash/RTC Select Header Diagram ......32 9150, 9155 Evaluation Card User Guide, UG-0210-00 Page 5...
- Page 6 Table 6-2. Environmental Specifications ....... . 37 9150, 9155 Evaluation Card User Guide, UG-0210-00...
- Page 7 9150/9155 Evaluation Card. The term “915x” will be used to denote either of the 9150 or 9155 devices. A single evaluation card supports both the 9150 and 9155 devices and has the following part...
- Page 8 Chapter 6, “Specifications", lists the A/C, D/C and environmental specification for the evaluation card. Customer Support For technical support about this product, please contact your local Hifn sales office, representative, or distributor. Web Site For general information about Hifn and Hifn products refer to: www.hifn.com...
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Page 9: Introduction
The primary ports are capable of operating at 10/100/1000 Mbps speeds (in copper mode). The Hifn 915x FlowThrough™ security processor chip is the heart of this card. Its two host ports and two network ports interface through four separate single-port Gigabit PHY devices to the rear panel Ethernet connectors. -
Page 10: Figure 1-1. Evaluation Card Typical Application
This is easily achieved due to the FlowThrough nature of the Hifn 915x devices. From the host perspective, software commands sent out the Ethernet port will be intercepted and acted upon just as if the chip were installed on the same PCB as the host GMAC/TOE/Network Processor. -
Page 11: Overview
Figure 2-1 below identifies the significant functional components on the evaluation card with the exception of the LEDs, jumpers, connectors, and switches, which are described fully in a later chapter. The Hifn security processor chip is in the center of the card and clearly labeled. -
Page 12: Functional Overview
2.2 Functional Overview 2.2.1 Block Diagram Figure 2-2. Evaluation Card Block Diagram 9150, 9155 Evaluation Card User Guide, UG-0210-00 Page 12 Hifn Confidential... -
Page 13: Hifn Security Processor Chip
2.2.2 Hifn Security Processor Chip At the heart of the evaluation card is the Hifn 915x applied services processor. The 915x device combines high performance throughput, full Internet Key Exchange (IKE) support, Internet Protocol Security (IPsec) support, and Internet Protocol Payload Compression (IPComp) support with the intelligent packet processing functionality of Hifn's product family. -
Page 14: Ddr2 Sdram Interface
MAC addressing, ARP, etc. The MII interface consists of the seven RMII signals, a Fast Ethernet PHY transceiver, and an integrated magnetics-RJ45 connector module. 9150, 9155 Evaluation Card User Guide, UG-0210-00 Page 14 Hifn Confidential... -
Page 15: Jtag Interface
In addition, the JTAG interface is used for chip manufacturing tests and is also used by Hifn for developing and debugging the firmware for the embedded processors. The JTAG connector and pin descriptions are shown in a later chapter. -
Page 16: Table 2-3. General Purpose I/O Pins
Most of the GPIO pins have pre-defined functions as shown in the table below. These functions are subject to change, so the user should consult the latest data sheet revision applicable to the Hifn device selected for detailed and accurate GPIO descriptions. Table 2-3. General Purpose I/O Pins... - Page 17 CPLD (GPIO Mux) esc_gpio[2] eSC_Flash_ 100M/1G Boot 1= 100M boot, 0= 1G CPLD (GPIO Mux) boot esc_gpio[1] eSC_Flash_ Unused Unused GPIO Mux esc_gpio[0] eSC_Flash_ Unused Unused CPLD (GPIO Mux) 9150, 9155 Evaluation Card User Guide, UG-0210-00 Page 17 Hifn Confidential...
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Page 18: Connectors
Evaluation Card: Figure 3-1. 915x Evaluation Card Connectors 3.1 Power Connectors The 915x Hifn Evaluation Card can be powered from either an external power supply or through the PCI connector. Two voltages are required for proper operation: +5V and +3.3V. -
Page 19: P4: Pci Connector
Do not reverse polarity on power connections. Possible damage to the card may result 3.2 Ethernet Connectors Four Gigabit Ethernet interfaces and one RMII 100Mbps Ethernet interface exist on this card. 9150, 9155 Evaluation Card User Guide, UG-0210-00 Page 19 Hifn Confidential... -
Page 20: U54, U56: Sfp Connectors
(I2C via GPIO) that is connected through the on-card CPLD device. Since all SFP modules are hard-wired for the same I2C address, the evaluation card also includes an I2C mux that can be accessed via I2C commands. Please contact Hifn for further details on GPIO-driven SFP communication. -
Page 21: Debug Connectors
Table 3-4. JTAG Connector Pinout Pin Number Description +3.3V JTAG_RST*: This signal is not supported in the Hifn security chip and should be left unconnected. JTAG_TCK: JTAG Test Clock JTAG_TDI: JTAG Test Data Input JTAG_TDO: JTAG Test Data Output JTAG_TMS: JTAG Test Mode Select Caution Care must be taken when attaching cables to the JTAG header. -
Page 22: Amp Mictor Headers
PCB. Note that the 38-pin MICTOR connector is surface-mounted on the evaluation card. It should also be noted that the connector includes through-hole ground pins, which provides good noise immunity. 9150, 9155 Evaluation Card User Guide, UG-0210-00 Page 22 Hifn Confidential... -
Page 23: Figure 3-3. Debug Connector Usage
Agilent (pn E5346A). Table 3-6. J6: Net-0/Net-1Gigabit Port Pin Number Signal Pin Number Signal N0_TXC N1_TXC (Note 1) N0_SFP_RLOS N0_PHY_SDET N0_TXD4 N1_TXD4 N0_TXD3 N1_TXD3 N0_TXD2 N1_TXD2 N0_TXD1 N1_TXD1 N0_TXD0 N1_TXD0 9150, 9155 Evaluation Card User Guide, UG-0210-00 Page 23 Hifn Confidential... -
Page 24: Table 3-7. J5: Host-1 Gigabit Port
H1_RXD7 H1_TXD6 H1_RXD6 H1_TXD5 H1_RXD5 H1_TXD4 H1_RXD4 H1_TXD3 H1_RXD3 H1_TXD2 H1_RXD2 H1_TXD1 H1_RXD1 H1_TXD0 H1_RXD0 Table 3-8. J7: Host-0 Gigabit Port Pin Number Signal Pin Number Signal H0_GTXCLK H0_PHY_REFCLK 9150, 9155 Evaluation Card User Guide, UG-0210-00 Page 24 Hifn Confidential... -
Page 25: Table 3-9. J1: System Interfaces
DPU_GPIO_15 DPU_GPIO_15 MDIO DPU_GPIO_14 DPU_GPIO_13 PHY_INTERRUPT DPU_GPIO_12 SFP_SCL DPU_GPIO_11 SFP_SDA DPU_GPIO_10 DPU_GPIO_9 DPU_GPIO_8 DPU_GPIO_7 ESC_GPIO7 DPU_GPIO_6 ESC_GPIO6 DPU_GPIO_5 ESC_GPIO5 DPU_GPIO_4 ESC_GPIO4 DPU_GPIO_3 ESC_GPIO3 DPU_GPIO_2 ESC_GPIO2 DPU_GPIO_1 ESC_GPIO1 DPU_GPIO_0 ESC_GPIO0 9150, 9155 Evaluation Card User Guide, UG-0210-00 Page 25 Hifn Confidential... -
Page 26: Table 3-10. J2: Ddr2 Addr/Ctl
DDR2_A9 DDR2_A13 Table 3-11. J3: DDR2 Data Pin Number Signal Pin Number Signal DDR2_DQ26 DDR2_DQ31 DDR2_DQ27 DDR2_DQ30 DDR2_DQ28 DDR2_DQ25 DDR2_DQ29 DDR2_DQ24 DDR2_DQ20 DDR2_DQ19 DDR2_DQ21 DDR2_DQ18 DDR2_DQ22 DDR2_DQ17 DDR2_DQ23 DDR2_DQ16 9150, 9155 Evaluation Card User Guide, UG-0210-00 Page 26 Hifn Confidential... -
Page 27: Table 3-12. Jp48: 915X Serial Port
Pin Number Description Signal Bottom pin, rectangular pad RXIN on back of PCB Center pin Top pin TXOUT 3-pin right-angle rectangular connector, Amp 103361-1. Mating connector is Amp 103976. 9150, 9155 Evaluation Card User Guide, UG-0210-00 Page 27 Hifn Confidential... -
Page 28: Jumpers, Leds, And Switches
1: Jumper Not Installed The text inside parenthesis represents the identification of the header in the silkscreen on the PCB. Also, default manufacturing jumper settings are highlighted in bold. 9150, 9155 Evaluation Card User Guide, UG-0210-00 Page 28 Hifn Confidential... -
Page 29: Jp34: Device Id Header (Dev-Id)
Setting Device ID = '000' (Default) 4.1.2 JP45: Secure Features Header (SEC) These jumpers are for Hifn use only and should not be modified. Figure 4-3. JP45 Secure Features Jumpers Diagram 4.1.3 JP49: System Configuration Header 1 (MISC-1) Figure 4-4. JP49 System Configuration Header 1 Diagram... -
Page 30: Jp42: System Configuration Header 2 (Misc-2)
0 = SerDes transmit level = 1.0V 1 = SerDes transmit level = 1.16V 4.1.4 JP42: System Configuration Header 2 (MISC-2) Figure 4-5. JP42 System Configuration Header 2 Diagram 9150, 9155 Evaluation Card User Guide, UG-0210-00 Page 30 Hifn Confidential... -
Page 31: Jp43: Smi/I2C Interface Select Header
Two of the 915x's GPIOs can be used as either Flash interface signals (FLASH_CLK and CLASH_CS1_N) or RTC interface signals (AUX_SCL/AUX_SDA). The following two jumpers are used to provide this selection. 9150, 9155 Evaluation Card User Guide, UG-0210-00 Page 31 Hifn Confidential... -
Page 32: Leds
Net-1 Link (1G) (Marvell): LED_TX Host-1 Transmit Activity (Marvell): LINK1000 Host-1 Link (1G) (Vitesse): LED_1 Net-0 Link10/100/Activity (Vitesse): LED_0 Net-0 Link1000/Activity (Vitesse): LED_1 Host-0 Link10/100/Activity (Vitesse): LED_0 Host-0 Link1000/Activity 9150, 9155 Evaluation Card User Guide, UG-0210-00 Page 32 Hifn Confidential... -
Page 33: Card Status Led
Two LED's provide visual indication of the state of 915x's DPU and eSC processors and firmware. The state of these LED's is undefined when the GPIO outputs are being used for PC Mode (Hifn Use Only). 9150, 9155 Evaluation Card User Guide, UG-0210-00 Page 33 Hifn Confidential... -
Page 34: Switches
Table 4-11. Switches Switch Description SW1 (TMPR) Hifn Use Only SW2 (BR RST) Card Reset When depressed, resets all on-card logic including PHY and 915x devices. SW3 (RSVD) Hifn Use Only 9150, 9155 Evaluation Card User Guide, UG-0210-00 Page 34 Hifn Confidential... -
Page 35: Operation
PHY devices. The RMII Ethernet port is also configured through MDIO operations between the Hifn security processor and the 100 Mbps PHY. Some of the significant register assignments that are set with the evaluation card Flash memory are listed in the following sections. -
Page 36: Mii Port
5.1.3 MII Port • Speed: 100 Mbps forced • Duplex: Half • Pause Frames: N/A 9150, 9155 Evaluation Card User Guide, UG-0210-00 Page 36 Hifn Confidential... -
Page 37: Specifications
SDRAM Clock Frequency 200 MHz (DDR400) Maximum Power Consumption 15 Watts (+5V/+3.3V Combined) 6.2 Environmental Table 6-2. Environmental Specifications Specification Description Temperature (operating) 0°C to 50°C Temperature (storage) -20°C to 75°C 9150, 9155 Evaluation Card User Guide, UG-0210-00 Page 37 Hifn Confidential... -
Page 38: Addendum I Document Changes/Revisions
Document Changes/Revisions Documentation Changes include additions, deletions, and modifications made to this document. This section identifies the changes made in each release of the document. Document Revision 00 Initial release. 9150, 9155 Evaluation Card User Guide, UG-0210-00 Page 38 Hifn Confidential... - Page 39 48720 Kato Road Fremont, CA 94538 tel: 510.668.7000 www.hifn.com Hifn Confidential...
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