Albedo AT-2048 Installation And Maintenance Manual page 27

5.4 Multiplexing Level 4: 140 Mbit/s
The structure of this frame is described in the ITU-T Rec. G.751 (see Figure 20). In
this case, the frame is divided into six groups:
•
Group I contains the FAS, with sequence "111110100000;" the A-bit (remote
alarm); the S-bit (spare); and 472 T-bits (tributary) transporting data.
•
Groups II, III, IV, and V contain a block of four J-bits (justification control)
and 484 T-bits transporting data.
•
Group VI contains a block of four J-bits, a block of R-bits (justification oppor-
tunity), one per tributary, and 376 T-bits. To check whether R-bits have been
used, the J-bits are analyzed in each of the groups II, III, IV, V, and VI (there
are five per tributary). Ideally the R-bit does not carry useful information on
41.9% of the occasions.
The PDH hierarchy, with four levels from 2 to 140 Mbit/s. A bit-oriented justification process is
used to fit tributaries created with different clocks in the second, third, and fourth hierarchy.
Standard Binary Rate
G.704/732 2,048 kbit/s±50 ppm
G.742 8,448 kbit/s±30 ppm
G.751 34,368 kbit/s±20 ppm
G.751 139,264 kbit/
s±15 ppm
5.5 Service Bits in Higher Level Frames
In any of the groups containing the FAS in the 8-, 34-, and 140-Mbit/s frames,
alarm bits and spare bits are also to be found. These are known as service bits. The
A-bits (alarm) carry an alarm indication to the remote multiplexing device, when
certain breakdown conditions are detected in the near-end device. The spare bits are
designed for national use, and must be set to "1" in digital paths that cross interna-
tional boundaries.
5.6 Plesiochronous Synchronization
As far as synchronization is concerned, the multiplexing of plesiochronous signals
is not completely trouble free, especially when it comes to demultiplexing the cir-
cuits. In a PCM multiplexer of 30 + 2 channels, a sample of the output signal clock
(1/32) is sent to the coders, so that the input channels are synchronized with the out-
put frame. However, higher level multiplexers receive frames from lower level
multiplexers with clocks whose value fluctuates around a nominal frequency value
within certain margins of tolerance.
E1 testing
Table 3
Size Frame/s
256 bits 8,000
848 bits 9,962.2
1536 bits 22,375.0
2928 bits 47,562.8
Code Amplitude
HDB3 2.37-3.00V
HDB3 2.37V
HDB3 1.00V
CMI 1.00V
27
Attenuation
6 dB
6 dB
12 dB
12 dB