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11.8. A-Board (4/12) Schematic Diagram
GENX4 PIO
1
IIC
2
TO 2/12
EA[8:23] for No FS board
LiteII
R8953
EXB2HV680JV
EA08
VI2P12
EA09
VI2P13
EA10
VI2P14
EA11
VI2P15
EA12
VI2P16
EA13
VI2P17
EA14
VI2P18
EA15
VI2P19
EA16
VI2P22
EA17
VI2P23
EA18
VI2P24
EA19
VI2P25
EA20
VI2P26
EA21
VI2P27
EA22
VI2P28
EA23
VI2P29
R8952
EXB2HV680JV
ExBUS
TO 5/12
AA_XRST
AA_XRST
STB5V
SUB3.3V
R8950
R8946
R8944
0
0
22k
Q8852
STB_RST
R8938
Q8850
2SD0601A0L
10k
2SD0601A0L
R8942
R8945
47k
10k
R8936
R8943
10k
47k
R8937
Q8853
47k
2SD0601A0L
R8868
68
A-BOARD (4/12)
!
3
TH-46PZ81FV
A-Board (4/12) Schematic Diagram
28
29
TO 2/12
LiteII
R8867
EXB2HV680JV
ADDRESS MPXed, if D-Latch
AA_EA8
AA_ED0
ExBUS
ED0
/EA8
AA_EA9
AA_ED1
ED1
/EA9
AA_EA10
AA_ED2
ED2
/EA10
AA_EA11
AA_ED3
ED3
/EA11
AA_EA12
AA_ED4
ED4
/EA12
AA_EA13
AA_ED5
ED5
/EA13
AA_EA14
AA_ED6
ED6
/EA14
AA_EA15
AA_ED7
ED7
/EA15
AA_EA16
AA_ED8
ED8
/EA16
AA_EA17
AA_ED9
ED9
/EA17
AA_EA18
AA_ED10
ED10
/EA18
AA_EA19
AA_ED11
ED11
/EA19
AA_EA20
AA_ED12
ED12
/EA20
AA_EA21
AA_ED13
ED13
/EA21
AA_EA22
AA_ED14
ED14
/EA22
AA_EA23
AA_ED15
/EA23
ED15
R8866
ED/EA with Int.PU at start
EXB2HV680JV
(XECS2, 3 setting)
R8865
EXB2HV680JV
AA_EA0
EA0
AA_EA1
EA1
AA_EA2
EA2
ExBUS
AA_EA3
EA3
AA_EA4
EA4
AA_EA5
EA5
AA_EA6
EA6
AA_EA7
EA7
AA_EA24
VI2P4
EA24
INT.PD
R8710
68
SUB3.3V
clk_mode[0-5]
Debug Use
SUB3.3V
B_PORT
R8935
10k
RMCO
PORT16[5]
POWER_DET
Hi-Z
SUB3.3V
SUB3.3V
to SUB_TUNER
ed_pullup_sel
H:Int.PU on ED
AA_FE_XRST
ExBUS
R8264
10k
XECS3, 5, 7: USED FOR OTHER PORPOSE PINS
AA_FE_XRST
R8947
68
XNFWE
PORT14[7], FE_XRST
INT.PU
see also SDA2 for ea_pullup_sel
AA_XECS0
R8877
68
XECS0
OUTPUT
AA_XECS1
R8878
68
XECS1
OUTPUT
R8879
68
XECS2
(ed_pullup_sel)
AA_XEAS
R8880
68
XECS4
OUTPUT/(BOOTBT)
BOOTBT
L:ADMPX
AA_XNMIRQ
R8882
68
XNMIRQ
INT.PU
AA_XIRQ1
R8883
68
XIRQ1
NEED EXT.PU
AA_XIRQ2
R8884
68
NET0034484
XIRQ2
NEED EXT.PU
XIRQ3 for HDMI_INT in ADV sheet
AA_ERXW
R8885
68
ERXW
INT.PU
AA_XERE
R8886
68
XERE
INT.PU
AA_XEWE0
R8887
68
XEWE0
INT.PU
AA_XEWE1
R8888
68
XEWE1
INT.PU
AA_XEDK
R8889
68
XEDK
INT.PU
AA_ECLK
R8890
68
ECLK
OUTPUT
AA_ESZ0
R8891
68
ESZ0
OUTPUT
AA_ESZ1
R8892
68
ESZ1
OUTPUT
AA_BOOTSWAP
R8894
68
BOOTSWAP
INT.PU
TP8851
AG_DTV_VOUTENB
0
R8896
VOUTENB
INT.PD
AG_SD_BOOT_STS
0
R8897
AUDCLK
PORT0[0], SDBOOT
KEEP L at reset (normal boot), if GENX doesn't output H.
R8898
R8963
10k
10k
R8900
68
SBI0
DUBUG/JIG
R8901
68
SBO0
INT.PU
TO 8/12
AA_SBI0
AA_SBO0
TO 8/12
R8959
68
AA_FE_SW
IS1VAL
PORT7[7] FE_SW/ SDRAM_CHK1
INT_PD
R8960
68
AA_SDRAM_CHK2
IS1PSYNC
PORT8[0] SDRAM_CHK2
INT_PU
JTAG
30
31
TO 2/12
TO 2/12
LiteII
Output Port need no Ext.PD.
INT.PD
YC
YUV RGB
-
V
R
C
U
B
Y
Y
G
Comp. Comp. Comp.
AG_CLK74SEL
CLKGEN_S2
R8927
0
RESERVED
N.C. for CLKGEN port
PORT9[4] EEPROM_WP
PU, PORT14[6]
pcitest_sg
CI I/F
IS1CLK
CI_OCP
IS1CLK
PORT16[3], CI_OCP
Hi-Z
SMTCLK0
CI_POWER_ON
INT_PD
PORT15[5], FE1_XIRQ
SMTCLK0
PORT5[4], CI_POWER_ON
Hi-Z
R8929
Hi-Z
AC_CHDI0
EXB2HVR000V
XDCD0
INT_PD
PORT15[4], ETHER_XIRQ
AC_CHDI1
XCTS0
INT.PD
PORT16[1], ETHER_XRST
AC_CHDI2
XRI0
AC_CHDI3
TXD0
AC_CHDI4
RXD0
AC_CHDI5
SMTCLK1
AC_CHDI6
SMTD1
CI PARALLEL TS
AC_CHDI7
SMTRST1
Hi-Z
HI-Z
PORT7[0], CHINA_FE_SW
AC_CHVAL
XRTS0
AC_CHSYNC
R8851
0
XDTR0
AC_CHCLK
R8852
0
XDSR0
R8853
PORT15[0], H FIXED
0
SMTCMD0
XPDCD1
SMTCMD0
Hi-Z
SMTSEL0
XPDCD2
INT_PD
PORT16[4], USB_OCP
SMTSEL0
Hi-Z
CH1VAL
XCI_IREQ
CH1VAL
PORT16[6], CI_XIREQ
Int.PU
AC_XPDWT
R8854
SMTD0
Hi-Z
INT.PD, PORT16[2], DDR_CLK_SEL
VJUMP1005-S
AC_REG
NFCLE
PORT7[1], REG, Hi-Z
R8855
68
AC_XPDOE
XEXDMK0
INT.PU
R8856
68
AC_XPDWE
XEXDMR0
Hi-Z
R8857
68
AC_IORD
SMTCMD1
Hi-Z
AC_IOWR
R8858
68
SMTSEL1
Hi-Z
R8859
68
AC_XPDCE2
XECS6
INT.PU
R8860
68
AC_XEDBA
SMTRST0
Hi-Z
R8954
68
AC_XETS
PORT14[5], XETS
INT.PU
XNFCE
AA_ED0
AC_XEAB
R8862
68
CH1DATA
PORT5[7], XEAB
INT.PU
AA_ED1
R8863
68
AC_CI_RESET
AA_ED2
XNFWP
PORT7[2], CI_RESET
INT.PD
R8864
68
AA_ED3
AA_ED4
AA_ED5
Need PD for All Model
AA_ED6
DVB-T SERIAL TS
DVBT_CH0CLK
AA_ED7
R8221
CH0CLK
Hi-Z
DVBT_CH0PSYNC
AA_ED8
R8222
CH0PSYNC
CH0PSYNC
INT.PD
DVBT_CH0VAL
CH0VAL
AA_ED9
R8223
CH0VAL
INT.PD
DVBT_CH0DATA
AA_ED10
R8224
CH0DATA
CH0DATA
INT.PD
AA_ED11
R8328
AA_ED12
10k
AA_ED13
AA_ED14
DVB-S SERIAL TS
CPU BUS
AA_ED15
DVBS_IS0CLK
R8225
IS0CLK
IS0CLK
Hi-Z
AA_EA1
R8285
10k
AA_EA2
AA_EA3
AA_EA4
AA_EA5
AA_EA6
AA_EA7
AA_EA23
AA_XERE
AA_ERXW
32
33
48
AG_CLK74SEL
AG_SD_BOOT_STS
AG_DTV_VOUTENB
AG_SW_OFF_DET
STB_RST
R8501
100
AH_IECOUT0
OUTPUT
IECOUT0
R8502
330
AH_SRCK0
SRCK0
AH_LRCK0
R8503
330
LRCK0
330
AH_DMIX0
R8504
DMIX0
AH_DAUDIO
R8506
330
DAUDIO
MVDACO1
Comp.
TO 2, 9/12
MVDACO1
MVDACO1
R8510
AH_DAUDIO
160
1%
AH_DMIX0
SUB3.3V
AH_SRCK0
AH_LRCK0
R8604
C8601
AH_IECOUT0
16V
0.1u
1
A0
8
R8603
LITEII EEPROM WP
VCC
47k
2
7
A1
WP_PL2_CN
WP
R8658
22
3
6
A2
LITE2-EEP_SCL
SCL
4
VSS
5
LITE2-EEP_SDA
SDA
R8605
68
VI2CLK2
EEPROM
SUB3.3V
R8255
10k
XNFRE
SUB3.3V
SUB3.3V
SUB3.3V
R8655
LAN needs PU1k
10k
move to
R8266
R8280
R8196
sht006/016
10k
1k
1k
R8208
68
VI1P1
FE1_IRQ
R8194
68
ETHER_XECS
XECS7
AA_XECS7
VI1P20
R8195
68
R10017
TO 2/12
VI2P11
VI1P20
AA_ETHER_XRST
SUB3.3V
R8659
10k
Need to reset LAN at default
NFALE
NFALE
TO 2/12
SUB3.3V
R8556
10k
NANDRYBY
SUB3.3V
R8751
1k
IS1DATA
VI2P10
Hi-Z
VI2CLK
R8861
R8657
10k
10k
AA_ED0
DVBS TS serial to IS0
AA_ED1
AA_ED2
DVBS_IS0CLK
DVBS_IS0CLK
AA_ED3
DVBS_IS0PSYNC
DVBS_IS0PSYNC
AA_ED4
DVBS_IS0VAL
DVBS_IS0VAL
AA_ED5
DVBS_IS0DATA
DVBS_IS0DATA
AA_ED6
AA_ED7
AA_ED8
AA_ED9
AA_ED10
AA_ED11
TS parallel throughed CI to HS
AA_ED12
AC_CHCLK
AA_ED13
AC_CHCLK
AC_CHSYNC
AA_ED14
AC_CHSYNC
AC_CHVAL
AA_ED15
AC_CHVAL
AC_CHDI0
AC_CHDI0
AC_CHDI1
AA_EA1
AC_CHDI1
AC_CHDI2
AA_EA2
AC_CHDI2
AC_CHDI3
AA_EA3
AC_CHDI3
AC_CHDI4
AA_EA4
AC_CHDI4
AC_CHDI5
AA_EA5
AC_CHDI5
AC_CHDI6
AA_EA6
AC_CHDI6
AC_CHDI7
AA_EA7
AC_CHDI7
AA_EA23
AA_XERE
AA_ERXW
34
35
GENX4
TO 6/12
AG_CLK74SEL
AG_SD_BOOT_STS
AG_DTV_VOUTENB
AG_SW_OFF_DET
TO 6, 11/12
STB_RST
to H-PCB
CONNECTOR
TP8501
TO 2, 9/12
MVDACO1
(DVB_CVBS)
TO 11/12
DIGITAL AUDIO
with AUDIO DESCRIPTION DATA
AH_DAUDIO
MAIN AUDIO DATA
AH_DMIX0
COMMON LR/SR CLK
AH_SRCK0
AH_LRCK0
for PHOTO OUT
AH_IECOUT0
TO 8/12
TO 1/12
TH-46PZ81FV
A-Board (4/12) Schematic Diagram
36
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