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ICS PHYceiver ICS1890 General Description Manual

10base-t/100base-tx integrated
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Summary of Contents for ICS PHYceiver ICS1890

  • Page 9 Status Progress Monitor Status Bits A-N Complete Bit 2 Bit 1 Bit 0 Idle Parallel Detected Parallel Detection Failure Ability Matched Acknowledge Match Failure Acknowledge Matched Consistency Match Failure Consistency Matched Auto-Negotiation Completed Successfully...
  • Page 11 4B Code 5B Code 4B Code 5B Code Symbol Meaning Symbol Meaning 3210 43210 3210 43210 Data 0 0000 11110 Data 8 1000 10010 Data 1 0001 01001 Data 9 1001 10011 Data 2 0010 10100 Data A 1010 10110 Data 3 0011 10101...
  • Page 13 Resistance (Ohm/m) v. Freq. (MHz)
  • Page 14 Cable Attenuation (dB) v. Freq. (MHz) typical worst case...
  • Page 19 Definition When bit=0 When bit=1 Access Default Reset no effect reset the PHY RW/SC Loopback disable loop back mode enable loop back mode Data Rate 10 Mb/s operation 100 Mb/s operation Auto-Negotiation Enable disable Auto-Negotiation enable Auto-Negotiation reduced power Power-Down normal mode consumption 0 if PHY...
  • Page 21 Definition When bit=0 When bit=1 Access Default 100Base-T4 always 0 TX full duplex not 100Base-TX Full Duplex TX full duplex supported supported TX half duplex not 100Base-TX Half Duplex TX half duplex supported supported 10 full duplex not 10Base-T Full Duplex 10 full duplex supported supported 10 half duplex not...
  • Page 23 Definition When bit=0 When bit=1 Access Default OUI bit 3 | c OUI bit 4 | d OUI bit 5 | e OUI bit 6 | f OUI bit 7 | g OUI bit 8 | h OUI bit 9 | I OUI bit 10 | j OUI bit 11 | k OUI bit 12 | l...
  • Page 24 Definition When bit=0 When bit=1 Access Default OUI bit 19 | s OUI bit 20 | t OUI bit 21 | u OUI bit 22 | v OUI bit 23 | w OUI bit 24 | x Manufacturer’s Model Number bit 5 Manufacturer’s Model Number bit 4 Manufacturer’s Model Number bit 3 Manufacturer’s Model Number bit 2...
  • Page 25 Definition When bit=0 When bit=1 Access Default always 0 - not capable of Next Page sending next pages Reserved by IEEE always 0 Fault Indication to link partner no fault a fault has occurred locally Technology Ability Field bit A7 reserved by IEEE Technology Ability Field bit A6 reserved by IEEE...
  • Page 27 Definition When bit=0 When bit=1 Access Default partner does not support partner supports next Next Page next page exchange page exchange Reserved by IEEE always 0 a fault has occurred at Remote Fault no fault the remote link partner Technology Ability Field reserved by IEEE bit A7 Technology Ability Field...
  • Page 28 Definition When bit=0 When bit=1 Access Default Reserved by IEEE always 0 Reserved by IEEE always 0 Reserved by IEEE always 0 Reserved by IEEE always 0 Reserved by IEEE always 0 Reserved by IEEE always 0 Reserved by IEEE always 0 Reserved by IEEE always 0...
  • Page 29 Access Default don’t allow writes to CW allow next write to effect Command Register Override bits both RW & CW bits Reserved for ICS Read unspecified RW /0 Reserved for ICS Read unspecified RW /0 Reserved for ICS Read unspecified...
  • Page 30 Definition When bit=0 When bit=1 Access Default Data Rate 10 Mb/s negotiated 100 Mb/s negotiated Duplex half duplex negotiated full duplex negotiated Auto-Negotiation Progress see decode table Monitor bit 2 Auto-Negotiation Progress see decode table Monitor bit 1 Auto-Negotiation Progress see decode table Monitor bit 0 Receive Signal Error...
  • Page 32 Definition When bit=0 When bit=1 Access Default Reserved for ICS Read unspecified must be wirtten as a 0 RW /0 Polarity Reversed polarity normal polarity reserved Reserved for ICS Read unspecified RW /0 Reserved for ICS Read unspecified RW /0...
  • Page 34 HW/S- Hardware/Software Priority Hardware Priority Software Priority Link Partner Supports unknown partner supports Remote Fault Remote Fault Reserved for ICS Read unspecified RW /0 Reserved for ICS Read unspecified RW /0 Transmitted Remote Fault RF bit in transmitted LCW=0 RF bit in transmitted LCW=1...
  • Page 36 Signal Meaning Signal Meaning TXCLK* Transmit Clock NOD/REP Node/Repeater Mode TXEN* Transmit Enable MII/SI MII Data/Stream Interface TXD3* Transmit Data 3 10/LP 10M Serial/Link Pulse Interface TXD2* Transmit Data 2 HW/SW Hardware/Software Priority TXD1* Transmit Data 1 10/100SEL 10/100 Select TXD0* Transmit Data 0 DPXSEL...
  • Page 43 Ω Ω...
  • Page 44 NOD/REP ITCLS Latching Clock REF_IN TXCLK TXCLK REF_IN...
  • Page 45 Ω Ω Ω...
  • Page 46 Digital Domain Transmit Domain Receive Domain 16 VDD 41 VDD 8 VDD 18 VDD 40 VSS 7VSS 17 VSS 54 VDD 56 VDD 25 VDD 51 VSS 55 VSS 29 VSS 57 VDD 63 VSS...
  • Page 47 PIN NAME TYPE Description NUMBER NOD/REP TTL-compatible Node/Repeater Mode 10/100SEL TTL-compatible 10/100 Select 10TCSR 10M Transmit Current Set Resistor 100TCSR 100M Transmit Current Set Resistor TP_TX Twisted Pair Transmit Data+ TP_TX- Twisted Pair Transmit Data- Ditigal Domain Power (Transmitter) TPTRI TTL-compatible Twisted Pair Tristate TP_RX+...
  • Page 48 PIN NAME TYPE DESCRIPTION NUMBER RXD2* TTL-compatible Receive Data 2 RXD1* TTL-compatible Receive Data 1 RXD0* TTL-compatible Receive Data 0 RXDV* TTL-compatible Receive Data Valid RXCLK* TTL-compatible Receive Clock RXER TTL-compatible Receive Error RXTRI TTL-compatible Receive MAC-PHY Interface Tristate Digital Domain Power TXER* TTL-compatible Transmit Error...
  • Page 50 PARAMETER SYMBOL TEST CONDITIONS UNITS Ambient Operating Temp. °C Power Supply +4.75 +5.25 PARAMETER UNITS Crystal Oscillator Frequency* Crystal Oscillator Frequency Tolerance Ω 10TCSR Resistor Value 2.61 Ω 100TCSR Resistor Value 6.49 6.81 7.50 Ω LED Resistor Value 1000 10,000...
  • Page 51 PARAMETER SYMBOL CONDITIONS UNITS IC Supply Current =5.25V PARAMETER SYMBOL CONDITIONS UNITS TTL Input High Voltage VDD=5V, VSS=0V TTL Input Low Voltage VDD=5V, VSS=0V TTL Output High Voltage VDD=5V, VSS=0V TTL Output Low Voltage VDD=5V, VSS=0V TTL Driving CMOS, Output High Voltage VDD=5V, VSS=0V 3.68 TTL Driving CMOS, Output Low Voltage...
  • Page 52 PARAMETER (condition) UNITS REF_IN Duty Cycle REF_IN Period...
  • Page 53 PARAMETER (condition) UNITS TXCLK Duty Cycle TXCLK Period (100Base-T/MII Interface) TXCLK Period (10Base-T/MII Interface) TXCLK Period (100Base-T/100M Stream Interface) TXCLK Period (10Base-T/10M Serial Interface) PARAMETER (condition) UNITS RXCLK Duty Cycle RXCLK Period (100Base-T/MII Interface) RXCLK Period (10Base-T/MII Interface) RXCLK Period (100Base-T/100M Stream Interface) RXCLK Period (10Base-T/10M Serial Interface) RXDV Asserted Nominal Clock to Recovered Clock Cycle Extension...
  • Page 54 PARAMETER (condition) UNITS TXD, TXEN, TXER Setup to TXCLK rise TXD, TXEN, TXER Hold after TXCLK rise PARAMETER (condition) UNITS RXD, RXDV, RXER Setup to RXCLK rise 10.0 RXD, RXDV, RXER Hold after RXCLK rise 10.0...
  • Page 55 PARAMETER (condition) UNITS MDC Minimum High Time MDC Minimum Low Time MDC Period MDC rise to MDIO valid MDIO Setup to MDC MDIO Hold after MDC Maximum allowable frequency (50pF Loading)
  • Page 56 PARAMETER (condition) UNITS TP_RX input to 10RD delay 16.5 bits (10M Serial Interface) PARAMETER (condition) UNITS 1st bit of /5/ on TP_RX to /5/ on RXD 19.5 bits (10M MII)
  • Page 57 PARAMETER (condition) UNITS 10TD in to TP_TX out delay bits (10M Serial Interface) PARAMETER (condition) UNITS TXD sampled to MDI Output of 1st bit bits (10M MII)
  • Page 58 PARAMETER (condition) UNITS TXEN sampled to MDI Output 1st bit of /J/ (MII IF)* bits TXD sampled to MDI Output of 1st bit (100M Stream IF) bits...
  • Page 59 PARAMETER (condition) UNITS TXEN sampled to CRS assert bits TXD sampled to CRS de-assert bits PARAMETER (condition) UNITS 1st bit of /J/ into TP_RX to /J/ on RXD (100M MII IF) 19BT bits 1st bit of /J/ into TP_RX to /J/ on RXD (100M Stream IF) 12.5 bits...
  • Page 60 PARAMETER (condition) UNITS 1st bit of /J/ into TP_RX to CRS assert* 124ns/13BT bits 1st bit of /J/ into TP_RX while transmitting data to bits COL assert (Half Duplex Mode)* First bit of /T/ into TP_RX to CRS de-assert** 130ns/13BT bits First bit of /T/ received into TP_RX to COL de- bits...
  • Page 61 PARAMETER (condition) UNITS VDD to 4.5V to Reset Complete µs PARAMETER (condition) UNITS RESET active to device isolation and initialization Minimum RESET pulse width RESET released to device ready...
  • Page 62 PARAMETER (condition) UNITS COL Heartbeat assertion delay from TXEN de-assertion 1210 (10Base-T Half Duplex) COL Heartbeat assertion duration (10Base-T Half Duplex) 1170 PARAMETER (condition) UNITS Jabber activation time (10Base-T Half Duplex) Jabber deactivation time (10Base-T Half Duplex)
  • Page 63 PARAMETER (condition) UNITS Normal Link Pulse Width (10Base-T) COL Heartbeat assertion duration (10Base-T Half Duplex) PARAMETER (condition) UNITS Clock/Data pulse width Clock pulse to Data pulse timing 55.5 62.5 69.5 µs Clock pulse to Clock pulse µs FLP Burst width FLP burst to FLP burst timing Number of Clock/Data pulses in a burst pulses...
  • Page 64 PARAMETER (condition) UNITS Ideal data recovery window Actual data recovery window Data recovery window truncation SD assert to data acquired...
  • Page 65 Ω Ω...
  • Page 66 LEAD COUNT (N) 64L TQFP MQFP BODY THICKNESS FOOTPRINT (BODY+) Nominal 3.20 DIMENSION NAME TOLERANCE TOLERANCE DIMENSIONS TQFP MQFP Full Package Height MAX. MAX. 1.60 3.00 Package Standoff MAX. MAX. 0.15 0.25 Package Thickness ±0.05 +0.10/-0.05 Tip-to-Tip Width BASIC ±0.25 16.0 17.20 Body Width...