GainSpan GS2011M Datasheet page 39

GS2011M Low Power WiFi Module Data Sheet
Table 7 GS2011Mxx Module Pin Signal Description (Continued)
Pins Name
GPIO13/
20
SPI1_CS_n_1
GPIO21/
21
CLK_RTC
GPIO20/
22
CLK_HS_RC
GPIO19/
23
CLK_HS_XTAL
24 GPIO10/PWM0
25 GPIO9/I2C_CLK VDDIO
26 GPIO8/I2C_DATA VDDIO
GPIO36/
27 SDIO_DAT0/
SPI0_DOUT
GPIO35/
28 SDIO_CLK/
SPI0_CLK
GPIO33/
29 SDIO_DAT3/
SPI0_CS_n_0
GPIO34/
30 SDIO_CMD/
SPI0_DIN
31 VIN_3V3
32 GND
33 EN_1V8
34 VDDIO
GS2011M-DS-001211, Release 0.9
Voltage Internal Bias after
Domain Hardware Reset
VDDIO Pull-down
VDDIO Pull-down
VDDIO Pull-down
VDDIO Pull-down
VDDIO Pull-down
Pull-down (see Note 4) 12
Pull-down (see Note 4) 12
VDDIO Pull-down (see Note 1) 4
VDDIO Pull-down (see Note 1) 4
VDDIO Pull-up (see Note 1)
VDDIO Pull-down (see Note 1) 4
VIN_3V3 Not Applicable
0V Not Applicable
Need to be driven
VDDIO
HIGH or LOW
VDDIO Not Applicable
Confidential
Drive Signal State
Strength
(mA)
Digital
4
Input/Output
Digital
4
Input/Output
Digital
4
Input/Output
Digital
4
Input/Output
Digital
4
Input/Output
Digital
Input/Output
Digital
Input/Output
Digital
Input/Output
Digital
Input/Output
Digital Input
4
Output
Digital
Input/Output
Analog port
Analog port
Digital Input
Analog port
Preliminary
Pin-out and Signal Description
GS2011Mxx Device Pin-out
Description
GPIO/ Serial Peripheral
Interface 1 Chip Select_1
(Active Low)
GPIO/Internal RTC Clock
Circuitry Test Point. This
pin is used for Code
Restore.
GPIO/Internal RTC Clock
Circuitry Test Point
GPIO/XTAL Clock
Circuitry Test Point
GPIO/XTAL Clock
Circuitry Test Point
GPIO/Inter-Integrated
Circuit Clock
GPIO/Inter-Integrated
Circuit Data
GPIO/SDIO Data Bit0/SPI0
Transmit Data Output to the
HOST
GPIO/SDIO Clock/SPI0
Clock Input from the HOST
GPIO/SDIO Data Bit
3/SPI0 Chip Select Input 0
from the HOST (Active
Low)
GPIO/SDIO Command
Input/SPI0 Receive Data
Input from HOST
Single Supply Port
Ground
Internal 1.8V regulator
enable port Active High
All I/O voltage domain (can
be tied to VIN_3V3 or tied
to HOST I/O supply)
39