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2- or 4-Channel 16-Bit Buffered ∆Σ Multi-Range ADC
Features
l
Delta-Sigma A/D Converter
— Linearity Error: 0.0015%FS
l
Buffered Bipolar/Unipolar Input Ranges
— 25 mV, 55 mV, 100 mV, 1 V, 2.5 V and 5 V
l
Chopper Stabilized Instrumentation Amplifier
l
On-Chip Charge Pump Drive Circuitry
l
Differential Multiplexer
l
Conversion Data FIFO
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Programmable/Auto Channel Sequencer
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2-Bit Output Latch
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Simple three-wire serial interface
— SPI™ and Microwire™ Compatible
— Schmitt Trigger on Serial Clock (SCLK)
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Output Settles in One Conversion Cycle
l
50/60 Hz ±3 Hz Simultaneous Rejection
l
Buffered V
with +5 V Input Capability
REF
l
System and Self-Calibration with R/W
Registers per Channel
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Single +5 V Analog Supply
+3.0 V or +5 V Digital Supply
l
Power Consumption: 5.5 mW
- 1.8 mW in 1 V, 2.5 V and 5 V input ranges
AIN1+
AIN1-
MUX
AIN2+
AIN2-
CS5523
Shown
AIN3+
AIN3-
AIN4+
AIN4-
NBV
CPD
Preliminary Product Information
Cirrus Logic, Inc.
Crystal Semiconductor Products Division
P.O. Box 17847, Austin, Texas 78760
(512) 445 7222 FAX: (512) 445 7581
http://www.crystal.com
VA+
AGND
X1
+
Programmable
X20
Gain
-
X1
Calibration
Latch
Memory
A0 A1
This document contains information for a new product.
Cirrus Logic reserves the right to modify this product without notice.
General Description
The 16-bit CS5521/23 are highly integrated ∆Σ A/D con-
verters which include an instrumentation amplifier, a PGA
(programmable gain amplifier), a multi-channel multiplexer,
digital filters, and self and system calibration circuitry.
The chips are designed to provide their own negative
supply which enables their on-chip instrumentation am-
plifiers to measure bipolar ground-referenced signals
less-than or equal to ±100 mV.
The digital filters provide programmable output update
rates of 1.88 Hz, 3.76 Hz, 7.51 Hz, 15 Hz, 30 Hz,
61.6 Hz, 84.5 Hz, and 101.1 Hz when operating from a
32 kHz crystal. The CS5521/23 are capable of producing
output update rates up to 303 Hz with a 100kHz clock.
The filters are designed to settle to full accuracy for the
selected output update rate within one conversion cycle.
When operated at word rates of 15 Hz or less, the digital
filters reject both 50 and 60 Hz line interference
simultaneously.
Low power, single conversion settling time, programma-
ble output rates, and the ability to handle negative input
signals make these single supply products ideal solu-
tions for isolated and non-isolated applications.
ORDERING INFORMATION
See page 33.
VREF+
VREF-
DGND
X1
Digital Filter
Differential
4th order
delta-sigma
modulator
Clock
Calibration µC
Gen.
XIN XOUT
Copyright © Cirrus Logic, Inc. 1999
(All Rights Reserved)
CS5521
CS5523
±
3 Hz
VD+
Calibration
CS
Register
SCLK
Control
Register
SDI
Output
SDO
Register
MAR '99
DS317PP2
1
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Summary of Contents for Crystal CS5521-AS
- Page 1 Programmable/Auto Channel Sequencer 61.6 Hz, 84.5 Hz, and 101.1 Hz when operating from a 2-Bit Output Latch 32 kHz crystal. The CS5521/23 are capable of producing Simple three-wire serial interface output update rates up to 303 Hz with a 100kHz clock.
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Page 2: Table Of Contents
CS5521 CS5523 TABLE OF CONTENTS CHARACTERISTICS/SPECIFICATIONS ............4 ANALOG CHARACTERISTICS..............4 RMS NOISE....................4 5 V DIGITAL CHARACTERISTICS ............. 6 3 V DIGITAL CHARACTERISTICS ............. 6 DYNAMIC CHARACTERISTICS ..............7 RECOMMENDED OPERATING CONDITIONS .......... 7 ABSOLUTE MAXIMUM RATINGS .............. 7 SWITCHING CHARACTERISTICS ............. - Page 3 CS5521 CS5523 TABLE OF FIGURES CS5521/23 Configured to use on-chip charge pump to supply NBV....10 Charge Pump Drive Circuit for VD+ = 3 V............11 Alternate NBV Circuits..................11 CS5521/23 Configured for ground-referenced Unipolar Signals......11 CS5521/23 Configured for Single Supply Bridge Measurement.
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Page 4: Characteristics/Specifications
CS5521 CS5523 CHARACTERISTICS/SPECIFICATIONS ANALOG CHARACTERISTICS = 25 °C; VA+, VD+ = 5 V ±5%; VREF+ = 2.5 V, VREF- = AGND, NBV = -2.1 V, FCLK =32.768 kHz, OWR (Output Word Rate) = 15.0 Hz, Bipolar Mode, Input Range = ±100 mV; See Notes 1 and 2.) Parameter Unit... - Page 5 CS5521 CS5523 ANALOG CHARACTERISTICS (Continued) Parameter Unit Analog Input Common Mode + Signal on AIN+ or AIN- Bipolar/Unipolar Mode NBV = -1.8 to -2.5 V Range = 25 mV, 55 mV, or 100 mV -0.150 0.950 Range = 1 V, 2.5 V, or 5 V NBV = AGND Range = 25 mV, 55 mV, or 100 mV 1.85...
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Page 6: 5 V Digital Characteristics
CS5521 CS5523 5 V DIGITAL CHARACTERISTICS = 25 °C; VA+, VD+ = 5 V ±5%; GND = 0; See Notes 2 and 12.) Parameter Symbol Unit High-Level Input Voltage All Pins Except XIN and SCLK 0.6 VD+ (VD+)-0.5 SCLK (VD+) - 0.45 Low-Level Input Voltage All Pins Except XIN and SCLK SCLK... -
Page 7: Dynamic Characteristics
CS5521 CS5523 DYNAMIC CHARACTERISTICS Parameter Symbol Ratio Unit Modulator Sampling Frequency XIN/4 Filter Settling Time to 1/2 LSB (Full Scale Step) RECOMMENDED OPERATING CONDITIONS (AGND, DGND = 0 V; See Note 14.) Parameter Symbol Unit DC Power Supplies Positive Digital 5.25 Positive Analog 4.75... -
Page 8: Switching Characteristics
20. Specified using 10% and 90% points on waveform of interest. Output loaded with 50 pF. 21. Oscillator start-up time varies with crystal parameters. This specification does not apply when using an external clock source. 22. Applicable when SCLK is continuously running. - Page 9 CS5521 CS5523 SCLK Continuous Running SCLK Timing (Not to Scale) MSB-1 SCLK SDI Write Timing (Not to Scale) MSB-1 SCLK SDO Read Timing (Not to Scale) DS317PP2...
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Page 10: General Description
CS5521 CS5523 GENERAL DESCRIPTION the CS5521/23 to measure negative voltages with respect to ground without the need for a negative The CS5521/23 are 16-bit converters which in- supply. clude a chopper-stabilized instrumentation amplifi- er, and an on-chip programmable gain amplifier. Theory of Operation They are optimized for measuring low-level unipo- The CS5521/23 A/D converters are designed to op-... -
Page 11: Charge Pump Drive Circuit For Vd+ = 3 V
CS5521 CS5523 Figure 4 illustrates the CS5521/23 connected to for the measurement of ratiometric bridge trans- measure ground referenced unipolar signals of a ducer outputs. Figure 5 illustrates the CS5521/23 positive polarity using the 1 V, 2.5 V, and 5 V rang- connected to measure the output of a ratiometric es on the converter. -
Page 12: System Initialization
CS5521 CS5523 10 Ω Analog 0.1 µF 0.1 µ F Supply XOUT 32.768 ~ 100kHz VREF+ VREF- Optional Clock AIN1+ Source CS5521 AIN1- Serial SCLK AGND Data AIN2+ Interface AIN2- DGND Figure 5. CS5521/23 Configured for Single Supply Bridge Measurement. System Initialization Serial Port Overview When power to the CS5521/23 are applied, the... -
Page 13: Serial Port Interface
CS5521 CS5523 instructs the converter to read from or write to a tor with slower rise and fall times to directly drive register(s), perform a conversion or a calibration, the pin. Additionally, SDO is capable of sinking or or perform a NULL command. If a command other sourcing up to 5 mA to directly drive an optoisola- than start calibration or NULL command is re- tor LED. - Page 14 CS5521 CS5523 Command Register D7(MSB) CSB1 CSB0 RSB2 RSB1 RSB0 NAME VALUE FUNCTION Command Bit, CB Must be logic 0 for these commands. See Table 2. Not Used, NU Must always be logic zero. D5-D4 Channel Select Bits, CSB1-CSB0 provide the address of one of the four physical CSB1-CSB0 channels.
- Page 15 CS5521 CS5523 SCLK Command Time Data Time 24 SCLKs 8 SCLKs Write Cycle SCLK Command Time 8 SCLKs Data Time 24 SCLKs Read Cycle SCLK XIN/OWR Command Time Clock Cycles 8 SCLKs 8 SCLKs Clear SDO Flag Data Time * td = XIN/OWR clock cycles for each conversion except the 24 SCLKs first conversion which will take XIN/OWR + 7 clock cycles Figure 6.
- Page 16 CS5521 CS5523 Channel-Setup Registers CSR (Channel-Setup Register) LC (Log. Channel) 1 LC 2 LC 1 LC 2 Bits <47:36> Bits <35:24> Bits <95:84> Bits <83:72> LC 3 LC 4 Bits <23:12> Bits <11:0> LC 7 LC 8 Bits <23:12> Bits <11:0> CS5521 CS5523 D23(MSB)
- Page 17 CS5521 CS5523 Configuration Register D23(MSB) CFS1 CFS0 PS/R NAME VALUE FUNCTION D23-D22 Not Used, NU R* Must always be logic 0. D21-D20 Chop Frequency Select, R 256 Hz Amplifier chop frequency. CFS1-CFS0 4,096 Hz Amplifier chop frequency. 16,384 Hz Amplifier chop frequency. 1,024 Hz Amplifier chop frequency.
- Page 18 CS5521 CS5523 the way to access the resulting data is determined rises and falls to indicate the availability of a new by the MC (multiple conversion), the LP (loop), conversion. To exit this conversion mode the user and the RC (read convert) bits in the configuration must provide ‘11111111’...
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Page 19: Calibration Protocol
CS5521 CS5523 tion register determine how many conversions are data FIFO and remain in this mode; this is accom- performed and hence must be initialized before this plished by providing SDI with ‘00000000’ during conversion mode is entered. Upon completion of the first 8 SCLKs and then giving 24xN more the conversions, SDO falls to indicate that the con- SCLKs to read the conversion data;... -
Page 20: Use Of Pointers In Command Byte
CS5521 CS5523 calibration cycle is complete SDO falls and the re- CSRs are programmed with the following physical sults are stored in either the gain or offset register channel order: 4, 1, 4, 2, 4, 3, 4, 1. for the physical channel being calibrated. Note that Example 1: The configuration register has the fol- if additional calibrations are performed on the same lowing bits as shown: DP2-DP0 = ‘101’, MC = 1,... -
Page 21: Analog Input
CS5521 CS5523 Example 2: The configuration register has the fol- nel 4 in this example). SDO falls after physical lowing bits as shown: DP2-DP0 = ‘101’, MC = 1, channel 4 is converted. To read the conversion, 32 LP = 0, RC = X. The command issued is SCLKs are then required. - Page 22 CS5521 CS5523 to AGND. The choice of the operating mode for the Signal) input on AIN+ and AIN- must stay between NBV voltage depends upon the input signal and its NBV and VA+. common mode voltage. The CS5521/23 can accommodate full scale ranges For the 25 mV, 55 mV, and 100 mV input ranges, the other than 25 mV, 55 mV, 100 mV, 1 V, 2.5 V and input signals to AIN+ and AIN- are amplified by the...
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Page 23: Charge Pump Drive
CS5521 CS5523 ∆-Σ Nominal ∆-Σ Max. Differential Output VREF Gain Factor Input Range 20X Amplifier Differential Input Max. Input ± 25 mV ± 0.5 V ± 0.75 V 2.5V 2.8 V ± 55 mV ± 1.1 V ± 1.65 V 2.5V 2.272727... -
Page 24: Voltage Reference
CS5521 CS5523 pacitors can be used with acceptable results. The 10 25 mV, 55 mV, and 100 mV Ranges µ F ensures very low ripple on NBV. Intrinsic safety requirements prohibit the use of electrolytic capac- C = 48 pF µ... -
Page 25: Self Calibration
CS5521 CS5523 negative (0 positive, 1 negative). The converter can in the 1.0 V, 2.5 V, and 5 V ranges, the inputs of the typically trim ±50 percent of the input span. The modulator are connected together and then routed to gain register spans from 0 to (4 - 2 ). -
Page 26: Self Calibration Of Offset (Low Ranges)
CS5521 CS5523 perform a system gain calibration. In either case, a system gain calibration is performed the follow- the calibration signals must be within the specified ing conditions must be met: 1) Full-scale input calibration limits for each specific calibration step must not saturate the 20X instrumentation amplifi- (refer to the System Calibration Specifications). -
Page 27: Calibration Tips
CS5521 CS5523 The converter’s input ranges were chosen to guar- Offset calibration register value (24-bit 2’s complement) antee gain calibration accuracy to 1 LSB when gain Gain calibration register value calibration is performed. This is useful when a user (24-bit integer) wants to manually scale the full scale range of the converter and maintain accuracy. -
Page 28: Analog Output Latch Pins
Figure 17. Filter Response ter clock for the chip. The chips are designed to (Normalized to Output Word Rate = 1) operate using a low-cost 32.768 kHz “tuning fork” type crystal. One lead of the crystal should be con- DS317PP2... -
Page 29: Power Consumption
CS5521 CS5523 The output conversion word is 24 bits, or three Power Consumption bytes long, as shown in Table 8. The first two bytes The CS5521/23 accommodate three power con- represent the data output MSB first. The last byte sumption modes: normal, standby, and sleep. Nor- contains three ones and a zero followed by the mal mode, the default mode, is entered after a Channel Indicator bits (CI1 and CI0), Oscillation... -
Page 30: Pcb Layout
CS5521 CS5523 lay period is required before returning to the Note: See the CDB5522 data sheet for suggested layout de- tails and Applications Note 18 for more detailed layout normal power mode. guidelines. Before layout, please call for our Free Schematic PCB Layout Review Service. -
Page 31: Pin Descriptions
XIN; XOUT - Crystal In; Crystal Out. A gate inside the chip is connected to these pins and can be used with a crystal to provide the master clock for the device. Alternatively, an external (CMOS compatible) clock can be supplied into the XIN pin to provide the master clock for the device. -
Page 32: Measurement And Reference Inputs
CS5521 CS5523 SDO - Serial Data Output. SDO is the serial data output. It will output a high impedance state if CS = 1. SCLK - Serial Clock Input. A clock signal on this pin determines the input/output rate of the data for the SDI/SDO pins respectively. -
Page 33: Specification Definitions
Model Number Linearity Error (Max) Temperature Range Package ±0.003% CS5521-AP -40°C to +85°C 20-pin 0.3" Skinny Plastic DIP ±0.003% CS5521-AS -40°C to +85°C 20-pin 0.2" Plastic SSOP ±0.003% CS5523-AP -40°C to +85°C 24-pin 0.3" Skinny Plastic DIP ±0.003% CS5523-AS -40°C to +85°C 24-pin 0.2"... -
Page 34: Package Descriptions
CS5521 CS5523 PACKAGE DESCRIPTIONS 20 PIN PLASTIC (PDIP) PACKAGE DRAWING SEATING ∝ PLANE TOP VIEW SIDE VIEW BOTTOM VIEW INCHES MILLIMETERS 0.155 0.180 3.94 4.57 0.020 0.040 0.51 1.02 0.015 0.022 0.38 0.56 0.050 0.065 1.27 1.65 0.008 0.015 0.20 0.38 0.960 1.040... - Page 35 CS5521 CS5523 24 PIN SKINNY (PDIP) PACKAGE DRAWING SEATING ∝ PLANE TOP VIEW SIDE VIEW BOTTOM VIEW INCHES MILLIMETERS 0.155 0.180 3.94 4.57 0.020 0.040 0.51 1.02 0.014 0.022 0.36 0.56 0.040 0.065 1.02 1.65 0.008 0.015 0.20 0.38 1.235 1.265 31.37 32.13...
- Page 36 CS5521 CS5523 20 PIN SSOP PACKAGE DRAWING END VIEW SEATING PLANE SIDE VIEW 1 2 3 TOP VIEW NOTE INCHES MILLIMETERS 0.084 2.13 0.002 0.010 0.05 0.25 0.064 0.074 1.62 1.88 0.009 0.015 0.22 0.38 0.272 0.295 6.90 7.50 0.291 0.323 7.40 8.20...
- Page 37 CS5521 CS5523 24 PIN SSOP PACKAGE DRAWING END VIEW SEATING PLANE SIDE VIEW 1 2 3 TOP VIEW NOTE INCHES MILLIMETERS 0.084 2.13 0.002 0.010 0.05 0.25 0.064 0.074 1.62 1.88 0.009 0.015 0.22 0.38 0.311 0.335 7.90 8.50 0.291 0.323 7.40 8.20...
- Page 38 Preliminary product information describes products which are in production, but for which full characterization data is not yet available. Advance product information describes products which are in development and subject to development changes. Cirrus Logic, Inc. has made best efforts to ensure that the information contained in this document is accurate and reliable.
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