Altium Sharp ARM720T_LH79520 Specification Sheet

Sharp soc with 32-bit risc processor

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Summary

Core Reference

CR0162 (v2.0) March 10, 2008

Altium Designer's ARM720T_LH79520 component is a 32-bit Wishbone-compatible RISC

processor.

Although placed in an Altium Designer-based FPGA project just like any other 32-bit

processor component, the ARM720T_LH79520 is essentially a Wishbone-compliant wrapper

that allows communication with, and use of, the discrete ARM720T processor encapsulated

within the Sharp Bluestreak LH79520 device. You can think of the wrapper as being the

'means' by which to facilitate use of external memory and peripheral devices – defined within an FPGA – with the discrete

processor.

The ARM720T_LH79520 wrapper can be used in FPGA designs targeting any physical FPGA device – you are not constrained

to a particular vendor or platform.

Features

•

3-stage pipelined RISC processor

•

4GByte address space

•

32-bit ARM instruction set

•

Wishbone I/O and memory ports for simplified peripheral connection

•

Full Viper-based software development tool chain – C compiler/assembler/source-level

debugger/profiler

•

C-code compatible with other Altium Designer 8-bit and 32-bit Wishbone-compliant

processors, for easy design migration.

For further information on ARM720T features, refer to the following documents, available from

www.arm.com:

•

ARM720T Technical Reference Manual

•

ARM7TDMI-S Technical Reference Manual

For further information on LH79520 features, refer to the following documents, available from www.sharpsma.com:

•

LH79520 Product Brief

•

LH79520 Data Sheet

•

LH79520 System-on-Chip User's Guide

Available Devices

From a schematic document, the ARM720T_LH79520 device can be found in the FPGA Processors integrated library (FPGA

Processors.IntLib), located in the \Library\Fpga folder of the installation.

From an OpenBus System document, the ARM720T_LH79520 component can be found in the Processor Wrappers region of

the OpenBus Palette panel.

CR0162 (v2.0) March 10, 2008

ARM720T_LH79520 – Sharp LH79520 SoC

with ARM720T 32-bit RISC Processor

This document provides information on Altium Designer's Wishbone wrapper support

for the discrete Sharp Bluestreak® LH79520 – a fully integrated 32-bit System-on-

Chip (SoC), based on an ARM720T 32-bit RISC processor core.

The ARM720T macrocell within the

physical LH79520 is built around an

ARM7TDMI-S core processor. This

processor is an implementation of the

ARM architecture v4T.

Code written for the ARM720T is

binary-compatible with other members

of the ARM7 family of processors. It is

also forward-compatible with ARM9,

ARM9E, and ARM10 processor

families.

Table of Contents

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Summary of Contents for Altium Sharp ARM720T_LH79520

Page 1 Summary Core Reference CR0162 (v2.0) March 10, 2008 Altium Designer's ARM720T_LH79520 component is a 32-bit Wishbone-compatible RISC processor. Although placed in an Altium Designer-based FPGA project just like any other 32-bit processor component, the ARM720T_LH79520 is essentially a Wishbone-compliant wrapper that allows communication with, and use of, the discrete ARM720T processor encapsulated within the Sharp Bluestreak LH79520 device.
Page 2 ARM720T_LH79520 – Sharp LH79520 SoC with ARM720T 32-bit RISC Processor RISC Processor Background RISC, or Reduced Instruction Set Computer, is a term that is conventionally used to describe a type of microprocessor architecture that employs a small but highly-optimized set of instructions, rather than the large set of more specialized instructions often found in other types of architectures.
Page 3 Improving and Extending Product Life-Cycles Fast time to market is usually synonymous with a weaker feature set – a traditional trade-off. With FPGA-based system designs you can have the best of both worlds. You can get your product to market quickly with a limited feature set, then follow-up with more extensive features over time, upgrading the product while it is already in the field.
Page 4 ARM720T_LH79520 – Sharp LH79520 SoC with ARM720T 32-bit RISC Processor Wishbone OpenBUS Processor Wrappers To normalize access to hardware and peripherals, each of the 32-bit processors supported in Altium Designer has a Wishbone OpenBUS-based FPGA core that 'wraps' around the processor. This enables peripherals defined in the FPGA to be used transparently with any type of processor.
Page 5: Architectural Overview
Architectural Overview Symbol Figure 1. Symbols used for the ARM720T_LH79520 in both schematic (left) and OpenBus System (right). As can be seen from the schematic symbol in Figure 1, the ARM720T_LH79520 wrapper that is placed in an FPGA design essentially has three interfaces. The Wishbone External Memory and Peripheral I/O interfaces are identical to those of all other 32-bit processors supported by Altium Designer.
Page 6: Pin Description
ARM720T_LH79520 – Sharp LH79520 SoC with ARM720T 32-bit RISC Processor Pin Description The following pin description is for the processor when used on the schematic. In an OpenBus System, although the same signals are present, the abstract nature of the system hides the pin-level Wishbone interfaces. The interface signals to the physical processor will be made available as sheet entries, associated with the parent sheet symbol used to reference the underlying OpenBus System.
Page 7 Name Type IO_STB_O IO_CYC_O IO_ACK_I IO_ADR_O IO_DAT_I IO_DAT_O IO_SEL_O IO_WE_O IO_CLK_O IO_RST_O PER_DATA PER_ADDR PER_WEB PER_WE PER_CS PER_OE CR0162 (v2.0) March 10, 2008 ARM720T_LH79520 – Sharp LH79520 SoC with ARM720T 32-bit RISC Processor Polarity/Bus size Description Peripheral I/O Interface Signals Strobe signal.
Page 8: Configuring The Processor
ARM720T_LH79520 – Sharp LH79520 SoC with ARM720T 32-bit RISC Processor Name Type PER_RESET ARM7_SYS_RESE PER_CLK ARM7_SYS_CLK PER_READY PER_INT Configuring the Processor The architecture of the ARM720T_LH79520 can be configured after placement on the schematic sheet, or OpenBus System document, using the Configure (32-bit Processors) dialog (Figure 2). Access to this dialog depends on the document in which you are working: •...
Page 9 Speed-critical (or latency-sensitive) parts of an application should also be placed in this memory space. The following memory sizes are available to choose from: • 1KB (256 x 32-bit Words) • 2KB (512 x 32-bit Words) • 4KB (1K x 32-bit Words) •...
Page 10: Defining The Memory Map
ARM720T_LH79520 – Sharp LH79520 SoC with ARM720T 32-bit RISC Processor Memory & I/O Management The ARM720T_LH79520 uses 32-bit address buses providing a 4GByte linear address space. All memory access is in 32-bit words, which creates a physical address bus of 30-bits. Memory space is broken into seven main areas, as illustrated in Figure 4.
Page 11 ARM720T_LH79520 – Sharp LH79520 SoC with ARM720T 32-bit RISC Processor Figure 5. Memory devices mapped into banks 0- 4 (cs0-cs4) of the ARM720T_LH79520's addressable External Static Memory. Figure 6. Peripheral devices mapped into bank 5 (cs5) of the ARM720T_LH79520's addressable External Static Memory. CR0162 (v2.0) March 10, 2008...
Page 12 ARM720T_LH79520 – Sharp LH79520 SoC with ARM720T 32-bit RISC Processor The adjacent flow chart shows the process that was followed to build this memory map in a schematic-based FPGA design. This flow chart is only a guide, during the course of development it is likely that you will jump back and forth through this process as you build up the design.
Page 13: Internal Memory
• cs0 (Bank 0) – 4000_0000h to 43FF_FFFFh • cs1 (Bank 1) – 4400_0000h to 47FF_FFFFh • cs2 (Bank 2) – 4800_0000h to 4BFF_FFFFh • cs3 (Bank 3) – 4C00_0000h to 4FFF_FFFFh • cs4 (Bank 4) – 5000_0000h to 53FF_FFFFh •...
Page 14: External Memory
ARM720T_LH79520 – Sharp LH79520 SoC with ARM720T 32-bit RISC Processor The size of the RAM can vary between 1KB and 16MB, dependent on the availability of embedded block RAM in the target FPGA device used. Memory size is configured in the Internal Processor Memory region of the Configure (32-bit Processors) dialog (see the section Configuring the Processor).
Page 15: Data Organization
clock signal (CLK_I), an acknowledge signal fails to appear from the addressed slave peripheral device, the wait request to the ARM720T is dropped, the processor times out normally and the current data transfer cycle is forcibly terminated. The ACK_O signal from a slave peripheral should not be used as a ‘long delay’ hand-shaking mechanism. Where such a mechanism needs to be implemented, either use polling or interrupts.
Page 16 ARM720T_LH79520 – Sharp LH79520 SoC with ARM720T 32-bit RISC Processor • for an unsigned read, the processor will pad-out the remaining 24 or 16 bits respectively with zeroes • for a byte load/store, the processor will sign-extend from bit 8 •...
Page 17: Hardware Description
Hardware Description For detailed information about the hardware and functionality of the ARM720T_LH79520 processor, including internal registers, refer to the following reference guide, available from the • ARM720T Technical Reference Manual Clocking The signal ARM7_SYS_CLK sent from the processor wrapper to the physical processor itself is simply the internally-routed CLK_I signal.
Page 18 ARM720T_LH79520 – Sharp LH79520 SoC with ARM720T 32-bit RISC Processor Wishbone Communications The following sections detail the standard handshaking that takes place when the processor communicates to a slave peripheral or memory device connected to the relevant Wishbone interface port. Both of the ARM720T_LH79520's Wishbone ports can be configured for 8-, 16- or 32-bit data transfer, depending on the width of the data bus supported by the connected slave device.
Page 19 Reading from a Slave Wishbone Memory Device Data is read by the host processor (Wishbone Master) from a Wishbone-compliant memory device or memory controller (Wishbone Slave) in accordance with the standard Wishbone data transfer handshaking protocol. This data transfer cycle can be summarized as follows: •...
Page 20 ARM720T_LH79520 – Sharp LH79520 SoC with ARM720T 32-bit RISC Processor Placing an ARM720T_LH79520 in an FPGA design How the ARM720T_LH79520 is placed and wired within an FPGA design depends on the method used to build that design. The main processor-based system can be defined purely on the schematic sheet, or it can be contained as a separate OpenBus System, which is then referenced from the top-level schematic.
Page 21 ARM720T_LH79520 – Sharp LH79520 SoC with ARM720T 32-bit RISC Processor Design Featuring an OpenBus System Figure 11 illustrates identical use of the ARM720T_LH79520 within a design where the main processor system has been defined as an OpenBus System. Peripherals (and memory) are connected to the processor through an Interconnect component. The OpenBus System environment is a much more abstract and intuitive place to create a design, where the interfaces are reduced to single ports and connection is made courtesy of single links.
Page 22 ARM720T_LH79520 – Sharp LH79520 SoC with ARM720T 32-bit RISC Processor Figure 12. Wiring the OpenBus System-based ARM720T_LH79520 to the physical pins of the FPGA device. For more information on the concepts and workings of the OpenBus System, refer to the article Processor-based FPGA design with the OpenBus Facilitating Communications The host computer is connected to the ARM720T_LH79520 using the IEEE 1149.1 (JTAG) standard interface.
Page 23 As the physical ARM720T processor does not reside within an FPGA, communications between the host computer and the ARM720T are carried out through the Hard Devices JTAG chain. This is a departure from the normal way of communicating with FPGA-based, debug-enabled devices, such as the 'soft' processors and virtual instruments, whereby communication is carried out through the Soft Devices JTAG chain, and in accordance with the Nexus 5001 standard.
Page 24: On-Chip Debugging
ARM720T_LH79520 – Sharp LH79520 SoC with ARM720T 32-bit RISC Processor • Download of the embedded code targeted to the discrete ARM720T device. Click on the LH79520 device in the Hard Devices chain to access the process flow required to download the embedded software to the processor, as illustrated below. Notice that the process flow consist of compilation and download only.
Page 25 Figure 16. Starting an embedded code debug session. The debug environment offers the full suite of tools you would expect to see in order to efficiently debug the embedded code. These features include: • Setting Breakpoints • Adding Watches • Stepping into and over at both the source (*.C) and instruction (*.asm) level •...
Page 26 ARM720T_LH79520 – Sharp LH79520 SoC with ARM720T 32-bit RISC Processor Figure 17. Workspace panels offering code-specific information and controls Figure 18. Workspace panels offering information specific to the parent processor. Full-feature debugging is of course enjoyed at the source code level – from within the source code file itself.
Page 27 Figure 19. Accessing debug features from the processor's instrument panel The Nexus Debugger button provides access to the associated debug panel (Figure 20), which in turn allows you to interrogate and to a lighter extent control, debugging of the processor and its embedded code, notably with respect to the registers and memory.
Page 28: Revision History
ARM720T_LH79520 – Sharp LH79520 SoC with ARM720T 32-bit RISC Processor Instruction Set The ARM7TDMI-S core processor – on which the ARM720T is based – is an implementation of the ARM architecture v4T. For an overview of the ARM instructions available for this processor, refer to the following documents, available from the website: •...

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