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Xembedded XVME-689-VR7 User Manual

Single-slot vmebus intel celeron m processor module
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XVME-689-VR7
Single-Slot VMEbus
®
Intel
Celeron™ M Processor Module
User Manual
© © © © 2008 X
Printed in the United States of America
™, INC.
EMBEDDED
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  • Page 1 XVME-689-VR7 Single-Slot VMEbus ® Intel Celeron™ M Processor Module User Manual © © © © 2008 X Printed in the United States of America ™, INC. EMBEDDED...
  • Page 2 This document is copyrighted by Xembedded, Incorporated (Xembedded) and shall not be reproduced or copied without expressed written authorization from Xembedded. The information contained within this document is subject to change without notice. Xembedded does not guarantee the accuracy of the information.
  • Page 3 RS232, USB, keyboard, mouse, etc.) must have metal housings and provide direct connection to the metal VME chassis. Connector ground drain wires are not adequate. Environmental Protection Statement This product has been manufactured to satisfy environmental protection requirements where possible. Many of the components used (structural parts, printed circuit boards, connectors, batteries, etc.) are capable of being recycled.

  • Page 5: Table Of Contents

    Table of Contents Table of Contents XVME-689-VR7........................... i Table of Contents ..........................v Table of Figures and Tables....................... vii Chapter 1 – Introduction ....................... 1-1 Module Features ..........................1-1 Architecture ........................... 1-2 Software Support ........................... 1-6 Operational Description ......................... 1-6 Environmental Specifications......................
  • Page 6 Table of Contents PCI Device Map – ..........................4-4 VME Interface ..........................4-5 Software-Selectable Byte-Swapping Hardware................4-7 Chapter 5 XVME 990-VR7 Rear Transition Module ............. 5-1 Connectors............................. 5-2 Serial ATA hard drive Interface ..................... 5-3 Appendix A SDRAM and Battery Installation ................. 1 Memory Type ...........................

  • Page 7: Table Of Contents

    Table of Contents Table of Figures and Tables Figure 1-1 XVME 689-VR7 Block Diagram ................1-6 Figure 3-1 Main Setup Menu....................3-2 Figure 3-2 Slave Interface Submenu..................3-26 Figure 4-1 Byte Ordering Schemes...................4-8 Figure 4-2 Address-Invariant Translation .................4-8 Figure 4-3 Maintaining Numeric Consistency................4-9 Figure 4-4 Maintaining Address Consistency................4-10 Table 1-1 Maximum Video Modes Supported ................1-3 Table 1-2 XVME 689-VR7 CPU configurations...............1-9...

  • Page 8: Chapter 1 - Introduction

    Introduction Chapter 1 – Introduction ® ® The XVME 689-VR7 VMEbus Intel Celeron M PC-compatible VMEbus processor module combines the high performance and ruggedized packaging of the VMEbus with the broad application software base of the IBM PC/AT standard. It integrates the latest processor and chipset technology. The XVME 689- VR7is the lowest power draw of any of our processors while maintaining a very high level of processing power.

  • Page 9: Architecture

    2GB of ECC DDR 266/333MHz SDRAM. Approved SDRAM suppliers are listed in 0. Flash BIOS The XVME 689-VR7 system BIOS is contained in a 1MB flash device to facilitate system BIOS updates. Contact Xembedded support for available updates at support@xembedded.com if needed. Be sure to record your current version number and the reason for the request.

  • Page 10: Table 1-1 Maximum Video Modes Supported

    Compact Flash site and the secondary IDE slave signals are not supported. The XVME-689-VR7 is NOT compatible with the XVME-977 and/or the XVME-979 mass storage modules. For applications that require mass storage outside the VMEbus chassis, the XVME 9090-VR7 rear transition module plugs onto the VMEbus J2 connector.
  • Page 11 Introduction Caution The IDE controller supports enhanced PIO modes, which reduce the cycle times for 16-bit data transfers to the hard drive. Check with your drive manual to see if the drive you are using supports these modes. The higher the PIO mode, the shorter the cycle time.
  • Page 12 This makes it easy to configure VMEbus resources in protected and real mode programs The XVME 689- VR7 also incorporates onboard hardware byte-swapping (see Table 1-2). For a complete API, the Xembedded Board Support Packages tailored to your operating system will allow quick programming of your application.

  • Page 13: Software Support

    The XVME 689-VR7 is fully PC-compatible and will run "off-the-shelf" PC software, but most packages will not be able to access the features of the VMEbus. To solve this problem, Xembedded has developed extensive Board Support Packages (BSPs) that simplify the integration of VMEbus data into PC software applications.

  • Page 14: Environmental Specifications

    Introduction Environmental Specifications The XVME 689-VR7 will meet the following environmental requirements: Environmental Specification Operating Non-Operating Thermal -40 to 85 C Humidity 10% to 90% RH, 10% to 90% RH, non- non-condensing condensing Shock 30 g peak 50 g peak acceleration, acceleration, 11 11 msec duration msec duration...

  • Page 15: Hardware Specifications

    Introduction Hardware Specifications Characteristic Specification Power Specifications: 5.4 A (typical); 10.5 A (maximum) Voltage Specifications: +5V, +12V, -12V; all +5%/-2.5% CPU speed: Intel Celeron M Low Power 1.8 GHz Processor L2 Cache: Intel Celeron M Low Power Processor 2 MB Onboard memory SDRAM, up to 2 GB (one 200-pin SODIMM) Integrated Graphics Controller...

  • Page 16: Vmebus Specification

    Introduction VMEbus Specification VMEbus Compliance Complies with VMEbus Specification ANSI/VITA 1–1994 A32/A24/A16:D64/D32/D16/D08(EO) DTB Master A32/A24/A16:D64/D32/D16/D08(EO) DTB Slave R(0-3) Bus Requester Interrupter I(1)-I(7) DYN IH(1)-IH(7) Interrupt Handler SYSCLK and SYSRESET Driver PRI, SGL, RRS Arbiter RWD, ROR bus release Form Factor: DOUBLE 233.7 mm x 160 mm (9.2" x 6.3") System Configuration and Expansion Options Tables Table 1-2 XVME 689-VR7 CPU configurations Ordering...

  • Page 17: Table 1-3 Xvme 689-Vr7 Expansion Module Options

    PMC Carrier module with two PMC module sites. The XVME-976- 209 allows for stacking of a second XVME-976-209, this combination will accommodate a total of five PMC modules XVME-977/011 Not Compatible with the XVME-689-VR7 XVME-979/1 Not Compatible with the XVME-689-VR7 XVME-979/2...

  • Page 18: Chapter 2 - Installation And Setup

    Installation and Setup Chapter 2 – Installation and Setup Board Layout This chapter provides information on configuring the XVME 689-VR7 modules. It also provides information on installing the XVME 689-VR7 into a backplane and enabling the Ethernet controller. Fig. 2-1 shows the jumper, switch, and connector locations on the XVME 689-VR7.

  • Page 19: 3Jumper Settings

    Installation and Setup Jumper Settings The following table Lists XVME689-VR7 jumpers, their default positions, and their functions. Table 2-1 XVME 689-VR7 Jumper Settings Jumper Position Function XVME 689-VR7 cannot generate SYSFAIL* B √ √ √ √ XVME 689-VR7 generates SYSFAIL* normally Disables system resources (no auto SYSCON) B √...

  • Page 20: Switch Settings

    No local reset Toggle switch causes local reset Registers The XVME 689-VR7 modules contain the following Xembedded-defined I/O registers: 218h, 219h, 233h, and 234h. Register 218h – Abort/CMOS Clear Register This register controls the abort toggle switch and allows you to read the CMOS clear jumper (main board J21).
  • Page 21 Installation and Setup Register 219h – Flash Control Register This register controls the following LEDs and signals. Table 2-4 LED/BIOS Register Settings LED/Signal Result FAULT 0 = Fault LED on 1 = Fault LED off PASS 0 = PASS LED off 1 = PASS LED on RESERVED Reserved...

  • Page 22: Front Panel Layout

    Installation and Setup Register 234h – Flash Paging and Byte Swap Register This register controls access to the Flash paging and byte-swapping functions. Table 2-6 Flash Paging and Byte Swap Register Settings Signal Result FLB_A15 Flash address 15 - page control bit FLB_A16 Flash address 16 - page control bit FLB_A17...

  • Page 23: Connectors

    Installation and Setup Connectors This section provides pin outs for the XVME 689-VR7 connectors. Refer to the EMC warning at the beginning of this manual before attaching cables. Keyboard/Mouse Port Connector (P7) Figure 2-7 Table 2-7 Keyboard Port Connector Pin out Signal Keyboard Data Mouse Data...
  • Page 24 Installation and Setup Front panel (P12), Rear Transition Module and Vita 31.1 Ethernet ____________________________________________________________ The Ethernet ports on the XVME 689-VR7 are switch able between the front and the rear of the XVME 689- VR7. When in the rear mode, the Ethernet ports can use the (optional, available at order time only) PO connector for either Vita 31.1 switch fabric over the Vita 31.1 compliant backplane or Ethernet out the XVME 990-VR7/2 rear transition module.
  • Page 25 Installation and Setup VGA Connector (P9) The video is BIOS selectable and is available on either the front panel on a standard SVGA connector or out the VMEbus P2. The table below shows the pin out of the standard video connector and also the VMEbus P2 pin out for the rear access of video.
  • Page 26 Installation and Setup USB Port Connector (J5) USB provides an expandable, hot-pluggable Plug and Play serial interface that ensures a standard, low-cost connection for peripheral devices. Devices suitable for USB range from simple input devices such as keyboards, mice, and joysticks, to advanced devices such as printers, scanners, storage devices, modems, and video conferencing cameras.

  • Page 27: Com1 And Com4 (J4) Pin Definitions

    Installation and Setup COM1 and COM4 (J4) Pin Definitions The XVME 689-VR7 has two serial ports out the front panel, Com 1 and Com 4, these two com ports use the RJ- 45 connector. Two more com ports are out the VMEbus P2 connector and when the XVME 990-VR7 rear transition module is in place com port 2 and 3 uses a DB-9 connector.
  • Page 28 Installation and Setup On-Board Hard Drive/Compact Flash Site (J17) A horizontal ZIF connector is used on the board. (Samtec part number ZF5-40-01-TM-WT.) The connector on the board has a reverse pin out because of the connector orientation relative to the hard drive.
  • Page 29 Installation and Setup VMEbus Connectors VMEbus P1 Connector Table 2-16 P1 Connector Pin out BBSY* BCLR* MCLK ACFAIL* BG0IN* RSVU1 BG0OUT* BG1IN* BG1OUT* BG2IN* RSVU2 MCTL BG2OUT* GAP* GA0* SYSCLK BG3IN* SYSFAIL* RESP* GA1* BG3OUT* BERR* DS1* BR0* SYSRESET* SDB14* DS0* BR1* LWORD*...

  • Page 30: Vmebus P2 Connector

    Installation and Setup VMEbus P2 Connector Row Z Row A Row B Row C Row D Number FD_DRV0 VGA_RED USB0- FD_INDX VGA_GREEN USB0+ FD_DCHG FD_DIR VGA_BLUE VME_RETRY USB1- FD_MTR0 VGA_HSYN USB1+ FD_STEP FD_WGAT VGA_VSYN FD_WDAT AUD_LINE_IN_L FD_TRK0 FD_RDAT AUD_LINE_IN_R FD_WPRT AUD_LINE_OUT_L FD_HDSL LPT1_AFED...
  • Page 31 Installation and Setup VMEbus P0 Connector IDE_PDDACK# PMC I/O 32 IDE_PDDREQ PMC I/O 17 PMC I/O 1 PMC I/O 18 PMC I/O 2 IDE_PDDCS1# PMC I/O 19 PMC I/O 3 IDE_PDDA0 PMC I/O 33 PMC I/O 4 IDE_PDDA1 PMC I/O 20 PMC I/O 5 IDE_IRQ14 PMC I/O 34...
  • Page 32 Installation and Setup 80pin PCI connector (P3) The P3, high speed micro-strip connector has all the PCI signals along with 2 separate PCI clocks and the 2 request and grants predefined. The CPU board and the Interface boards will be keyed for either 3.3V or 5V signaling. The keying mechanism is based on standoffs.
  • Page 33 Installation and Setup PMC Host Connectors PMC Host Connector 1 Table 2-19 XVME 689-VR7 Daughterboard PMC Host Connector 1 Pin out Signal Signal FRAME* -12V INTA* IRDY* INTB* DEVSEL* INTC* BUSMODE1* PLOCK* INTD* SDONE PCI-RSVD14B SBO* PCI-RSVD14A PCICLK V_I/O AD(15) AD(12) GNT* AD(11)

  • Page 34: Table 2-202 Xvme 689-Vr7 Pmc Host Connector 2 Pin Out

    Installation and Setup PMC Host Connector 2 Table 2-202 XVME 689-VR7 PMC Host Connector 2 Pin out Signal Signal +12V TRST* PMC-RSVD_PN2-34 TRDY* +3.3V STOP* PERR* PCI-RSVD9A PCI-RSVD10B +3.3V PCI-RSVD11A SERR* BUSMODE2* (V_IO) C_BE*(1) +3.3V RST* AD(14) BUSMODE3* (GND) AD(13) +3.3V BUSMODE4* (GND) AD(10)

  • Page 35: Installing The Xvme 689-Vr7 Into A Backplane

    This section provides the information necessary to install the XVME 689-VR7 into the VMEbus backplane. The XVME 689-VR7 is a double-high, single-slot VMEbus module. Note Xembedded modules are designed to comply with all physical and electrical VMEbus backplane specifications of VME64x. Note The XVME 689-VR7 is available from the factory in two basic configurations, with P0 and without P0.
  • Page 36 Installation and Setup 8. Turn on power to the VMEbus card cage. Table 2-22 Front Panel Connector Labels Connector Label Keyboard/Mouse KEYBD/ MOUSE Display cable USB cable Ethernet cable 10/100/1000T Serial devices COM 1, COM 3 Parallel device LPT1 PMC card Note The floppy drive and hard drive are either cabled across P2 to an XVME-977 or an XVME-979 mass storage module, or they are connected to the XVME 990-...

  • Page 37: Enabling The Pci Ethernet Controller

    Installation and Setup Enabling the PCI Ethernet Controller Loading the Ethernet Driver To enable the Ethernet controller, you must load the applicable Ethernet driver for your operating system from the Documentation and Support Library CD included with the XVME 689-VR7. For best results, always use the supplied drivers. Ethernet RJ-45 10/100/1000 BaseT Connector (P12) Table 2-23 RJ-45 10/100/1000 BaseT Connector Pin out Signal...

  • Page 38: Chapter 3 Bios Setup Menus

    BIOS Setup Menus Chapter 3 BIOS Setup Menus The XVME 689-VR7 customized BIOS is designed to surpass the functionality provided for normal PCs. The custom BIOS allows access to the value-added features on the XVME 689-VR7. Some of the on- board features of the XVME 689-VR7 can also be setup via on-board jumpers, most of the time if a feature can be setup either way, the jumper takes priority over the BIOS settings.

  • Page 39: Main Setup Menu

    BIOS Setup Menus and select “Save Settings and Restart”. This causes the settings to be stored in nonvolatile memory in the system, and the system will reboot so that POST can configure itself with the new settings. After rebooting it may be desirable to reenter the Setup system as necessary to adjust settings as necessary.
  • Page 40 BIOS Setup Menus BIOS Version Indicates the major and minor core architecture versions (6.x, where x is a number from 0 to 999.) BIOS Build Date Date in MM/DD/YY format on which the OEM built the system BIOS binary file. System BIOS Size Size of BIOS exposed in low memory below the 1MB boundary.

  • Page 41: Exit Menu

    BIOS Setup Menus 3.2 Exit Menu The Exit menu provides methods for saving changes made in other menus, discarding changes, or reloading the standard system settings. This menu is shown in Figure 3.2 below. System Configuration Utility Main Exit Boot Post Features Firmbase...

  • Page 42: System Boot Menu

    BIOS Setup Menus 3.3 System Boot Menu The Boot menu allows the system’s boot actions and boot devices to be configured. This menu is shown in Figure 3.3. System Configuration Utility Main Exit Boot Post Features Firmbase Misc> System Boot Configuration Select Initialization And boot priority for All devices.
  • Page 43 BIOS Setup Menus This list can also contain other boot actions, as boot from network ports. When deciding what boot action to do first and then next in succession, POST first scans all the drives in the list to verify they are present and operating properly (as described earlier in this section) and then goes down the list and tries to perform the actions in order.
  • Page 44 BIOS Setup Menus This is the order in which the BIOS Boot Device Prioritization (BBS) will look for the Operating System. 0 [Fixed USB 0] Place the device to which you want to 1 [IDE 0/Pri Master] Boot at the top on the list. The device 2 [Floppy 0] 3 [None] Names are loaded by the...
  • Page 45 BIOS Setup Menus IDE 3 Mode [Fastest support mode] PIO-Mode, MULTI-Word-DMA- Mode, UDMA_Mode (40- Conductor Cable), UDMA_Mode (80-Conductor Cable), Fastest-Supported Mode Embedded BIOS® 2000 V6.0.5 – Copyright 2006 General Software, Inc. In addition to the boot device list, there are two more sections in the BOOT menu; namely, the Floppy Drive Configuration and IDE Drive Configuration sections.

  • Page 46: Post Memory Tests

    BIOS Setup Menus 3.4 POST Memory Tests The POST menu is used to configure POST. This menu is shown in Figure 3.4 (scrolled down more so the full set of options can be seen.). System Configuration Utility Main Exit Boot Post Features Firmbase...
  • Page 47 BIOS Setup Menus Low Memory Standard Test Enable basic memory confidence test, of memory below 1MB address boundary (conventional memory, or memory normally used by DOS.) Low Memory Exhaustive Test Enable exhaustive memory confidence test of memory below 1MB address boundary. High Memory Standard Test Enable basic memory confidence test, of memory between 1MB and 4.2GB address boundaries...
  • Page 48 BIOS Setup Menus POST Fast Reboot Cycle Enable early reboot in POST, allowing service technician to verify that the hardware can reboot very quickly many times in succession. Platform will continue to reboot after every boot until the system’s CMOS is reset, as there is no way to enter Setup from this early point during POST.

  • Page 49: Plug And Play Configuration Menu

    BIOS Setup Menus 3.5 Plug and Play Configuration Menu The PnP menu is used to configure Plug-n-Play, a legacy BIOS initiative used to support operating systems such as Windows95, Windows98, and WindowsNT. ACPI has largely replaced this feature; however, it is necessary for platforms to support older operating systems. Figure 3.5 shows the PnP Setup menu.
  • Page 50 BIOS Setup Menus System Configuration Utility Main Exit Boot Post Features Firmbase Misc> Plug-n-Play (PnP) Configuration Enable Plug-n-Play 1.0A specification Support. Plug-n-Play [Enabled] Plug-n-Play OS [Enabled] IRQs Reserved for Plug-n-Play IRQ 0 [Disabled] IRQ 1 [Disabled] IRQ 2 [Disabled] IRQ 3 [Enabled] IRQ 4 [Enabled]...
  • Page 51 BIOS Setup Menus The PnP menu consists of two sections; basic configuration that enables Plug-n-Play and identifies if a PnP should perform configuration or let the OS do it; and then, another section that defines which system IRQs should be reserved for PnP’s use, so that PCI doesn’t use them. The following table presents the fields in the PnP menu.

  • Page 52: Bios Super I/O Configuration Menu

    BIOS Setup Menus 3.6 BIOS Super I/O Configuration Menu The SIO menu is used to configure Super I/O components on the XVME 689-VR7/689. These components commonly are serial and parallel port controllers to floppy disk and keyboard controllers. The I/O, DMA, and IRQ assignments of each peripheral are configurable, so these values are also brought out to the SIO Setup menu.
  • Page 53 BIOS Setup Menus especially early DOS programs that do not use BIOS to access the COM ports. Keyboard Enable PC/AT or PS/2 keyboard controller. Mouse Enable PC/AT or PS/2 mouse portion of keyboard controller. GPIO [device name] Enable GPIO device. ACPI [device name] Enable ACPI device.
  • Page 54 BIOS Setup Menus 3.7 BIOS Super I/O Configuration Menu The Features menu is used to configure the system BIOS’ major features, including Quick Boot, APM, ACPI, PMM, SMBUS, SMBIOS, Manufacturing Mode, Splash Screen, Console Redirection, and others added by the OEM. Figure 3.7 shows a typical Setup. System Configuration Utility Main Exit...
  • Page 55 BIOS Setup Menus ACPI Enable ACPI system description and power management (ACPI replaces PnP and APM.) Used with ACPI-aware OSes such as Linux kernels version 2.6 and above, Windows XP, and Windows Vista. Commonly also uses the SMM feature (see Firmbase) to operate properly.

  • Page 56: Firmbase® Technology Configuration

    BIOS Setup Menus 3.8 Firmbase® Technology Configuration This menu is highly configurable by the OEM who may elect to eliminate some of the Firmbase Technology tuning parameters in more fixed-function devices. To illustrate what all of the standard Firmbase Technology configuration parameters are. System Configuration Utility Main Exit...

  • Page 57: Misc. Menu

    BIOS Setup Menus Enable this option in order for USB devices to be supported in the BBS device list (see the BOOT menu.) EHCI/USB 2.0 Enables EHCI Firmbase Technology driver, allowing USB Boot feature to use high speed transfers on USB 2.0 ports in the system. Firmbase Disk I/O Enables Firmbase Technology FAT file system driver, so that Firmbase applications such as Boot...
  • Page 58 BIOS Setup Menus System Configuration Utility Main Exit Boot Post Features Firmbase Misc> Cache Control CPU Cache [Enabled] System Cache [Enabled] Keyboard Control Keyboard Numlock LED [Disabled] Typematic Rate [30/sec] Typematic Delay [250ms] Miscellaneous BIOS Configuration Lowercase Hex Displays [Disabled] Embedded BIOS®...
  • Page 59 BIOS Setup Menus uppercase letters (ie, 2f8ah instead of 2F8AH.) Proprietary Stimulation Enables System Monitor’s callout to the OEM’s BPM adaptation code to execute code that causes stimulation of the SMM environment for measurement purposes. Hard Disk Read Stimulation Enables System Monitor’s read of a preconfigured number of sectors from a location on the first hard disk in the system in order to stimulate the SMM environment.
  • Page 60 BIOS Setup Menus drive. Please note that when this parameter is selected, the system automatically enables reading, so that the stimulation of the system includes reading a range of sectors into a memory buffer, and writing the same data back to the same range of sectors for safety.

  • Page 61: Vmebus Master

    BIOS Setup Menus 3.10 VMEbus Master System Controller Submenu The XVME 689-VR7 automatically provides slot 1 system resource functions. The system resource functions are explained in the Universe manual. (Contact Tundra at www.tundra.com for a PDF version of the Universe manual.) This function can be disabled using XVME 689-VR7 jumper J3.
  • Page 62 BIOS Setup Menus Option Description System Resources This read-only field displays the status (Enabled or Disabled) of the XVME-661 system resources. This value is automatically detected. µ µ µ BERR Timeout* This field is used to set the VMEbus error timeout. Choices are 16 s, 32 s, 64 µ...

  • Page 63: Figure 3-2 Slave Interface Submenu

    BIOS Setup Menus 3.11 VMEbus Slave Configuration The VMEbus slave setup allows configuration of the XVME processor board's VMEbus slave interfaces. Note When the Slave 1 & 2 Operational Mode setting is Compatible, slave images 0 and 1 are reserved for BIOS use. See p. Error! Bookmark not defined.

  • Page 64: Table 3-1 Slave Interface Submenu

    BIOS Setup Menus Table 3-1 Slave Interface Submenu Option Description Slave Interface Used to turn the slave interface boot state On or Off (default). When turned Off, other VME masters cannot access memory on the XVME 689-VR7. Address Modifiers Determines which type of VMEbus slave access is permitted to read or write to the XVME 689-VR7 dual-access memory.

  • Page 65: Front Panel Resources Control

    BIOS Setup Menus 3.12 Front Panel resources control Use this menu to select front panel or rear transition module I/O for the Video and the two Ethernet ports. System Configuration Utility <Features Misc VME_Master VME_Slave FrontPanelConfig Front Panel Config Video routed to front VGA Port or rear.

  • Page 66: Chapter 4 Programming

    **The PCI devices are located at the very top of memory just below the system BIOS. I/O Map This Preliminary I/O map for the XVME 689-VR7 contains I/O ports of the IBM AT architecture plus some additions for PCI I/O registers and Xembedded specific I/O registers. Hex Range...
  • Page 67 Programming 0C0-0DF DMA controller 2, 8237A-5 equivalent (note 3) 0F2-0FF 170-177 Secondary IDE Controller (Generates CS1*) 1F0-1F7 Primary IDE Controller (Generates CS1*) Xembedded LED control register Byte Swap port 235-277 Available 278-27F Parallel Port 2 (note 1) 280-2F7 Available 2F8-2FF...

  • Page 68: Irq Map

    Programming IRQ Map Table 4-2 IRQ Map INT# Function IRQ0 System Timer IRQ1 Keyboard IRQ2 Interrupt Cascade (reserved) IRQ3 COM2 IRQ4 COM1 IRQ5 Ethernet 1 IRQ5 PCI Expansion to PMC 2 IRQ6 Floppy IRQ7 Parallel Port (LPT1) IRQ8 Real Time Clock IRQ9 Universe IID IRQ9...

  • Page 69: Pci Device Map

    Programming PCI Device Map – Table 4-3 PCI device Map INT# Devic Device DWORD A B C D Line 82546GB 1079 Ethernet Controller PCI-X 8000 8000 PX_IRQ#0 AD(20) (Ethernet1) 8086 Function 0 R/G 0 82546GB 1079 Ethernet Controller PCI-X 8000 8000 PX_IRQ#1 AD(20) (Ethernet2)

  • Page 70: Vme Interface

    Programming VME Interface The VME interface is the Tundra Universe IID chip, which is a PCI bus-to-VMEbus bridge device. The XVME 689-VR7 implements a 32-bit PCI bus and a 32/64-bit VMEbus interface. The Universe chip configuration registers are located in a 4 KB block of PCI memory space.
  • Page 71 Programming slave image. The address mode and type are also programmed on a VMEbus slave image basis. The VMEbus memory address location for the VMEbus slave cycle is specified by the Base and Bound address. The PCI address is calculated by adding the Base address to the Translation offset address. The XVME 689-VR7 DRAM memory is based on the PC/AT architecture and is not contiguous.

  • Page 72: Software-Selectable Byte-Swapping Hardware

    Programming Note: The 6300ESB allows multiple PCI bus Interrupts to be mapped to one AT-bus interrupt. Example: In the BIOS setup menu map the VMEbus IRQ(1) to PCI IRQ(11). VMEbus Interrupt Generation The XVME 689-VR7 can generate VMEbus interrupts on all 7 levels. There is a unique STATUS/ID associated with each level.

  • Page 73: Figure 4-1 Byte Ordering Schemes

    Programming Address INTEL MOTOROLA Low Byte High Byte High Byte Low Byte Figure 4-1 Byte Ordering Schemes Note The two architectures differ only in the way in which they store data into memory, not in the way in which they place data on the shared data bus. The XVME 689-VR7 contains a Universe chip that performs address-invariant translation between the PCI bus (Intel architecture) and the VMEbus (Motorola architecture), and byte-swapping hardware to reverse the Universe chip byte-lane swapping.

  • Page 74: Figure 4-3 Maintaining Numeric Consistency

    Programming Numeric Consistency Numeric consistency, or data consistency, refers to communications between the XVME 689-VR7 and the VMEbus in which the byte-ordering scheme described above is maintained during the transfer of a 16-bit or 32-bit quantity. Numeric consistency is achieved by setting the XVME 689-VR7 buffers to pass data straight through, which allows the Universe chip to perform address-invariant byte-lane swapping.

  • Page 75: Figure 4-4 Maintaining Address Consistency

    Programming Address Consistency Address consistency, or address coherency, refers to communications between the XVME 689-VR7 and the VMEbus in which both architectures' addresses are the same for each byte. In other words, the XVME 689-VR7 and the VMEbus memory images appear the same.

  • Page 76: Chapter 5 Xvme 990-Vr7 Rear Transition Module

    Rear Transition Module Chapter 5 XVME 990-VR7 Rear Transition Module The XVME 990-VR7 rear transition module is available in two configurations, a XVME 990-VR7/1 (without P0 connector and the User I/O connector) and a XVME 990-VR7/2 (with the P0 connector and the User I/O connector).

  • Page 77: Connectors

    Rear Transition Module Connectors This section describes the pin outs for each of the fifth teen connectors on the XVME 990-VR7/X. IDE1 Connector The P1 connector connects up to two EIDE hard drives. Power for the drives is not supplied by the XVME 990-VR7/X. Table 5-1 XVME 990-VR7 IDE1 Connector Pin out Signal Signal...

  • Page 78: Serial Ata Hard Drive Interface

    Rear Transition Module Caution The total cable length for EIDE drives must not exceed 12 inches. Also, if two drives are connected, they must be no more than six inches apart. Use the SATA drive interface if longer cabling is required. Serial ATA hard drive Interface The use of the XVME 990-VR7 rear transition module, allows for connection to one or two SATA-150 drives...
  • Page 79 Rear Transition Module P2 Connector The XVME 990-VR7 P2 connector connects directly to the XVME 689-VR7 P2 connector through the VME chassis backplane. If the backplane used is NOT a 5- row/160-pin connector type of back plane, the outer rows of signals will not connect to the functions of the XVME 990-VR7 and therefore will not be available.
  • Page 80 Rear Transition Module P3 Interconnect connector The P3 connector on the XVME 990-VR7 is used to pass the P2 signals through to an adjacent XVME- 977 or XVME-979 drive card. It has the same pin out as rows A, B, and C of P2. The required interconnect 64-pin cable is included with the XVME-977 or XVME-979 modules.
  • Page 81 Rear Transition Module FDD1 Connector FDD1 connects a single 3.5" floppy drive. Only one drive is supported. Power for this external drive is not supplied by the XVME 990-VR7. Table 5-5 XVME 990-VR7 FDD1 Connector Pin out Signal Signal FDIRC* FRWC* FSTEP* KEY (NC)
  • Page 82 Rear Transition Module IDE1 Connector IDE1 connects up to two hard drives, primary master and slave. Power for the drives is not supplied by the XVME 990-VR7. Table 5-6 XVME 990-VR7 IDE1Connector Pin out Signal Signal HDRSTDRV* DIOW* DIOR* IORDY HDACK* HD10 IRQ14...
  • Page 83 Rear Transition Module The total cable length must not exceed 12 inches. Also, if two drives are connected, they must be no more than six inches apart. USB Port Connector USB provides an expandable, hot-pluggable Plug and Play serial interface that ensures a standard, low-cost connection for peripheral devices.
  • Page 84 Rear Transition Module P0 VMEbus connector This connector is used to distribute the on-board PMC rear I/O and the rear Ethernet ports (if Vita 31.1 is not in use). Table 5-9 showing pin out of the VMEbus P0. Row A Row B Row C Row D...
  • Page 85 Rear Transition Module USER_I/O Connector This is a 68-pin SCSI type connector that brings out the rear PMC site I/O from the XVME 689- VR7 PMC site to the P0 to the XVME 990-VR7, P0 to this USER_I/O. Table 5-10 Showing pin out of the User I/O connector. Pin Number Signal Name Pin Number...
  • Page 86 Rear Transition Module Ethernet RJ-45 Two Gigabyte Ethernet ports are available on the XVME 990-VR7. If the VMEbus has Vita 31.1 Capability, the rear Ethernet ports can not be used, they will conflict with the VMEbus switch fabric connections on the back plane. Fig.
  • Page 87 Rear Transition Module COM 2 Communications port 2 is a RS-232 serial communication port using a standard DB-9 connector. Figure 5-5 Com-2 DB-9 Table 5-12 Showing pin out of DB-9 to VMEbus P2 DB-9 Pin Location Signal Name VMEbus P2 Pin Location DCD2 Row a-12 RXD2...
  • Page 88 Rear Transition Module 25MIL_VIDA Row d Pin-31 LDDCDAT Row d Pin-26 HSYNC Row d Pin-23 VSYNC Row d Pin-24 LDDCCLK Row d Pin-25 LPT-1 The 26-pin header connector brings out the signals for the LPT or printer port. The use of a standard 26- pin ribbon cable to 25-pin D-Shell will be required to cable to a standard printer.
  • Page 89 Rear Transition Module Audio Input and Output The audio connects on the rear transition module are line level inputs and outputs. To drive a speaker, an amplifier will be needed. Table 5-15 Showing VMEbus P2 to Audio plugs. VMEbus P2 Pin Number Row a AUD_LINE_IN_L AUD_LINE_IN_R...

  • Page 90: Appendix A Sdram And Battery Installation

    The XVME 689-VR7 has one 200-pin DDR333 SDRAM memory module (SODIMM) site in which memory is inserted. The XVME 689-VR7 supports 256MB, 512MB, 1MB and 2MB of PC2700 SDRAM.. Table A-1 lists the SODIMM configurations. Table A-1 SDRAM SODIMM Configurations Xembedded Part Number Device Type and Size Vendor Vendor part number 200193...

  • Page 91: Module Battery Installation

    0 Appendix A SDRAM and Battery Installation 8. Gently push the SODIMM down until the metal clips snap into place to hold it. If you cannot gently push the SODIMM into position, you may need to redo step 7. 9. Replace the XVME 689-VR7 module, reconnect all connectors, etc. 10.

  • Page 92: Index

    Index Index Abort toggle switch........ 4-6 VGA..........2-8, 5-12 Abort/Clear CMOS register....2-3 VMEbus ...........2-12 backplane, installing XVME-689VR7 .. 2-18 XVME-973/1 BIOS menus P1 ...........5-2 Main menu......... 3-2 P3 ...........5-6 VMEbus menu P4 ...........5-7 Slave Interface submenus ..... 3-26 System Controller submenu ..3-24 fan power connector......2-17 block diagram ........
  • Page 93 Index PCM ..........1-5 memory map...........4-1 PMC ..........1-5 memory, SDRAM........1-9 short ISA..........1-5 P1 connector, XVME-973/1....5-2 Expansion Options ....... 1-10 P3 connector, XVME-973/1....5-6 Flash Paging and Byte Swap register . 2-5, 4- P4 connector, XVME-973/1....5-7 9, 4-10 parallel port ..........1-5 floppy drive ........
  • Page 94 Index registers VGA connector......2-8, 5-12 Abort/Clear CMOS ......2-3 VME interface ........4-5 Abort/Clear CMOS register ....2-3 VMEbus Flash Paging and Byte Swap2-5, 4-9, 4-10 compliance........1-9 LED/BIOS ......... 2-4 interface..........1-5 LED/BIOS register......2-4 interrrupt handling ......4-6 watchdog timer........2-4 interrupt generation ......4-7 reset options, VMEbus ......

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