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System Level Solutions USB20SR User Manual

Usb 2.0 device ip core
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System Level Solutions, Inc. (USA)
14100 Murphy Avenue
San Martin, CA 95046
(408) 852 - 0067
http://www.slscorp.com
USB 2.0 (USB20SR)
Device IP Core
User Guide
IP Core Version:
Document Version:
Document Date:
1.3
1.3
January 2013

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Summary of Contents for System Level Solutions USB20SR

  • Page 1 USB 2.0 (USB20SR) Device IP Core User Guide System Level Solutions, Inc. (USA) 14100 Murphy Avenue San Martin, CA 95046 IP Core Version: (408) 852 - 0067 Document Version: Document Date: January 2013 http://www.slscorp.com...
  • Page 2 Copyright©2013, System Level Solutions, Inc. (SLS) All rights reserved. SLS, an Embedded systems company, the styl- ized SLS logo, specific device designations, and all other words and logos that are identified as trademarks and/or service marks are, unless noted otherwise, the trademarks and service marks of SLS in India and other countries.

  • Page 3: About This Guide

    About this Guide Introduction This guide helps users to know about the basics of USB 2.0 (USB20SR), the software based enumeration device IP Core. Table below shows the revision history of this user guide. Version Date Description • January 2013 Added DCVERSION register •...

  • Page 4: How To Contact Sls

    For additional information about SLS products, consult the source shown below. Information Type E-mail Product literature services, SLS liter- support@slscorp.com ature services, Non-technical cus- tomer services, Technical support. System Level Solutions USB 2.0 (USB20SR) Device IP Core User Guide January 2013...

  • Page 5: Typographic Conventions

    The warning indicates information that should be read prior to starting or continuing the procedure or processes. The feet direct you to more information on a particular topic. System Level Solutions January 2013 USB 2.0 (USB20SR) Device IP Core User Guide...

  • Page 6: Table Of Contents

    On Chip RAM ............................6 Micro Controller/Processor Interface......................6 3. Operation ........................... 7 EndPoints ..............................8 Buffer Pointers ........................... 8 Data Organization ..........................8 Interrupts ..............................9 Timing..............................9 Software Interaction........................... 9 4. Core Registers......................... 11 DCVERSION............................14 FUNC_ADR............................15 System Level Solutions...
  • Page 7 Endpoint Registers ..........................28 EPn_CSR ..............................28 EPn_IMS ..............................31 EPn_BUF ..............................33 5. Core IOs ........................... 36 6. Using USB20SR IP in SOPC Builder ..................37 System Level Solutions January 2013 USB 2.0 (USB20SR) Device IP Core User Guide...

  • Page 8: Introduction

    1. Introduction The USB 2.0 Device IP Core (USB20SR) is a RAM based, 32-bit Avalon interface and ULPI interface support. The core supports both High Speed (480 Mbps) and Full Speed (12 Mbps) functionality. The core supports three endpoints Control, IN and OUT. Support of up to 15 endpoints can be added inside the IP Core as per customer request.

  • Page 9: Features

    Introduction refer to CoreCommander Reference Manual. Features Following are the USB20SR Device IP core features:  USB 2.0 USB IF high-speed certified  Supports both High Speed (480 Mbps) and Full Speed (12 Mbps)  High speed or Full speed operation selection through Software Low speed (1.5 Mbps) support also available on special request.

  • Page 10: Further Information

    Information support, refer readme.html located at <USB20SR Installation Path>\ usb20sr. <USB20SR Installation Path> is the installation directory. The default installation directory is c:\altera\<version #>\ip\sls. Where version no. is Quartus setup version.’...

  • Page 11: Core Architecture

    Each of the blocks is described in detail below: The Micro Controller/Processor interface provides a bridge between Host Interfaces (ex. Nios II Processor) and internal data memory and control registers. System Level Solutions January 2013 USB 2.0 (USB20SR) Device IP Core User Guide...

  • Page 12: Ulpi Phy

    ULPI Phy chip interface functionality with the HOST PC. The section below explains the steps to verify the ULPI PHY chip functionality with the host PC. Open the usb20sr_debug.v file located at <USB20SR Installation Path>\hardware\component\hdl. Disable the "‘define SR_ENABLE" line inside the file. Recompile your design.

  • Page 13: On Chip Ram

    Micro Controller/ This block provides a consistent core interface between the internal functions of the core and the function-specific host or micro controller. Processor Interface System Level Solutions January 2013 USB 2.0 (USB20SR) Device IP Core User Guide...

  • Page 14: Operation

    No software intervention is needed between endpoint access. Double buffer mechanism is used for reducing the latency requirement on the software, and increasing USB throughput. System Level Solutions January 2013 USB 2.0 (USB20SR) Device IP Core User Guide...

  • Page 15: Endpoints

    USB byte sequence. This USB core supports Little Endian byte ordering. System Level Solutions January 2013 USB 2.0 (USB20SR) Device IP Core User Guide...

  • Page 16: Interrupts

    If any of the bits 15 to 0 are set, the interrupt handler should also read the appropriate System Level Solutions USB 2.0 (USB20SR) Device IP Core User Guide January 2013...
  • Page 17 A care must be taken not to lose interrupt sources, as the main interrupt source register is cleared after interrupt source register read operation. System Level Solutions January 2013 USB 2.0 (USB20SR) Device IP Core User Guide...

  • Page 18: Core Registers

    4. Core Registers This section describes all the registers inside the USB20SR Core. The Register field describes the name of the register. The Offset field describes the offset of register in USB IP. The Access field describes the type of access to the register that is read or write.
  • Page 19 EndPoint 6 CSR Register EP6_IMS 0xA4 EndPoint 6 Interrupt Register EP6_BUFFER0 0xA8 EndPoint 6 Buffer0 Register EP6_BUFFER1 0xAc EndPoint 6 Buffer1 Register EP7_CSR 0xB0 EndPoint 7 CSR Register System Level Solutions January 2013 USB 2.0 (USB20SR) Device IP Core User Guide...
  • Page 20 EndPoint 12 Buffer1 Register EP13_CSR 0x110 EndPoint 13 CSR Register EP13_IMS 0x114 EndPoint 13 Interrupt Register EP13_BUFFER0 0x118 EndPoint 13 Buffer0 Register EP13_BUFFER1 0x11c EndPoint 13 Buffer1 Register System Level Solutions USB 2.0 (USB20SR) Device IP Core User Guide January 2013...

  • Page 21: Dcversion

    Table 4-2. DCVERSION Register Details Access Description 31:16 RO These bits represent the hexadecimal value of Product ID. (i.e. 0A04 for USB20SR) 15:8 These bits represent the hexadecimal value of IP Core Version. (i.e. 13 for IP Core Ver- sion 1.3)

  • Page 22: Func_Adr

    0: Disable interrupt generation due to USB reset UTMI RX Error Mask 1: Enable interrupt generation due to UTMI RX Error 0: Disable interrupt generation due to UTMI RX Error System Level Solutions USB 2.0 (USB20SR) Device IP Core User Guide January 2013...

  • Page 23: Int_Src

    Table 4-5 shows the interrupt source register description. Table 4-5. Interrupt Source (INT_SRC) Register Details Access Description 31:30 Reserved System Level Solutions January 2013 USB 2.0 (USB20SR) Device IP Core User Guide...
  • Page 24 1: Device is resumed 0: Device is not resumed System Level Solutions USB 2.0 (USB20SR) Device IP Core User Guide January 2013...
  • Page 25 Details of the endpoint interrupt event is given inside the endpoint interrupt register information. 1: Interrupt bit is set inside endpoint15. 0: Interrupt bit is not set inside endpoint15. System Level Solutions January 2013 USB 2.0 (USB20SR) Device IP Core User Guide...
  • Page 26 Details of the endpoint inter- rupt event is given inside endpoint interrupt register information. 1: Interrupt bit is set inside endpoint9. 0: Interrupt bit is not set inside endpoint9. System Level Solutions USB 2.0 (USB20SR) Device IP Core User Guide January 2013...
  • Page 27 Details of the endpoint interrupt event is given inside endpoint interrupt register information. 1: Interrupt bit is set inside endpoint3. 0: Interrupt bit is not set inside endpoint3. System Level Solutions January 2013 USB 2.0 (USB20SR) Device IP Core User Guide...

  • Page 28: Main_Csr

    MAIN_CSR This is the main configuration and status register of the core. This register provides current status of the device. Table 4-6 shows the Control/Status register description. System Level Solutions USB 2.0 (USB20SR) Device IP Core User Guide January 2013...
  • Page 29 Device sets this bit, when it is attached to the Host and Vbus is available from the Host PC Port. 1: Device is attached to the host. 0: Device is detached from the host. System Level Solutions January 2013 USB 2.0 (USB20SR) Device IP Core User Guide...

  • Page 30: Frm_Nat

    Number of frames with the same frame number (this field may be used to determine current microframe) Reserved 26:16 Frame number as received from SOF token 15:12 Reserved 11:0 Time since last SOF in 0.5 uS resolution Value after reset: 00000000h System Level Solutions USB 2.0 (USB20SR) Device IP Core User Guide January 2013...

  • Page 31: Test Mode

    Test_J_mode This bit is used to select Test-J mode for compliance test. 1: test mode is selected 0: test mode is not selected Value after Reset: 00h System Level Solutions January 2013 USB 2.0 (USB20SR) Device IP Core User Guide...

  • Page 32: Setup_Pack_1

    Processor can enable or disable the ULPI PHY Chip through this register as per the application requirement. Table 4-11 shows the ULPI PHY Chip Enable register description. System Level Solutions USB 2.0 (USB20SR) Device IP Core User Guide January 2013...

  • Page 33: Ulpi_Reg_Access

    PHY chip. Device clears this bit when it completes register write operation. 1: Reg write operation enable. 0: Reg write operation disable or completed System Level Solutions January 2013 USB 2.0 (USB20SR) Device IP Core User Guide...

  • Page 34: D_Speed_Sel

    0x01 should be written to the register and to disconnect the device from host 0x00 should be written to the register. Table 4-14 shows the Device Connect/ System Level Solutions USB 2.0 (USB20SR) Device IP Core User Guide January 2013...

  • Page 35: Endpoint Registers

    Detail description for usage of each bit of this register is given in table below. Table 4-15 shows the Endpoint CSR register description System Level Solutions January 2013 USB 2.0 (USB20SR) Device IP Core User Guide...
  • Page 36 Endpoint Type These two control bits are used by device to select the type of the endpoint. 00: Control Endpoint 01:IN EndPoint 10: OUT Endpoint 11: Reserved System Level Solutions USB 2.0 (USB20SR) Device IP Core User Guide January 2013...
  • Page 37 Device will discard all small packets received from host on its own and no information will be provided to host. Reserved Reserved Reserved System Level Solutions January 2013 USB 2.0 (USB20SR) Device IP Core User Guide...

  • Page 38: Epn_Ims

    0: Disable interrupt generation when buffer used bit of buffer registers is set. Unsupported PID Mask 1: Enable interrupt generation due to unsupported PIDerror 0: Disable interrupt generation due to unsupported PIDerror System Level Solutions USB 2.0 (USB20SR) Device IP Core User Guide January 2013...
  • Page 39 0: Operation is not completed on buffer 1 Note: Control endpoint uses single buffer communication for IN and OUT operation. Device sets buffer0 used bit when out operation is finished. System Level Solutions January 2013 USB 2.0 (USB20SR) Device IP Core User Guide...

  • Page 40: Epn_Buf

    The endpoint buffer register holds the buffer pointer for each endpoint. Each endpoint has two buffer registers, thus allowing double buffering as well as buffer start address inside the on chip buffer memory. Each buffer register has System Level Solutions USB 2.0 (USB20SR) Device IP Core User Guide January 2013...
  • Page 41 Note: The used bit inside the buffer registers of control endpoint is cleared when setup packet receive operation starts inside the IP core. System Level Solutions January 2013 USB 2.0 (USB20SR) Device IP Core User Guide...
  • Page 42 For control endpoint, buffer0 is used for OUT operation while buffer1 is used for IN endpoint. During IN endpoint operation, the buffer act as write only register while in OUT endpoint operation buffer act as read only register. System Level Solutions USB 2.0 (USB20SR) Device IP Core User Guide January 2013...

  • Page 43: Core Ios

    5. Core IOs Table 5-1 list all the IOs of the USB20SR IP core. Table 5-1. Core IOs Name Width Direction Description Data Bi-Di Bi-Direction Data Line for ULPI interface Direction line of ULPI interface. Use the Fast output register,...

  • Page 44: Using Usb20Sr Ip In Sopc Builder

    6. Using USB20SR IP in SOPC Builder To use USB20SR Device IP core in SOPC Builder follow the steps below: Running usb20sr_<licensetype>_v<version #>.exe will automatically place the USB20SR component into SOPC Builder GUI. You can see that USB20SR component is now added in the final view of the SOPC builder system.
  • Page 45 To generate complete reference design from scratch refer tutorial of design from scratch if you are new to SOPC builder tool. For further reference, refer Core Registers Section. System Level Solutions January 2013 USB 2.0 (USB20SR) Device IP Core User Guide...

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