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Dynamic Engineering PCI3IP-Minimap User Manual

Pci 3 slot ip compatible carrier 2kb address space
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DYNAMIC ENGINEERING
435 Park Dr., Ben Lomond, Calif. 95005
831-336-8891
Fax 831-336-3840
http://www.dyneng.com
sales@dyneng.com
Est. 1988
User Manual
PCI3IP-Minimap
PCI 3 Slot IP Compatible Carrier
2KB Address Space
Manual Revision A
Corresponding Hardware: Revision 3
Corresponding Firmware Revision A
10-1999-0403

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Summary of Contents for Dynamic Engineering PCI3IP-Minimap

  • Page 1 DYNAMIC ENGINEERING 435 Park Dr., Ben Lomond, Calif. 95005 831-336-8891 Fax 831-336-3840 http://www.dyneng.com sales@dyneng.com Est. 1988 User Manual PCI3IP-Minimap PCI 3 Slot IP Compatible Carrier 2KB Address Space Manual Revision A Corresponding Hardware: Revision 3 Corresponding Firmware Revision A 10-1999-0403...
  • Page 2 Dynamic Engineering has made every effort to ensure that this manual is accurate and complete. Still, the company reserves the right to make improvements or changes in the...

  • Page 3: Table Of Contents

    Table of Contents PRODUCT DESCRIPTION THEORY OF OPERATION ADDRESS MAP PROGRAMMING Register Definitions pci3ip_intreg0 pci3ip_intreg1 pci3ip_intreg2 APPLICATIONS GUIDE Interfacing Construction and Reliability Thermal Considerations WARRANTY AND REPAIR Service Policy Out of Warranty Repairs For Service Contact: SPECIFICATIONS ORDER INFORMATION Page Electronics Design •...
  • Page 4 List of Figures FIGURE 1 PCI3IPMM ADDRESS MAP FIGURE 2 PCI3IPMM CONTROL PORT FIGURE 3 PCI3IPMM INTERRUPT STATUS PORT FIGURE 4 PCI3IPMM USER SWITCH PORT FIGURE 5 PCI3IPMM CONNECTOR REFERENCE Page Electronics Design • Manufacturing Services...

  • Page 5: Product Description

    Product Description PCI3IPmm is part of the IP Compatible family of modular I/O components. The PCI3IPmm provides three IndustryPack Compatible sites in one PCI slot. ID, IO, INT, and MEM access types are supported for read and write cycles. All four spaces are limited to 128 bytes to provide a minimum address space for systems with limited memory.
  • Page 6 An 8 bit "dip switch" is provided on the PCI3IPmm. The switch configuration is readable via a register. The switch is for user-defined purposes. We envision the switch being used for software configuration control or test purposes. The reset switch provided can be used to reset the IP devices without affecting the PCI bus.

  • Page 7: Theory Of Operation

    As Dynamic Engineering adds features to the hardware we will update the PCI3IPmm page on the Dynamic Engineering website. If you want some of the new features, and have already purchased hardware, we will support you with a PROM update.
  • Page 8 The basic PCI identifying information will not change with the updates. The revision field will allow configuration control. Current revision is 0x01. Firmware Revision Table Initial Release Page Electronics Design • Manufacturing Services...

  • Page 9: Address Map

    Address Map Function Offset description // PCI relative addresses // #define pci3ip_intreg_0 0x00000000 base cntl reg #define pci3ip_intreg_1 0x00000004 interrupt request read back #define pci3ip_intreg_2 0x00000008 read back of switch // control register internal to Xilinx part. clock selection, interrupt enable and set, IPACK size // #define pci3ip_ida_st 0x00000200...

  • Page 10: Programming

    Once the initialization process has occurred and the system has assigned an address range to the PCI3IPmm card, the software will need to determine what the address space is. We refer to this address as base0 in our software. The next step is to initialize the PCI3IPmm. The main control register is written to for clock selection, and interrupt mask.

  • Page 11: Register Definitions

    Register Definitions pci3ip_intreg0 [$00 Main Control Register Port read/write] CONTROL REGISTER 0 DATA BIT DESCRIPTION Reset 1 = reset IPs 0 = normal spare LED5 1 = ON 0 = OFF LED4 LED3 LED2 LED1 LED0 spare spare Bus Error Int/Status Clear Bus Error Int En High Word Access C Increment Disable C...
  • Page 12 Spare means unused and unplanned RES means unused and planned for future enhancements INT FORCE will when set cause INTA on the PCI bus to be asserted. This bit can be useful for software debugging. Set this to simulate an IP interrupt when the hardware is not available.

  • Page 13: Pci3Ip_Intreg1

    software is checking to “see” what is installed or what address range is valid on an IP then the status can be polled to see if the IP responded. Bus Error Status/INT Clear when ‘1’ will clear the status bit and interrupt request (if enabled).

  • Page 14: Pci3Ip_Intreg2

    access to both INT0 and INT1 clearing addresses within the INT space. If the IP does not require a Vector fetch then proceed with IO or other accesses as necessary. The Bus Error status bit is set high when a Bus Error is handled by the internal watchdog timer circuit.

  • Page 15: Applications Guide

    Applications Guide Interfacing Some general interfacing guidelines are presented below. Do not hesitate to contact the factory if you need more assistance. Start-up Make sure that the "system" can see your hardware before trying to access it. Many BIOS will display the PCI devices found at boot up on a "splash screen"...
  • Page 16 and headers. The trace widths and density of parts required a 6-layer board. Through hole and surface mounting of components are used. IC sockets use gold plated screw machine pins. High insertion and removal forces are required, which assists in the retention of components. If the application requires unusually high reliability or is in an environment subject to high vibration, the user may solder the corner pins of each socketed IC into the socket, using a grounded soldering iron.

  • Page 17: Thermal Considerations

    Warranty and Repair Dynamic Engineering warrants this product to be free from defects in workmanship and materials under normal use and service and in its original, unmodified condition, for a period of one year from the time of purchase.

  • Page 18: Service Policy

    Include a return address and the telephone number of a technical contact. For out-of-warranty repairs, a purchase order for repair charges must accompany the return. Dynamic Engineering will not be responsible for damages due to improper packaging of returned items. For service on Dynamic Engineering Products not purchased directly from Dynamic Engineering contact your reseller.

  • Page 19: Specifications

    Specifications Logic Interfaces: IP Logic Interface, PCI Interface - 33 MHz, 32 bit Access types: IO, ID, MEM, INT IP Spaces supported via PCI bus accesses CLK rates supported: 8 MHz or 32 MHz slot by slot selectable 33 MHz PCI Software Interface: Control Registers, and Installed IP Initialization:...

  • Page 20: Order Information

    Locations for power and user circuits. HDRterm50 http://www.dyneng.com/HDRterm50.html 50 pin header to 50 screw terminal converter with DIN rail mounting. All information provided is Copyright Dynamic Engineering Page Electronics Design • Manufacturing...

  • Page 21: Figure 5 Pci3Ipmm Connector Reference

    FIGURE 5 PCI3IPMM CONNECTOR REFERENCE Pin 5 0 Pin 4 9 The PCI3IP has three slots (A,B,C) and three header connectors associated with those slots. The wiring is 1:1 from the IP IO connector to the PCI3IP header connector. The connectors are numbered to match standard ribbon cable as shown in the figure to the right.

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