Jennic JN5142 Datasheet

Ieee802.15.4 wireless microcontroller
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Overview
The JN5142 is an ultra low power, high performance wireless
microcontroller suitable for Remote Control, IEEE802.15.4 and Active RFID
applications. There is also a ROM variant that supports JenNet-IP Smart
Devices. The JN5142 features an enhanced 32-bit RISC processor offering
high coding efficiency through variable width instructions, a multi-stage
instruction pipeline and low power operation with programmable clock
speeds. It also includes a 2.4GHz IEEE802.15.4 compliant transceiver,
128KB of ROM, 32KB of RAM, and a comprehensive mix of analogue and
digital peripherals. The operating current is below 18mA, allowing operation
direct from a coin cell.
The peripherals support a wide range of applications. They include a 2-wire
serial interface, which operates as either master or slave, a two channel
ADC with battery and temperature sensors. A large switch matrix of up to 81
elements can be supported for remote control applications. The best in
class radio current and a 0.5µA sleep timer give excellent battery life.
Block Diagram
Voltage Supply
2.4GH
2.4GHz
z
Radio
Radio
XTAL
Power
Management
Benefits
Single chip optimized for
simple applications
Very low current solution for
long battery life – over 10 yrs
RF4CE in ROM
Variant for JenNet-IP Smart
Devices
Highly featured 32-bit RISC
CPU for high performance
and low power
System BOM is low in
component count and cost
Flexible sensor interfacing
options
© NXP Laboratories UK 2012
Data Sheet: JN5142
IEEE802.15.4 Wireless Microcontroller
Watchdog
Watchdog
RAM
ROM
Timer
Timer
32KB
128KB
Monitor
32-bit
RISC CPU
O-QPSK
Modem
29-byte
OTP eFuse
IEEE802.15.4
MAC
Accelerator
128-bit AES
Encryption
Accelerator
Applications
Robust and secure low power
wireless applications using
RF4CE
Remote Control
Toys and gaming peripherals
Active RFID tags
Point-to-point or star networks
using IEEE802.15.4
Energy harvesting, for example
self powered light switch
Smart Lighting Networks
Building Automation
JN-DS-JN5142 1v0
Features: Transceiver
2.4GHz IEEE802.15.4 compliant
128-bit AES security processor
MAC accelerator with packet
formatting, CRCs, address check,
auto-acks, timers
Integrated ultra low power sleep
oscillator – 0.5µA
2.0V to 3.6V battery operation
Deep sleep current 0.12µA
(Wake-up from IO)
0.5µA sleep with timer (1.5uA with
RAM held)
<$0.50 external component cost
Rx current 16.5mA
Tx current 14.8mA
Receiver sensitivity -95dBm
Transmit power 2.5dBm
SPI
Features: Microcontroller
2-Wire Serial
32-bit RISC CPU, 1 to 32MHz
(Master)
clock speed
Timer
Low power operation
UART
Variable instruction width for high
2-Wire Serial
(Slave)
coding efficiency
Sleep Counter
Multi-stage instruction pipeline
4-Chan 8-bit
128KB ROM and 32KB RAM for
ADC
bootloaded program code
Battery and ,
Temp Sensors
RF4CE or JenNet-IP software in
ROM
Master/Slave I2C interface.
3xPWM and Application
timer/counter
UART
SPI port with 3 selects
Supply Voltage Monitor with 8
programmable thresholds
2- to 4-input 8-bit ADC,
comparator
Battery and temperature sensors
Watchdog timer and Power-on-
Reset (with brown-out) circuit
Up to 18 DIO
Industrial temp -40°C to +125°C
6x6mm 40-lead Punched QFN
Lead-free and RoHS compliant
1

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Summary of Contents for Jennic JN5142

  • Page 1 Data Sheet: JN5142 IEEE802.15.4 Wireless Microcontroller Overview Features: Transceiver  2.4GHz IEEE802.15.4 compliant The JN5142 is an ultra low power, high performance wireless  128-bit AES security processor microcontroller suitable for Remote Control, IEEE802.15.4 and Active RFID  MAC accelerator with packet applications.
  • Page 2: Table Of Contents

    6.3 Software Reset 6.4 Supply Voltage Monitor (SVM) 6.5 Watchdog Timer 7 Interrupt System 7.1 System Calls 7.2 Processor Exceptions 7.2.1 Bus Error 7.2.2 Alignment 7.2.3 Illegal Instruction 7.2.4 Stack Overflow 7.3 Hardware Interrupts JN-DS-JN5142 1v0 © NXP Laboratories UK 2012...
  • Page 3 16 Random Number Generator 17 Analogue Peripherals 17.1 Analogue to Digital Converter 17.1.1 Operation 17.1.2 Supply Monitor 17.1.3 Temperature Sensor 17.2 Comparator 18 Power Management and Sleep Modes 18.1 Operating Modes 18.1.1 Power Domains © NXP Laboratories UK 2012 JN-DS-JN5142 1v0...
  • Page 4 B.1.1 Crystal Equivalent Circuit B.1.2 Crystal Load Capacitance B.1.3 Crystal ESR and Required Transconductance B.2 32MHz Oscillator B.3 32kHz Oscillator B.4 JN5142 Module Reference Designs B.4.1 Schematic Diagram B.4.2 PCB Design and Reflow Profile B.4.3 Moisture Sensitivity Level (MSL) JN-DS-JN5142 1v0...
  • Page 5 Related Documents RoHS Compliance Status Information Disclaimers Version Control Contact Details © NXP Laboratories UK 2012 JN-DS-JN5142 1v0...
  • Page 6: Introduction

    In view of the above, it is not necessary to provide the register details of the JN5142 in the datasheet. The device includes a Wireless Transceiver, RISC CPU, on chip memory and an extensive range of peripherals.
  • Page 7: Peripherals

     JTAG hardware debug port User applications access the peripherals using the Integrated Peripherals API. This allows applications to use a tested and easily understood view of the peripherals allowing rapid system development. © NXP Laboratories UK 2012 JN-DS-JN5142 1v0...
  • Page 8: Block Diagram

    32kHz 32KXTALIN Transceiver Clock 32KXTALOUT Security Processor Supply Monitor ADC1 VREF/ADC2 ADC3* ADC4* Digital Baseband Temperature Sensor RF_IN COMP1M* Radio VCOTUNE Comparator1 IBAIS COMP1P* *Multiplexed with DIO pins Figure 1: JN5142 Block Diagram JN-DS-JN5142 1v0 © NXP Laboratories UK 2012...
  • Page 9: Pin Configurations

    *Note: JTAG occupies UART0 pins in either position Figure 2: 40-pin QFN Configuration (top view)  Note: Please refer to Appendix B.4 JN5142 Module Reference Design for important applications information regarding the connection of the PADDLE to the PCB. © NXP Laboratories UK 2012...
  • Page 10: Pin Assignment

    DIO7, UART 0 Receive Data Input, JTAG Data Input or PWM 3 Output DIO8 TIM0CK_GT CMOS DIO8, Timer0 Clock/Gate Input or Pulse Counter1 Input DIO9 TIM0CAP 32KXTALIN CMOS DIO9, Timer0 Capture Input or 32K External Crystal Input JN-DS-JN5142 1v0 © NXP Laboratories UK 2012...
  • Page 11 The PCB schematic and layout rules detailed in Appendix B.4 must be followed. Failure to do so will likely result in the JN5142 failing to meet the performance specification detailed herein and worst case may result in device not functioning in the end application.
  • Page 12: Pin Descriptions

    The radio is a single ended design, requiring a capacitor and just two inductors to match to 50Ω microstrip line to the RF_IN pin. An external resistor (43kΩ) is required between IBIAS and analogue ground to set various bias currents and references within the radio. JN-DS-JN5142 1v0 © NXP Laboratories UK 2012...
  • Page 13: Analogue Peripherals

    2.2.6 Digital Input/Output Most digital I/O pins on the JN5142 can have signals applied up to 2V higher than VDD2 (with the exception of DIOs 0, 1, 9, 10, 15, 16 and 17, which are 3V tolerant) are therefore TTL-compatible with VDD2 > 3V. For other DC properties of these pins see Section 19.2.3.
  • Page 14 DIO pins retain both their input/output state and output level that was set as sleep commences. If the DIO pins were enabled as inputs and the interrupts were enabled then these pins may be used to wake up the JN5142 from sleep.
  • Page 15: Cpu

    GP registers to contain the address of objects. Subroutine parameter passing is also made more efficient by using GP registers rather than pushing objects onto the stack. The recommended programming method for the JN5142 is by using C, which is supported by a software developer kit comprising a C compiler, linker and debugger.
  • Page 16: Memory Organisation

    4 Memory Organisation This section describes the different memories found within the JN5142. The device contains ROM, RAM, OTP eFuse memory, the wireless transceiver and peripherals all within the same linear address space. 0xFFFFFFFF 0xF0008000 (32KB) 0xF0000000 Unpopulated RAM Echo...
  • Page 17: Ram

    4.2 RAM The JN5142 contains 32KBytes of high speed RAM. It can be used for both code and data storage and is accessed by the CPU in a single clock cycle. At reset, a boot loader controls the loading of segments of code and data from an external memory connected to the SPI port, into RAM.
  • Page 18: External Memory Encryption

    At reset, the contents of this memory are copied into RAM by the software boot loader. The Flash and EEPROM memory devices that are supported as standard through the JN5142 bootloader are given in Table 1. NXP recommends that where possible one of these devices should be selected.
  • Page 19: System Clocks

    5 System Clocks Two system clocks are used to provide timing references into the on-chip subsystems of the JN5142. A 16MHz clock, generated by a crystal-controlled 32MHz oscillator, is used by the transceiver, processor, memory and digital and analogue peripherals. A 32kHz clock is used by the sleep timer and is generated by one of two on-chip oscillators or can be supplied externally.
  • Page 20: High-Speed Rc Oscillator

    32kHz External Clock Upon a chip reset or power-up the JN5142 defaults to using the internal 32kHz RC Oscillator. If another clock source is selected then it will remain in use for all 32kHz timing until a chip reset is performed.
  • Page 21: 32Khz External Clock

    5.2.3 32kHz External Clock An externally supplied 32kHz reference clock on the 32KIN input (DIO9) may be provided to the JN5142. This would allow the 32kHz system clock to be sourced from a very stable external oscillator module, allowing more accurate sleep cycle timings compared to the internal RC oscillator.
  • Page 22: Reset

    A system reset initialises the device to a pre-defined state and forces the CPU to start program execution from the reset vector. The reset process that the JN5142 goes through is as follows. When power is first applied or when the external reset is released, the High-Speed RC oscillator and 32MHz crystal oscillator are activated.
  • Page 23: External Reset

    CPU doze mode. Dips in the supply voltage below a variable threshold can be detected and can be used to cause the JN5142 to perform a chip reset. Equally, dips in the supply voltage can be detected and used to cause an interrupt to the processor, when the voltage either drops below the threshold or rises above it.
  • Page 24: Watchdog Timer

    The watchdog runs continuously, even during doze, however the watchdog does not operate during sleep or deep sleep, or when the hardware debugger has taken control of the CPU. It will recommence automatically if enabled once the debugger un-stalls the CPU. JN-DS-JN5142 1v0 © NXP Laboratories UK 2012...
  • Page 25: Interrupt System

    7 Interrupt System The interrupt system on the JN5142 is a hardware-vectored interrupt system. The JN5142 provides several interrupt sources, some associated with CPU operations (CPU exceptions) and others which are used by hardware in the device. When an interrupt occurs, the CPU stops executing the current program and loads its program counter with a fixed hardware address specific to that interrupt.
  • Page 26: Hardware Interrupts

    [5]. For details of the interrupts generated from each peripheral see the respective section in this datasheet. Interrupts can be used to wake the JN5142 from sleep. The peripherals, baseband controller, security coprocessor and PIC are powered down during sleep but the DIO interrupts and optionally the pulse counters, wake-up timers and analogue comparator interrupts remain powered to bring the JN5142 out of sleep.
  • Page 27: Wireless Transceiver

    The 2.4 GHz signal from the VCO is then passed to the RF Power Amplifier (PA), whose power control can be selected from one of three settings. The output of the PA drives the antenna via the RX/TX switch © NXP Laboratories UK 2012 JN-DS-JN5142 1v0...
  • Page 28: Radio External Components

    The RF matching network requires three external components and the IBIAS pin requires one external component as shown in schematic in B.4.1. These components are critical and should be placed close to the JN5142 pins and analogue ground as defined in Table 13. Specifically, the output of the network comprising L2, C1 and L1 is designed to present an accurate match to a 50 ohm resistive network as well as provide a DC path to the final output stage or antenna.
  • Page 29 Figure 17: Antenna Diversity ADO Signal for TX with Acknowledgement If two DIO pins cannot be spared, DIO13 can be configured to be a normal DIO pin, and the inverse of ADO generated with an inverter on the PCB. © NXP Laboratories UK 2012 JN-DS-JN5142 1v0...
  • Page 30: Modem

    The CCA capability of the Modem supports all modes of operation defined in the IEEE 802.15.4 standard, namely Energy above ED threshold, Carrier Sense and Carrier Sense and/or energy above ED threshold. Figure 19: Energy Detect Value vs Receive Power Level JN-DS-JN5142 1v0 © NXP Laboratories UK 2012...
  • Page 31: Baseband Processor

    An interrupt may be provided to indicate successful packet reception. During reception, the modem determines the Link Quality, which is made available at the end of the reception as part of the requirements of IEEE802.15.4. © NXP Laboratories UK 2012 JN-DS-JN5142 1v0...
  • Page 32: Auto Acknowledge

    Part of the protocol allows for transmitted frames to be acknowledged by the destination sending an acknowledge packet within a very short window after the transmitted frame has been received. The JN5142 baseband processor can automatically construct and send the acknowledgement packet without processor intervention and hence avoid the protocol software being involved in time-critical processing within the acknowledge sequence.
  • Page 33: Digital Input/Output

    Two DIO pins can optionally be used to provide control signals for RF circuitry (e.g. switches and PA) in high power range extenders. DIO3/RFTX is asserted when the radio is in the transmit state and similarly, DIO2/RFRX is asserted when the radio is in the receiver state. © NXP Laboratories UK 2012 JN-DS-JN5142 1v0...
  • Page 34 PWM2 PWMs PWM3 DIO7/RXD0/JTAG_TDI/PWM3 SIF_D 2-wire DIO8/TIM0CK_GT/PC1 SIF_CLK Interface DIO9/TIM0CAP/32KXTALIN Pulse DIO10/TIM0OUT/32KXTALOUT Counters DIO11/PWM1 JTAG_TDI JTAG_TMS JTAG DIO12/PWM2/ADO/CTS0/JTAG_TCK JTAG_TCK Debug JTAG_TDO DIO13/PWM3/ADE/RTS0/JTAG_TMS Antenna DIO14/SIF_CLK/TXD0/JTAG_TD0/SPISEL1 Diversity DIO15/SIF_D/RXD0/JTAG_TDI/SPISEL2 DIO16/COMP1P/SIF_CLK DIO17/COMP1M/SIF_D Figure 22: DIO Block Diagram JN-DS-JN5142 1v0 © NXP Laboratories UK 2012...
  • Page 35: Serial Peripheral Interface

    The Serial Peripheral Interface (SPI) allows high-speed synchronous data transfer between the JN5142 and peripheral devices. The JN5142 operates as a master on the SPI bus and all other devices connected to the SPI are expected to be slave devices under the control of the JN5142 CPU. The SPI includes the following features: ...
  • Page 36 16MHz to 125kHz selected by a clock divider. Both SPICLK clock phase and polarity are configurable. The clock phase determines which edge of SPICLK is used by the JN5142 to present new data on the SPIMOSI line; the opposite edge will be used to read data from the SPIMISO line. The interface should be configured appropriately for the SPI slave being accessed.
  • Page 37 If a slave device wishes to signal the JN5142 indicating that it has data to provide, it may be connected to one of the DIO pins that can be enabled as an interrupt.
  • Page 38: Timers

    Shot Interrupt Enable Reset Interrupt Interrupt Generator Generator Fall < Capture TIMxCAP Generator Rise TIMxCK_GT >= TIMxOut Counter Edge Select PWM/DS PWM/DS SYSCLK Prescaler Delta Sigma PWM/DS Figure 26: Timer Unit Block Diagram JN-DS-JN5142 1v0 © NXP Laboratories UK 2012...
  • Page 39: Pulse Width Modulation Mode

    The values in the High and Low registers will be updated whenever there is a corresponding transition on the capture input, and the value stored will be relative to when the © NXP Laboratories UK 2012 JN-DS-JN5142 1v0...
  • Page 40: Counter/Timer Mode

    The integrated output will only reach half VDD2 in RTZ mode, since even at full scale only half the cycle contains pulses. Figure 29 and Figure 30 illustrate the difference between RTZ and NRZ for the same programmed number of pulses. JN-DS-JN5142 1v0 © NXP Laboratories UK 2012...
  • Page 41: Example Timer/Counter Application

    11.1.5 Example Timer/Counter Application Figure 31 shows an application of the JN5142 timers to provide closed loop speed control. Timer 0 is configured in PWM mode to provide a variable mark-space ratio switching waveform to the gate of the NFET. This in turn controls the power in the DC motor.
  • Page 42: Wakeup Timers

    11.3 Wakeup Timers Two 35-bit wakeup timers are available in the JN5142 driven from the 32kHz internal clock. They may run during sleep periods when the majority of the rest of the device is powered down, to time sleep periods or other long period timings that may be required by the application.
  • Page 43: Rc Oscillator Calibration

    16MHz system clock, is provided to allow comparisons to be made between the 32kHz RC clock and the 16MHz system clock when the JN5142 is awake. Wakeup timer0 counts for a set number of 32kHz clock periods during which time the reference counter runs. When the wakeup timer reaches zero the reference counter is stopped, allowing software to read the number of 16MHz clock ticks generated during the time represented by the number of 32kHz ticks programmed in the wakeup timer.
  • Page 44: Pulse Counters

    The system can work with signals up to 100kHz, with no debounce, or from 5.3kHz to 1.7kHz with debounce. When using debounce the 32kHz clock must be active, so for minimum sleep currents the debounce mode should not be used. JN-DS-JN5142 1v0 © NXP Laboratories UK 2012...
  • Page 45: Serial Communications

    13 Serial Communications The JN5142 has a Universal Asynchronous Receiver/Transmitter (UART) serial communication interface. It provides similar operating features to the industry standard 16550A device operating in FIFO mode. The interface performs serial-to-parallel conversion on incoming serial data and parallel-to-serial conversion on outgoing data from the CPU to external devices.
  • Page 46: Interrupts

    Modem Status: Generated when the CTS (Clear To Send) input control line changes. 13.2 UART Application The following example shows the UART connected to a 9-pin connector compatible with a PC. As the JN5142 device pins do not provide the RS232 line voltage, a level shifter is used.
  • Page 47 PC COM Port Signal JN5142 RS232 UART0 Level Shifter Figure 34: JN5142 Serial Communication Link © NXP Laboratories UK 2012 JN-DS-JN5142 1v0...
  • Page 48: Jtag Debug Interface

    It is possible to prevent all hardware debugging by blowing the relevant Efuse bit. For further information on how to program the eFuse, please contact technical support via the on-line tech-support system. The JTAG interface does not support boundary scan testing. It is recommended that the JN5142 is not connected as part of the board scan chain.
  • Page 49: Two-Wire Serial Interface (I C)

    15 Two-Wire Serial Interface (I The JN5142 includes industry standard I C two-wire synchronous Serial Interface operates as a Master (MSIF) or Slave (SSIF) that provides a simple and efficient method of data exchange between devices. The system uses a...
  • Page 50: Clock Stretching

    The first byte of data transferred by the device after a start bit is the slave address. The JN5142 supports both 7-bit and 10-bit slave addresses by generating either one or two address transfers. Only the slave with a matching address will respond by returning an acknowledge bit.
  • Page 51 (N.B. Loss of arbitration may occur at any point during the transfer, including data cycles). An interrupt will be generated when arbitration has been lost. © NXP Laboratories UK 2012 JN-DS-JN5142 1v0...
  • Page 52: Slave Two-Wire Serial Interface

    The last data in a transfer has completed – i.e. the end of a burst of data, when a Stop or Restart is seen  A protocol error has been spotted on the interface JN-DS-JN5142 1v0 © NXP Laboratories UK 2012...
  • Page 53: Random Number Generator

    The random bits are generated by sampling the state of the 32MHz clock every 32kHz system clock edge. As these clocks are asynchronous to each other, each sampled bit is unpredictable and hence random. © NXP Laboratories UK 2012 JN-DS-JN5142 1v0...
  • Page 54: Analogue Peripherals

    17 Analogue Peripherals The JN5142 contains a number of analogue peripherals allowing the direct connection of a wide range of external sensors and switches. Chip Boundary Supply Voltage (VDD1) Vref Internal Reference ADC1 Vref Select VREF/ADC2 ADC3 (DIO0) ADC4 (DIO1)
  • Page 55: Operation

    Software can then be used to apply the appropriate rounding and shifting to generate the average value, as well as setting up the accumulation function. For detailed electrical specifications, see Section 19.3.6. © NXP Laboratories UK 2012 JN-DS-JN5142 1v0...
  • Page 56: Supply Monitor

    17.2 Comparator The JN5142 contains one analogue comparator, COMP1, that is designed to have true rail-to-rail inputs and operate over the full voltage range of the analogue supply VDD1. The hysteresis level can be set to a nominal value of 0mV, 10mV, 20mV or 40mV.
  • Page 57: Power Management And Sleep Modes

    18.2 Active Processing Mode Active processing mode in the JN5142 is where all of the application processing takes place. By default, the CPU will execute at the selected clock speed executing application firmware. All of the peripherals are available to the application, as are options to actively enable or disable them to control power consumption;...
  • Page 58: Wakeup Timer Event

    The ability to wakeup when continuously monitoring analogue signals is useful in ultra-low power applications. For example, the JN5142 can remain in sleep mode until the voltage drops below a threshold and then be woken up to deal with the alarm condition.
  • Page 59: Electrical Characteristics

    Most parameter values cover the extended temperature range up to 125 ºC, where this is not the case, two values are given, the value in italics type face is for standard temperature range up to 85ºC and the value in bold is for the extended range. © NXP Laboratories UK 2012 JN-DS-JN5142 1v0...
  • Page 60: Dc Current Consumption

    For full 32KB retained RAM retention– measured at 25ºC Comparator (low-power mode) µA Reduced response time 19.2.2.3 Deep Sleep Mode Mode: Unit Notes Deep sleep mode– measured Waiting on chip RESET or I/O at 25ºC event JN-DS-JN5142 1v0 © NXP Laboratories UK 2012...
  • Page 61: I/O Characteristics

    Input Leakage Current 15, 50 Vcc = 3.6V, pin high IH - 19.3 AC Characteristics 19.3.1 Reset and Supply Voltage Monitor Internal RESET STAB Figure 40: Internal Power-on Reset without Showing Brown-Out RESETN © NXP Laboratories UK 2012 JN-DS-JN5142 1v0...
  • Page 62 3.01 3.10 Supply Voltage Monitor Corresponding to the 8 Hysteresis (V threshold levels Time from release of reset to start of executing ROM code. Loading program from Flash occurs in addition to this. JN-DS-JN5142 1v0 © NXP Laboratories UK 2012...
  • Page 63: Spi Master Timing

    16.7 @ 3.3V 18.2 @ 2.7V 21.0 @ 2.0V Data hold time Data invalid period Select set-up period Select hold period 30 (SPICLK = 16MHz) 0 (SPICLK<16MHz, mode=0 or 2) 60 (SPICLK<16MHz, mode=1 or 3) © NXP Laboratories UK 2012 JN-DS-JN5142 1v0...
  • Page 64: Two-Wire Serial Interface

    Sleep (memory not program size in external Flash is held) KBytes 16MHz Wake up from Sleep µs Start-up runs from (memory held) High-Speed RC oscillator Wake up from CPU Doze µs mode JN-DS-JN5142 1v0 © NXP Laboratories UK 2012...
  • Page 65: Bandgap Reference

    µs Programmable Input voltage range 0.04 Vref Switchable. Refer to 17.1.1 or 2*Vref Vref (Internal) See Section 19.3.5 Vref (External) 1.15 Allowable range into VREF pin Input capacitance In series with 5K ohms © NXP Laboratories UK 2012 JN-DS-JN5142 1v0...
  • Page 66: Comparator

    +30% Typical is at 3.0V 25C accuracy Calibrated 32kHz accuracy ±250 For a 1 second sleep period calibrating over 20 x 32kHz clock periods Variation with temperature -0.010 %/°C Variation with VDD2 -1.8 JN-DS-JN5142 1v0 © NXP Laboratories UK 2012...
  • Page 67: 32Khz Crystal Oscillator

    DC voltages, 390/425 425/465 470/520 XTALIN/XTALOUT 375/405 External Capacitors Total external capacitance needs to (CL=9pF) be 2*CL, allowing for stray capacitance from chip, package and Amplitude detect threshold mVp-p Threshold detection accessible via API © NXP Laboratories UK 2012 JN-DS-JN5142 1v0...
  • Page 68: High-Speed Rc Oscillator

    C Non-linearity 2.5, 3.5 Output Voltage 630, 570 Includes absolute variation due to manufacturing & temp Typical Voltage Typical at 3.0V 25C C/LSB Resolution 0.154 0.182 0.209 0 to Vref ADC I/P Range JN-DS-JN5142 1v0 © NXP Laboratories UK 2012...
  • Page 69: Radio Transceiver

    19.3.13 Radio Transceiver This JN5142 meets all the requirements of the IEEE802.15.4 standard over 2.0 - 3.6V and offers the following improved RF characteristics. All RF characteristics are measured single ended. This part also meets the following regulatory body approvals, when used with NXP‟s Module Reference Designs.
  • Page 70 The following exceptions apply 1.8 to 1.9GHz & 5.15 to 5.3GHz <-70 EVM [Offset] 10 [2.0] At maximum output power Transmit Power At greater than 3.5MHz offset, as Spectral Density per 802.15.4, Section 6.5.3.1 JN-DS-JN5142 1v0 © NXP Laboratories UK 2012...
  • Page 71 The following exceptions apply 1.8 to 1.9GHz & 5.15 to 5.3GHz <-70 EVM [Offset] 9 [2.0] At maximum output power Transmit Power At greater than 3.5MHz offset, as Spectral Density per 802.15.4, Section 6.5.3.1 © NXP Laboratories UK 2012 JN-DS-JN5142 1v0...
  • Page 72 The following exceptions apply 1.8 to 1.9GHz & 5.15 to 5.3GHz <-70 EVM [Offset] 10 [2.0] At maximum output power Transmit Power At greater than 3.5MHz offset, as Spectral Density per 802.15.4, Section 6.5.3.1 JN-DS-JN5142 1v0 © NXP Laboratories UK 2012...
  • Page 73 The following exceptions apply 1.8 to 1.9GHz & 5.15 to 5.3GHz <-70 EVM [Offset] 10 [3.0] At maximum output power Transmit Power At greater than 3.5MHz offset, as Spectral Density per 802.15.4, Section 6.5.3.1 © NXP Laboratories UK 2012 JN-DS-JN5142 1v0...
  • Page 74 Note1: Blocker rejection is defined as the value, when 1% PER is seen with the wanted signal 3dB above sensitivity, as per 802.15.4 Section 6.5.3.4 Note2: Channels 11,17,24 low/high values reversed. Note3: Up to an extra 2.5dB of attenuation is available if required. JN-DS-JN5142 1v0 © NXP Laboratories UK 2012...
  • Page 75: Appendix A Mechanical And Ordering Information

    0.05 0.30 4.75 4.75 0.5 4.5 4.5 0.1 0.05 0.05 0.1 0.00 0.18 4.45 4.45 Table 11: Package Dimensions  Plastic or metal protrusions of 0.075 mm maximum per side are not included. © NXP Laboratories UK 2012 JN-DS-JN5142 1v0...
  • Page 76: Footprint Information

    Information for reflow soldering. All dimensions are given in the table underneath. Figure 46: PCB Decal SPx tot Spy tot SPx 0.500 7.000 7.000 5.200 5.200 0.900 0.290 4.100 4.100 2.400 2.400 0.600 0.600 6.300 6.300 7.250 7.250 Table 12: Footprint Dimensions JN-DS-JN5142 1v0 © NXP Laboratories UK 2012...
  • Page 77  The PCB schematic and layout rules detailed in Appendix B.4 must be followed. Failure to do so will likely result in the JN5142 failing to meet the performance specification detailed herein and worst case may result in device not functioning in the end application.
  • Page 78: Ordering Information

    A.3 Ordering Information The standard qualification for the JN5142 is extended industrial temperature range: -40ºC to +125ºC, packaged in a 40-pin QFN package. Ordering code format: JN5142N / XXX XXX: ROM Variant: IEEE802.15.4, RF4CE and Active RFID JenNet-IP The device is available in two different reel quantities ...
  • Page 79: Device Package Marking

    The package on the right shows the specific markings for a JN5142 device, with revision B ROM software, that came from assembly build number 01 and was manufactured week 25 of 2011.
  • Page 80: Tape And Reel Information

    Measured from centreline of sprocket hole to centreline of pocket Cumulative tolerance of 10 sprocket holes is 0.20mm (II) (III) Measured from centreline of sprocket hole to centreline of pocket (IV) Other material available Figure 49: Tape Dimensions JN-DS-JN5142 1v0 © NXP Laboratories UK 2012...
  • Page 81: Reel Information: 180Mm Reel

    All dimensions and tolerances are fully compliant with EIA-481-B and are specified in millimetres. 6 window design with one window on each side blanked to allow adequate labelling space. Figure 50: Reel Dimensions © NXP Laboratories UK 2012 JN-DS-JN5142 1v0...
  • Page 82: Reel Information: 330Mm Reel

    C, and is dried before sealing in a moisture barrier bag (MBB) with desiccant bag weighing at 67.5 grams of activated clay and a humidity indicator card (HIC) meeting MIL-L-8835 specification. The MBB has a moisture-sensitivity caution label to indicate the moisture-sensitive classification of the enclosed devices. JN-DS-JN5142 1v0 © NXP Laboratories UK 2012...
  • Page 83: Appendix B Development Support

    PCB parasitic capacitance. With the recommended layout this is about 1.6pF is the on-chip parasitic capacitance and is about 1.4pF typically. Similarly for Hence for a 9pF load capacitance, and a tight layout the external capacitors should be 15pF © NXP Laboratories UK 2012 JN-DS-JN5142 1v0...
  • Page 84: Crystal Esr And Required Transconductance

    =18pF ( for a load capacitance of 9pF), the equation above gives the required transconductance ( ) as 2.59mA/V. The JN5142 has a typical value for transconductance of 4.3mA/V The example and equation illustrate the trade-off that exists between the load capacitance and crystal ESR. For example, a crystal with a higher load capacitance can be used, but the value of max.
  • Page 85: 32Mhz Oscillator

    B.2 32MHz Oscillator The JN5142 contains the necessary on-chip components to build a 32 MHz reference oscillator with the addition of an external crystal resonator, two tuning capacitors. The schematic of these components are shown in Figure 52. The two capacitors, C1 and C2, will typically be 15pF ±5% and use a COG dielectric. For a detailed specification of the crystal required and factors affecting C1 and C2 see Appendix B.1.
  • Page 86 Circuit techniques have been used to apply compensation, such that the user need only design for nominal conditions. 32MHz Crystal Oscillator 4.35 4.25 4.15 Temperature (C) 32MHz Crystal Oscillator 4.31 4.29 4.28 Supply Voltage (VDD) JN-DS-JN5142 1v0 © NXP Laboratories UK 2012...
  • Page 87: 32Khz Oscillator

    B.3 32kHz Oscillator In order to obtain more accurate sleep periods, the JN5142 contains the necessary on-chip components to build an optional 32kHz oscillator with the addition of an external 32.768kHz crystal and two tuning capacitors. The crystal should be connected between XTAL32K_IN and XTAL32K_OUT (DIO9 and DIO10), with two equal capacitors to ground, one on each pin.
  • Page 88 Below is measurement data showing the variation of the crystal oscillator supply current with voltage and with crystal ESR, for two load capacitances. 32KHz Crystal Oscillator Current Supply Voltage (VDD) 32KHz Crystal Oscillator Current 12.5pF Crystal ESR (K ohm) JN-DS-JN5142 1v0 © NXP Laboratories UK 2012...
  • Page 89: Jn5142 Module Reference Designs

    B.4 JN5142 Module Reference Designs For customers wishing to integrate the JN5142 device directly into their system, NXP provide a range of Module Reference Designs, covering standard and high-power modules fitted with different Antennae To ensure the correct performance, it is strongly recommended that where possible the design details provided by the reference designs, are used in their exact form for all end designs, this includes component values, pad dimensions, track layouts etc.
  • Page 90 R1: 43k C20: 100nF VB_RF L2: 2.7nH SPI Select To coaxial socket or integrated antenna VB_RF L1: 5.6nH C1: 47pF C12: 47pF C3: 100nF Figure 54: JN5142 Printed Antenna Reference Module Schematic Diagram JN-DS-JN5142 1v0 © NXP Laboratories UK 2012...
  • Page 91 Load Inductor MuRata LQP15MN2N7B02 Table 13: JN5142 Printed Antenna Reference Module Components and PCB Layout Constraints The paddle should be connected directly to ground. Any pads that require connection to ground should do so by connecting directly to the paddle.
  • Page 92: Pcb Design And Reflow Profile

    [8]. Depending on the damage after this test, an MSL of 1 (not sensitive to moisture) to 6 (very sensitive to moisture) is attached to the semiconductor package. JN-DS-JN5142 1v0 © NXP Laboratories UK 2012...
  • Page 93: Related Documents

    [9] JN-AN-1003 Boot Loader Operation RoHS Compliance JN5142 devices meet the requirements of Directive 2002/95/EC of the European Parliament and of the Council on the Restriction of Hazardous Substance (RoHS) and of the China RoHS (SJ/T11363 – 2006) requirements which came into force on 1 March 2007.
  • Page 94: Disclaimers

    All trademarks are the property of their respective owners. Version Control Version Notes 26/10/10 – First issue, released as Advance Information 22/12/11 - Major revision including the electrical parameters and appendix A JN-DS-JN5142 1v0 © NXP Laboratories UK 2012...
  • Page 95: Contact Details

    S1 4QT United Kingdom Tel: +44 (0)114 281 2655 Fax: +44 (0) 114 281 2951 For the contact details of your local NXP office or distributor, refer to the NXP web site: www.nxp.com © NXP Laboratories UK 2012 JN-DS-JN5142 1v0...

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