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RDC R8810LV User Manual

16-bit microcontroller
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R D C
®
RISC DSP Controller
16-Bit RISC Microcontroller User's Manual
RDC Semiconductor Co.
Subject to change without notice
R8810LV
RDC
RISC DSP Controller
RDC Semiconductor Co., Ltd
http:\\www.rdc.com.tw
Tel. 886-3-666-2866
Fax 886-3-563-1498
1
R8810LV
Rev:1.2

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  • Page 1 R D C ® R8810LV RISC DSP Controller R8810LV 16-Bit RISC Microcontroller User’s Manual RISC DSP Controller RDC Semiconductor Co., Ltd http:\\www.rdc.com.tw Tel. 886-3-666-2866 Fax 886-3-563-1498 Rev:1.2 RDC Semiconductor Co. Subject to change without notice...

  • Page 2: Table Of Contents

    ----------------------------------------------------------------31 MCSx ----------------------------------------------------------------32 PCSx - Interrupt Controller Unit ------------------------------------------------34 -----------------------------------------34 Master Mode and Slave Mode -----------------------------------35 Interrupt Vector, Type and Priority -----------------------------------------------------36 = Interrupt Request -----------------------------------------------36 Interrupt Acknowledge ------------------------------------------------37 Programming Register Rev:1.2 RDC Semiconductor Co. Subject to change without notice...
  • Page 3 - PIO Unit-------------------------------------------------------------------71 -----------------------------------71 PIO Multi-Function Pin list Table - PSRAM Control Unit ----------------------------------------------------74 - Instruction Set Opcodes and Clock Cycle -----------------------------75 ---------------------------------------79 R8810LV Execution Timings - DC Characteristics -------------------------------------------------------80 - AC Characteristics -------------------------------------------------------82 - Package Information-----------------------------------------------------91 - Revision History ----------------------------------------------------------93 Rev:1.2 RDC Semiconductor Co.

  • Page 4: Features

    Serial Eflag Register SRDY Unit Port S2~S0 DT/R Interface HOLD Execution (Special, HLDA Unit Logic, Unit Synchronous S6/CLKDIV2 Adder, BSF) Serial Interface SCLK SDATA A19~A0 SDEN0 SDEN1 AD7~AD0 AO15~AO8 RFSH/ADEN Rev:1.2 RDC Semiconductor Co. Subject to change without notice...

  • Page 5: Pin Configuration

    RFSH2/ADEN DRQ0/PIO12 DRQ1/PIO13 TMRIN0/PIO11 TMROUT0/PIO10 ARDY TMROUT1/PIO1 TMRIN1/PIO0 MCS3/RFSH/PIO25 MCS2/PIO24 R8810LV PCS0/PIO16 Microcontroller CLKOUTA PCS1/PIO17 CLKOUTB PCS2/PIO18 A19/PIO9 PCS3/PIO19 A18/PIO8 PCS5/A1/PIO3 A17/PIO7 PCS6/A2/PIO2 LCS/ONCE0 UCS/ONCE1 INT0 INT1/SELECT INT2/INTA0/PIO31 INT3/INTA1/IRQ INT4/PIO30 MCS1/PIO15 Rev:1.1 RDC Semiconductor Co. Subject to change without notice...
  • Page 6 R D C ® R8810LV RISC DSP Controller (LQFP) INT4/PIO30 MCS1/PIO15 MCS0/PIO14 DEN/PIO5 DT/R/PIO4 AO10 SRDY/PIO6 AO11 HOLD HLDA AO12 R8810LV AO13 AO14 AO15 S6/CLKDIV2/PIO29 UZI/PIO26 TXD/PIO27 RXD/PIO28 SDATA/PIO21 SDEN1/PIO23 SDEN0/PIO22 Rev:1.1 RDC Semiconductor Co. Subject to change without notice...

  • Page 7: Pqfp And Lqfp Pin-Out Table

    R D C ® R8810LV RISC DSP Controller R8810LV Pin Number Comparison Table Pin name LQFP Pin No. PQFP Pin No. Pin name LQFP Pin No. PQFP Pin No. AO10 AO11 AO12 AO13 AO14 HLDA AO15 HOLD SRDY/PI O6 /PI O29...

  • Page 8: Pin Description

    Address latch enable. Active high. This pin indicates that an Output address output on the AD bus. Address is guaranteed to be valid on the trailing edge of ALE. This pin is tri-stated during Rev:1.1 RDC Semiconductor Co. Subject to change without notice...
  • Page 9 UCS , LCS , PCS - PCS , MCS - PCS - will be drive high. After HOLD is detected as being low, the microcontroller will lower HLDA. Rev:1.1 RDC Semiconductor Co. Subject to change without notice...
  • Page 10 Output/Input LCS / ONCE defined portion memory block of the lower 512K (00000h- 7FFFFh) memory region. The address range acting LCS is Rev:1.1 RDC Semiconductor Co. Subject to change without notice...
  • Page 11 INT0. Maskable interrupt request 1/slave select. For INT1 feature, Input/Output except the difference interrupt line and interrupt address vector, INT1/ SELECT the function of INT1 is the same as INT4. Rev:1.1 RDC Semiconductor Co. Subject to change without notice...
  • Page 12 (pin76) can be as a PIO13 when enable the PIO Data register. 2.The PIO status during Power-On reset : PIO1, PIO10, PIO22, PIO23 are input with pull-down, PIO4 to PIO9 are normal operation and the others are input with pull-up. Rev:1.1 RDC Semiconductor Co. Subject to change without notice...

  • Page 13: Basic Application System Block

    Flash ROM D7-D0 Data(8) Address DT/R AD7-AD0 Transciver SRAM Data(8) RS232 Serial port0 AD7-AD0 Level Address A19-A0 AO15-AO8 R8810LV Converter A19-A16 Latch Timer0-1 Peripheral Data Address 100K BASIC APPLICATION SYSTEM BLOCK (B) Rev:1.1 RDC Semiconductor Co. Subject to change without notice...

  • Page 14: Oscillator Characteristics

    C1 --- 20pF ± 20% ; C2 --- 20pF ± 20% ; C3 --- 200pf ; Rf --- 1 mega-ohm L --- 3.0uH ± 20% (40MHz) , 4.7uH ± 20% (33MHz) 8.2uH ± 20% (25MHz) , 12uH ± 20% (20MHZ) Rev:1.1 RDC Semiconductor Co. Subject to change without notice...

  • Page 15: Read/Write Timing Diagram

    R D C ® R8810LV RISC DSP Controller Read/Write timing Diagram CLKOUTA A19:A0 ADDRESS AD7:AD0 ADDRESS DATA AO15:AO8 ADDRESS UCS,LCS DT/R S2:S0 READ CYCLE Rev:1.1 RDC Semiconductor Co. Subject to change without notice...
  • Page 16 R D C ® R8810LV RISC DSP Controller CLKOUTA A19:A0 ADDRESS AD7:AD0 ADDRESS DATA AO15:AO8 ADDRESS UCS,LCS DT/R S2:S0 WRITE CYCLE Rev:1.1 RDC Semiconductor Co. Subject to change without notice...

  • Page 17: Execution Unit

    CS (Code Segment) : The CS register points to the current code segment, which contains instruction to be fetched. The default location memory space for all instruction is 64K. The initial value of CS register is 0FFFFh. Rev:1.1 RDC Semiconductor Co. Subject to change without notice...

  • Page 18: Instruction Pointer And Status Flags Register

    Bit 9 : IF, Interrupt-Enable Flag. Refer the STI and CLI instructions for how to set and clear the IF flag. Set to 1 : The CPU enables the maskable interrupt request. Rev:1.1 RDC Semiconductor Co. Subject to change without notice...

  • Page 19: Address Generation

    16-bit segment and 16-bit offset. The Physical Address Generation figure describes how the logical address transfers to the physical address. Shift left 4 bits Segment Base Logical Address Offset Physical Address TO Memory Physical Address Generation Rev:1.1 RDC Semiconductor Co. Subject to change without notice...

  • Page 20: Peripheral Control Block Register

    PIO Mode 1 Register Synchronous Serial Transmit 0 Register PIO Data 0 Register Synchronous Serial Transmit 1 Register PIO Direction 0 Register Synchronous Serial Enable Register PIO Mode 0 Register Synchronous Serial Status Register Rev:1.1 RDC Semiconductor Co. Subject to change without notice...
  • Page 21 Processor Release Level Register Reset Value : Read only register that specifies the processor release version and RDC identify number Bit 15-8 : Processor version 01h : version A , 02h : version B, 03h : version C, 04h : version D Bit 7-0 : RDC identify number - D9h Rev:1.1...

  • Page 22: System Clock Block

    Set 0 : CLKOUTB output frequency is from the clock divisor, which frequency is same as that of microprocessor internal clock . Bit 8: CAD, CLKOUTA Drive Disable. Set 1: Disable the CLKOUTA. This pin will be three-state. Rev:1.2 RDC Semiconductor Co. Subject to change without notice...

  • Page 23: Reset

    2 when S6/ CLKDIV with pull-low resister. The AD7-AD0, AO15-AO8 will not drive the address phase during UCS , LCS cycle if BHE / ADEN with pull-low resister Rev:1.2 RDC Semiconductor Co. Subject to change without notice...
  • Page 24 AO8, AD7 to AD0) be latched into this register during the RST pin from low go high. And the value of the reset configuration register provides the system information when software read this register. This register is read only and the contents remain valid until the next processor reset. Rev:1.2 RDC Semiconductor Co. Subject to change without notice...

  • Page 25: Bus Interface Unit

    The memory address space data bus is physically implemented as one bank of 1M bytes. Address lines A19-A0 select a specific byte within the bank. Byte transfers to even or odd addresses transfer information in one bus cycle. Word transfers to Rev:1.2 RDC Semiconductor Co. Subject to change without notice...

  • Page 26: Wait States

    The wait state counter value is decided by the R1,R0 bits in each chip select register. There are five group R2,R1,R0 bits in the registers offset A0h, A2h, A4h, A6h, A8h. Each group is independent. Case1 Case2 Case3 CLKOUTA Ready Bus Ready Waveform Rev:1.2 RDC Semiconductor Co. Subject to change without notice...

  • Page 27: Bus Hold

    HLDA. Case 1 Case 2 CLKOUTA HOLD HLDA AD7:AD0 Floating AO15:AO8 Floating Floating A19:A0 Floating Floating Floating Floating Floating DT/R S2:S0 Floating Floating BUS HOLD ENTER WAVEFORM Rev:1.2 RDC Semiconductor Co. Subject to change without notice...
  • Page 28 RISC DSP Controller Case 1 Case 2 CLKOUTA HOLD HLDA AD7:AD0 Floating DATA AO15:AO8 Floating Address Floating A19:A0 ADDRESS Floating Floating Floating Floating Floating DT/R S2:S0 Floating Floating BUS HOLD LEAVE WAVEFORM Rev:1.2 RDC Semiconductor Co. Subject to change without notice...

  • Page 29: Chip Select Unit

    Bit 2 : R2, Ready Mode. This bit is used to configure the ready mode for UCS chip select. Set 1: external ready is ignored. Set 0: external ready is required. Rev:1.2 RDC Semiconductor Co. Subject to change without notice...

  • Page 30: Lcs

    PSE set to 1: PSRAM support is enable PSE set to 0: PSRAM support is disable Bit 5-3: Reserved Bit 2 : R2, Ready Mode. This bit is used to configure the ready mode for LCS chip select. Rev:1.2 RDC Semiconductor Co. Subject to change without notice...

  • Page 31: Mcsx

    Bit 1-0 : R1-R0, Wait-State value. The R1,R0 determines the number of wait states inserted into a MCS access. (R1,R0) : (1,1) – 3 wait states , (1,0) – 2 wait states, (0,1) – 1 wait states , (0,0) – 0 wait states Rev:1.2 RDC Semiconductor Co. Subject to change without notice...

  • Page 32: Pcsx

    The peripheral or memory chip selects which are programmed through A4h and A8h register to define these pins. The base address memory block can be located anywhere within the 1M bytes memory space, exclusive of the areas associated Rev:1.2 RDC Semiconductor Co. Subject to change without notice...
  • Page 33 Bit 2 : R2, Ready Mode. This bit is configured to enable/disable the wait states inserted for the PCS3 - PCS0 chip selects. The R3,R1,R0 bits determine the number of wait state to insert. set to 1: external ready is ignored set to 0: external ready is required Rev:1.2 RDC Semiconductor Co. Subject to change without notice...

  • Page 34: Interrupt Controller Unit

    The interrupt controller can be programmed as a master or slave mode. (program FEh , bit 14). The master mode has two connections : Fully Nested Mode connection or Cascade Mode connection. INT0 Interrupt Source INT1 Interrupt Source INT2 Interrupt Source INT3 Interrupt Source INT4 Interrupt Source R8810LV Fully Nested Mode Connections Rev:1.2 RDC Semiconductor Co. Subject to change without notice...

  • Page 35: Interrupt Vector, Type And Priority

    The Vector addresses for each interrupt are fixed. Interrupt source Interrupt Vector Priority Note Type Address Type Divide Error Exception Trace interrupt Breakpoint Interrupt INTO Detected Over Flow Exception 04h Rev:1.2 RDC Semiconductor Co. Subject to change without notice...

  • Page 36: Interrupt Request

    The internal interrupt controller provides the interrupt type to processor without external bus cycles generation. When an external interrupt controller is supplying the interrupt type, the processor generates two acknowledge bus cycles, and the interrupt type is written to the AD7-AD0 lines by the external interrupt controller. Rev:1.2 RDC Semiconductor Co. Subject to change without notice...

  • Page 37: Programming Register

    Serial Port Interrupt Control Register Offset : 44h Reset Value : 001Fh Reserved (Master Mode) Bit 15-4 : Reserved Bit 3: MSK, Mask. Set 1: Mask the interrupt source of the asynchronous serial port. Rev:1.2 RDC Semiconductor Co. Subject to change without notice...
  • Page 38 Set 1: Mask the interrupt source of the INT4 Set 0: Enable the INT4 interrupt. Bit 2-0: PR, Interrupt Priority These bits setting for priority selection is same as bit 2-0 of 44h Rev:1.2 RDC Semiconductor Co. Subject to change without notice...
  • Page 39 Set 1: Mask the interrupt source of the INT2 Set 0: Enable the INT2 interrupt. Bit 2-0: PR, Interrupt Priority These bits setting for priority selection is same as bit 2-0 of the register 44h Rev:1.2 RDC Semiconductor Co. Subject to change without notice...
  • Page 40 Bit 2-0: PR, Interrupt Priority These bits setting for priority selection is same as bit 2-0 of the register 44h Offset : 38h INT0 Control Register Reset Value : 000Fh Reserved SFNM (Master Mode) Rev:1.2 RDC Semiconductor Co. Subject to change without notice...
  • Page 41 Set 0: Enable the DMA 1 controller interrupt. Bit 2-0: PR, Interrupt Priority These bits setting for priority selection is same as bit 2-0 of the register 44h (Slave Mode), reset value is 0000h Rev:1.2 RDC Semiconductor Co. Subject to change without notice...
  • Page 42 These bits setting for priority selection is same as bit 2-0 of the register 44h Offset : 32h Timer Interrupt Control Register Reset Value : 000Fh (Master Mode) Bit 15-4 : Reserved Rev:1.2 RDC Semiconductor Co. Subject to change without notice...
  • Page 43 Set 1: halts any DMA activity. When non-maskable interrupts occur. Set 0: When an IRET instruction is executed. Bit 14-3 : Reserved. Bit 2-0 : TMR2-TMR0 , Set 1: indicates the corresponding timer has an interrupt request pending. Rev:1.2 RDC Semiconductor Co. Subject to change without notice...
  • Page 44 Set 1: Indicates the state of any interrupt requests form the associated timer. Bit 3-2 : D1-D0, DMA Channel Interrupt Request. Set 1: Indicates the corresponding DMA channel has an interrupt pending. Rev:1.2 RDC Semiconductor Co. Subject to change without notice...
  • Page 45 The bits in the In-Service register are set by the interrupt controller when the interrupt is taken. The in- cleared by writing to the EOI register. Bit 15-6 : Reserved. Bit 5-4 : TMR2-TMR1 , Timer2/Timer1 Interrupt In-Service. Rev:1.2 RDC Semiconductor Co. Subject to change without notice...
  • Page 46 Bit 2-0 : PRM2-PRM0 , Priority Field Mask. Determining the minimum priority that is required in order for a maskable interrupt source to generate an interrupt. Priority PR2-PR0 (High) 0 (Low) 7 Rev:1.2 RDC Semiconductor Co. Subject to change without notice...
  • Page 47 Poll Status Register Reset Value : IREQ Reserved S4 - S0 (Master Mode) The Poll Status (POLLST) register mirrors the current state of the Poll register. the POLLST register can be read without Rev:1.2 RDC Semiconductor Co. Subject to change without notice...
  • Page 48 Set 0: indicates the specific EOI interrupt type in S4-S0. Bit 14-5 : Reserved. Bit 4-0: S4-S0, Source EOI Type. Specifies the EOI type of the interrupt that is currently being processed. Rev:1.2 RDC Semiconductor Co. Subject to change without notice...
  • Page 49 Timer 1 interrupt controller : (T4,T3,T2,T1,T0, 1, 0, 0)b DMA 1 interrupt controller : (T4,T3,T2,T1,T0, 0, 1, 1)b DMA 0 interrupt controller : (T4,T3,T2,T1,T0, 0, 1, 0)b Timer 0 interrupt controller : (T4,T3,T2,T1,T0, 0, 0, 0)b Bit 2-0 :Reserved Rev:1.2 RDC Semiconductor Co. Subject to change without notice...

  • Page 50: Dma Unit

    DMA request. The registers ( CAh, C8h, C6h, C4h, C2h, C0h, DAh, D8h, D6h, D4h, D2h, D0h) are used to configure and operate the two DMA channels. Rev:1.2 RDC Semiconductor Co. Subject to change without notice...
  • Page 51 Bit 15-0: TC15-TC0, DMA 0 transfer Count. The value of this register is decremented by 1 after each transfer. DMA Destination Address High Register Offset : C6h (DMA0) Reset Value : Reserved DDA19 - DDA16 Bit 15-4: Reserved Rev:1.2 RDC Semiconductor Co. Subject to change without notice...
  • Page 52 The value of (DSA19-DSA0)b will increment or decrement by 2 after each DMA transfer. DMA Control Registers Offset : DAh (DMA1) Reset Value : FFF9h DM/IO DDEC DINC SM/IO SDEC SINC SYN1 SYN0 TDRQ Rev:1.2 RDC Semiconductor Co. Subject to change without notice...
  • Page 53 Set 1: It selects high priority for this channel when both DMA 0 and DMA 1 are transfer in same time. Bit 4: TDRQ, Timer Enable/Disable Request Set 1: Enable the DMA requests from timer 2. Rev:1.2 RDC Semiconductor Co. Subject to change without notice...
  • Page 54 Bit 15-0: DDA15-DDA0, Low DMA 1 Destination Address. These bits are mapped to A15- A0 during a DMA transfer. The value of (DDA19-DDA0)b will increment or decrement by 2 after each DMA transfer. Rev:1.2 RDC Semiconductor Co. Subject to change without notice...

  • Page 55: External Request

    DMA transfer can be either source or destination synchronized, and it can also be unsynchronized. The Source-Synchronized Transfer figure shows the typical source-synchronized transfer which provides the source device at least three clock cycles from the time it is acknowledged to deassert its DRQ line. Rev:1.2 RDC Semiconductor Co. Subject to change without notice...
  • Page 56 Case1 : Current destination synchronized transfer will not be immediately followed by another DMA transfer. Case2 : Current destination synchronized transfer will be immediately followed by another DMA transfer. Destination-Synchronized Transfers Rev:1.2 RDC Semiconductor Co. Subject to change without notice...

  • Page 57: Timer Control Unit

    CONT These bits definition for timer 0 are same as the bits of register 5Eh for timer 1. Offset : 50h Timer 0 Count Register Reset Value : TC15 - TC0 Rev:1.2 RDC Semiconductor Co. Subject to change without notice...
  • Page 58 A or max-count B Set 0: Timer 1 will not issue interrupt request. Bit 12: RIU, Register in Use Bit. Set 1: The Maxcount Compare B register of timer 1 is being used Rev:1.2 RDC Semiconductor Co. Subject to change without notice...
  • Page 59 Bit 0: CONT, Continuous Mode Bit. Set 1: The timer to run continuously. Set 0: The timer will halt after each counting to the maximum count and the EN bit will be cleared. Rev:1.2 RDC Semiconductor Co. Subject to change without notice...
  • Page 60 INH bit and EN bit must be in the same write. This bit is not stored and is always read as 0. Bit 13: INT, Interrupt Bit. Rev:1.2 RDC Semiconductor Co. Subject to change without notice...

  • Page 61: Watchdog Timer

    , The Timer 1 Count Register must be reloaded at intervals less than the Timer 1 Maxcount value to assure the watchdog interrupt is not occurred. Watchdog Timer Interrupt Control Register Offset : 42h Reset Value : 000Fh Reserved Rev:1.2 RDC Semiconductor Co. Subject to change without notice...

  • Page 62: Timer/Counter Unit Output Mode

    Maxcount A Maxcount B Maxcount A Maxcount B Dual Maximum Count Mode Maxcount A Maxcount A Maxcount A Single Maximum Count Mode * 1T:One Microprocessor clock Timer/Counter Unit Output Modes Rev:1.2 RDC Semiconductor Co. Subject to change without notice...

  • Page 63: Asynchronous Serial Port

    Set 1: The serial port in the loopback mode. In this mode, the transmit shift register is connect to the transmit shift register internal and the TXD pin output high. It provides the serial port testing in this mode. Bit 8: BRK, Send Break. Rev:1.2 RDC Semiconductor Co. Subject to change without notice...
  • Page 64 (84h) can be written a new data. When this bit is 0, it indicate that transmit holding buffer contains valid data that not yet been copied to transmit shift register and the transmit data register (84h) Rev:1.2 RDC Semiconductor Co. Subject to change without notice...
  • Page 65 Reset Value : Reserved RDATA Bit 15-8: Reserved Bit 7-0: RDATA , Received DATA. The PDR bit (82h.4) should be read as 1 before read the RDATA register to avoid reading invalid data. Rev:1.2 RDC Semiconductor Co. Subject to change without notice...
  • Page 66 The general formula for baud rate divisor is Baud Rate = Microprocessor Clock / [32 * (BAUDDIV+1)] For example, The Microprocessor clock is 22.1184MHz and the BAUDDIV=5 (Decimal), the baud rate of serial port is 115.2k. Rev:1.2 RDC Semiconductor Co. Subject to change without notice...

  • Page 67: Synchronous Serial Port

    This read/write register controls the operation of the SDEN0-SDEN1 outputs the transfer rate of the SSI port. Bit 15-3 : Reserved. Bit 3-2 : SCLKDIV, SCLK Divide. SCLKDIV SCLK Frequency Divider Processor clock/2 Processor clock/4 Rev:1.2 RDC Semiconductor Co. Subject to change without notice...
  • Page 68 Bit 7-0: SD, Send Data. Data to transmit over the SDATA pin. Offset : 18h Synchronous Serial receive Register Reset Value : Reserved Th Synchronous Serial Receive Register contains the data transferred from the peripheral to the processor on a read Rev:1.2 RDC Semiconductor Co. Subject to change without notice...

  • Page 69: Synchronous Serial Port Operation

    Read From 10h or SDEN1 (dummy) SDATA Bit0 Bit7 Bit0 Bit7 Bit0 Bit7 SCLK PB=1 PB=0 PB=1 PB=0 PB=1 PB=0 DR/DT=0 DR/DT=1 DR/DT=0 DR/DT=1 DR/DT=0 DR/DT=1 Synchronous Serial Port Multiple Read Rev:1.2 RDC Semiconductor Co. Subject to change without notice...
  • Page 70 R D C ® R8810LV RISC DSP Controller CLKOUTA SDEN SCLK SDATA(RX) DATA SDATA(TX) DATA Synchronous Serial Interface Waveforms Rev:1.2 RDC Semiconductor Co. Subject to change without notice...

  • Page 71: Pio Unit

    TMRIN0 Input with 10k pull-up DRQ0 Input with 10k pull-up DRQ1 Input with 10k pull-up Input with 10k pull-up Input with 10k pull-up Input with 10k pull-up Input with 10k pull-up Rev:1.2 RDC Semiconductor Co. Subject to change without notice...
  • Page 72 Set 1: Configure the PIO pin as an input. Set 0: Configure the PIO pin as an output or as normal pin function. Offset : 76h PIO Mode 1 Register Reset Value : 0000h PMODE (31 - 16) Rev:1.2 RDC Semiconductor Co. Subject to change without notice...
  • Page 73 Set 0: Configure the PIO pin as an output or as normal pin function. Offset : 70h PIO Mode 0 Register Reset Value : 0000h PMODE (15 - 0) Bit 15-0: PMODE15-PMODE0 , PIO Mode Bit. Rev:1.2 RDC Semiconductor Co. Subject to change without notice...

  • Page 74: Psram Control Unit

    Set 0 : Disable the refresh counter unit. Bit 14-9 : Reserved Bit 8-0: T8-T0, Refresh Count. Read only bits and these bits present value of the down counter which triggers refresh requests. Rev:1.2 RDC Semiconductor Co. Subject to change without notice...

  • Page 75: Instruction Set Opcodes And Clock Cycle

    ADD = Add reg/memory with register to either 000000dw mod reg r/m immediate to register/memory 100000sw mod 000 r/m data data if sw=01 immediate to accumulator 0000010w data data if w=1 Rev:1.2 RDC Semiconductor Co. Subject to change without notice...
  • Page 76 00100111 AAD = ASCII adjust for divide 11010101 00001010 AAM = ASCII adjust for multiply 11010100 00001010 CBW = Corrvert byte to word 10011000 CWD = Convert word to double-word 10011001 Rev:1.2 RDC Semiconductor Co. Subject to change without notice...
  • Page 77 /above or equal JNBE/JA = not below or equal/above 01110111 disp JNP/JPO = not parity/parity odd 01111011 disp JNO = not overflow 01110001 disp JNS = not sign 01111001 disp Rev:1.2 RDC Semiconductor Co. Subject to change without notice...
  • Page 78 WAIT = Wait 10011011 LOCK = Bus lock prefix 11110000 ESC = Math coprocessor escape 11011MMM mod PPP r/m NOP = No operation 10010000 SEGMENT OVERRIDE PREFIX 00101110 00110110 00111110 00100110 Rev:1.2 RDC Semiconductor Co. Subject to change without notice...

  • Page 79: R8810Lv Execution Timings

    ® R8810LV RISC DSP Controller R8810LV Execution Timings The above instruction timing represent the minimum execution time in clock cycles for each instruction. The timings given are based on the following assumptions: 1. The opcode, along with and data or displacement required for execution, has been prefetched and resides in the instruction queue at the time is needed.

  • Page 80: Dc Characteristics

    (for 32 Pio Pins) Vin=GND to Input Leakage Vcc=Vmax Current (Others) Vin=GND to Output Leakage Vcc=Vmax Current Vin=GND to Output Low Voltage Iol=2mA, _____ Vcc=Min. Output High V oltagr Ioh=-2.4mA, ____ Vcc=Min. Note1:Vmax=3.6V Vmin=3.0V Rev:1.2 RDC Semiconductor Co. Subject to change without notice...
  • Page 81 ® R8810LV RISC DSP Controller DC Electrical Characteristics Symbol Parameter Test condition Unit Note Max Operating Vcc=3.6V, Current 33MHz Fmax Max operation Vcc+-5% clock frequency Fmax Max operation Vcc+-10% clock frequency Rev:1.2 RDC Semiconductor Co. Subject to change without notice...

  • Page 82: Ac Characteristics

    R D C ® R8810LV RISC DSP Controller AC Characteristics CLKOUTA A19:A0 ADDRESS AD15:AD0 ADDRESS DATA UCS,LCS S2:S0 STATUS READ CYCLE Rev:1.2 RDC Semiconductor Co. Subject to change without notice...
  • Page 83 UZI inactive delay 1. T means a clock period time 2. All timing parameters are measured at 1.5V with 50 PF loading on CLKOUTA All output test conditions are with CL=50 pF Rev:1.2 RDC Semiconductor Co. Subject to change without notice...
  • Page 84 R D C ® R8810LV RISC DSP Controller CLKOUTA A19:A0 ADDRESS AD15:AD0 ADDRESS DATA WHB,WLB UCS,LCS S2:S0 STATUS WRITE CYCLE Rev:1.2 RDC Semiconductor Co. Subject to change without notice...
  • Page 85 PCS , MCS active delay PCS , MCS inactive delay DEN active delay DEN inactive delay active delay inactive delay Status active delay Status inactive delay UZI active delay UZI inactive delay Rev:1.2 RDC Semiconductor Co. Subject to change without notice...
  • Page 86 20000 101fc AD15:AD0 2211 2211 DT/R S2:S0 DRQ0 DMA (1) * The source-synchronized transfer is not followed immediately by another DMA transfer No. Description Unit DRQ is confirmed time Rev:1.2 RDC Semiconductor Co. Subject to change without notice...
  • Page 87 20000 C0002 20002 101fc AD15:AD0 2211 2211 4433 4433 DT/R S2:S0 DRQ0 DMA (2) * The source-synchronized transfer is followed immediately by another DMA transfer Description Unit DRQ is confirmed time Rev:1.2 RDC Semiconductor Co. Subject to change without notice...
  • Page 88 RISC DSP Controller CLKOUTA A19:A0 fff* f0000 ffff4 ffff6 zZZZZ AD15:AD0 fff6 fff6 DT/R S2:S0 HOLD HLDA HOLD/HLDA Timing Description Unit HOLD setup time HLDA Valid Delay HOLD hold time HLDA Valid Delay Rev:1.2 RDC Semiconductor Co. Subject to change without notice...
  • Page 89 R D C ® R8810LV RISC DSP Controller CLKOUTA ARDY SRDY ARDY Timing Description Unit ARDY Resolution Transition setup time ARDY active hold time Rev:1.2 RDC Semiconductor Co. Subject to change without notice...
  • Page 90 R D C ® R8810LV RISC DSP Controller CLKOUTA ARDY SRDY SRDY Timing Description Unit SRDY transition setup time SRDY transition hold time Rev:1.2 RDC Semiconductor Co. Subject to change without notice...

  • Page 91: Package Information

    RISC DSP Controller PACKAGE INFORMATION (PQFP) 23.20 0.25 D1 20.00 0.10 "A" 0.65 BSC SEATING PLANE 0.089 0.22/0.38 WITH PLATING 0.13/0.17 BASE 0.22/0.30/0.33 METAL 3.40 MAX 1.60 REF 0.25 0.88 0.15 DETAIL A Rev:1.2 RDC Semiconductor Co. Subject to change without notice...
  • Page 92 R D C ® R8810LV RISC DSP Controller (LQFP) 16.00 0.10 14.00 0.10 0.50(TYP) 0.22 0.05 "A" Sealing Plane 0.076(MAX) 0 ~ 7 0.60 0.15 1.00(REF) UNIT:mm Rev:1.2 RDC Semiconductor Co. Subject to change without notice...

  • Page 93: Revision History

    R D C ® R8810LV RISC DSP Controller Revision History Rev. Date History 2001/4/30 Formal release 2001/6/19 Address and Phone number update. 2001/8/15 Modify Wait State Description (Page 26) Rev:1.2 RDC Semiconductor Co. Subject to change without notice...

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