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Silicon Systems Silicon Drive SSD-P08G(I)-3521 Datasheet

Silicon systems pc card specification sheet
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O
VERVIEW
The SiliconDrive PC Card is an optimal
time-to-market
replacement
drives and flash cards or in host systems
that require low power and scalable
storage solutions.
SiliconDrive technology is engineered
exclusively for the high performance, high
reliability, and multiyear product lifecycle
requirements of the Enterprise System
OEM
market.
applications include broadband data and
voice networks, military systems, flight
system
avionics,
industrial
control
surveillance, storage networking, VoIP,
wireless infrastructure, and interactive
kiosks.
Every SiliconDrive is integrated with
SiliconSystems' PowerArmor technology
to virtually eliminate storage systems
failures.
PowerArmor prevents data corruption and
loss
from
power
integrating patented technology into every
SiliconDrive.
Numerous SiliconSystems' patented and
patent-pending
technologies
can
SiliconDrive to safeguard application data
and
software
IP.
detailing these performance-enhancing
options are available under NDA.
This document and the information contained within it is confidential and proprietary to SiliconSystems, Inc.
26840 A
V
P
, A
LISO
IEJO
ARKWAY
3521P-02DSR
for
hard
Typical
end-market
medical
equipment,
systems,
video
disturbances
application-specific
be
integrated
into
Application
notes
S
S
ILICON
YSTEMS
All unauthorized use and/or reproduction is prohibited.
•
V
, CA 92656
P
LISO
IEJO
HONE
D
S
ILICON
F
EATURES
• RoHS 6 of 6 compliant
• Integrated PowerArmor technology
• Capacity range: 32MB to 8GB
• Supports both 8-bit and 16-bit data
register transfers
• Supports dual-voltage 3.3V or 5V
interface
• Data reliability <1 error in 10
• MTBF 4,000,000 hours
• ATA-3 compliant
• Industry standard Type II PC Card form
factor
• Supports PIO modes 0-4
8GB
SSD-P08G(I)-3521
by
Click here
P
ROPRIETARY
•
: 949.900.9400
F
: 949.900.9500
AX
S
ATA
HEET
D
PC C
RIVE
SSD-P
(I)-3521
XXX
14
bits read
Click here
•
http://www.siliconsystems.com
F
EBRUARY
ARD
2, 2009

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Summary of Contents for Silicon Systems Silicon Drive SSD-P08G(I)-3521

  • Page 1 VERVIEW The SiliconDrive PC Card is an optimal time-to-market replacement drives and flash cards or in host systems that require low power and scalable storage solutions. SiliconDrive technology is engineered exclusively for the high performance, high reliability, and multiyear product lifecycle requirements of the Enterprise System market.

  • Page 2: Revision History

    EVISION ISTORY EVISION ISTORY Document No. Release Date 3521P-02DSR February 2, 2009 3521P-01DSR May 19, 2008 SSDS00-3521P-R March 12, 2008 This document and the information contained within it is confidential and proprietary to SiliconSystems, Inc. All unauthorized use and/or reproduction is prohibited. 3521P-02DSR Changes Updated:...

  • Page 3: Table Of Contents

    ABLE OF ONTENTS Overview ... i Features ... i Revision History... List of Figures ... List of Tables ... Physical Specifications ... 1 Physical Dimensions ... 1 Product Specifications ... 2 System Performance... 2 System Power Requirements... 2 Reliability ... 3 Projected Operational Life Span ...
  • Page 4 ABLE OF ONTENTS Attribute Memory Description and Operation ... 23 Attribute Memory Read Operations... 23 Attribute Memory Write Operations ... 24 Attribute Memory Map ... 25 Card Information Structure ... 26 Configuration Option Register (200h)... 37 Configuration and Status Register (202h) ... 38 Pin Placement Register (204h) ...
  • Page 5 ABLE OF ONTENTS Status Register... 54 Command Register ... 55 Alternate Status Register ... 56 Device Control Register ... 57 Device Address Register... 58 ATA Command Block and Set Description ... 59 ATA Command Set ... 59 Check Power Mode — 98h, E5h ... 61 Executive Drive Diagnostic —...
  • Page 6 ABLE OF ONTENTS Write DMA — CAh ... 85 Write Multiple — C5h ... 86 Write Sector(s) — 30h, 31h... 87 Write Long Sector(s) — 32h, 33h... 88 Erase Sector(s) — C0h ... 89 Request Sense — 03h ... 90 Translate Sector —...

  • Page 7: List Of Figures

    IST OF IGURES Figure 1: Physical Dimensions... 1 Figure 2: Attribute and Common Memory Read Timing Diagram... 17 Figure 3: Attribute and Common Memory Write Timing Diagram ... 18 Figure 4: I/O Access Read Timing Diagram ... 19 Figure 5: I/O Access Write Timing Diagram... 20 Figure 6: True IDE Read/Write Access Timing Diagram ...
  • Page 8 IST OF ABLES Table 1: System Performance ... 2 Table 2: System Power Requirements ... 2 Table 3: Reliability... 3 Table 4: Operational Life Span ... 3 Table 5: Product Capacity Specifications ... 4 Table 6: Environmental Specifications... 4 Table 7: Pin Assignments ... 5 Table 8: Signal Descriptions ...
  • Page 9 IST OF ABLES Table 28: I/O Space Read Operations... 42 Table 29: I/O Space Write Operations ... 42 Table 30: Memory-Mapped Register Decoding ... 43 Table 31: Independent I/O Mode Register Decoding... 44 Table 32: Primary and Secondary I/O Mapped Register Decoding ... 45 Table 33: Task File Register Specification...
  • Page 10 IST OF ABLES Table 57: Read Buffer — E4h... 72 Table 58: Read DMA — C8h ... 73 Table 59: Read Multiple — C4h... 74 Table 60: Read Sector — 20h, 21h ... 75 Table 61: Read Long Sector(s) — 22h, 23h ... 76 Table 62: Read Verify Sector(s) —...

  • Page 11: Physical Specifications

    HYSICAL PECIFICATIONS HYSICAL PECIFICATIONS The SiliconDrive PC Card products are offered in a Type II form factor. See "Part Numbering" on page 96 HYSICAL IMENSIONS This section provides diagrams that describe the physical dimensions for the PC Card. This document and the information contained within it is confidential and proprietary to SiliconSystems, Inc. All unauthorized use and/or reproduction is prohibited.

  • Page 12: Product Specifications

    RODUCT PECIFICATIONS RODUCT PECIFICATIONS Note: All SiliconDrive PC Card values quoted are typical at 25°C and nominal supply voltage. YSTEM ERFORMANCE Reset to Ready Startup Time (Typical/Maximum) Read Transfer Rate (Typical) Write Transfer Rate (Typical) Burst Transfer Rate Controller Overhead (Command to DRQ) YSTEM OWER EQUIREMENTS...

  • Page 13: Reliability

    RODUCT PECIFICATIONS ELIABILITY MTBF (@ 25ºC) Bit Error Rate ROJECTED PERATIONAL SiliconDrive Part# SSD-P08G-3521 SSD-P04G-3521 SSD-P02G-3521 SSD-P01G-3521 SSD-P51M-3521 SSD-P25M-3521 SSD-P12M-3521 SSD-P64M-3521 SSD-P32M-3521 * There are unlimited read cycles. Service life is determined using SiliconSystems’ LifeEst calculation at 100% duty cycle with 25% write cycles. LifeEst is a comprehensive measurement that considers numerous factors to determine the projected life span of a SiliconDrive.

  • Page 14: Product Capacity Specifications

    RODUCT PECIFICATIONS RODUCT APACITY Table 5: Product Capacity Specifications Product Capacity Capacity (Bytes) 32MB 32,702,464 64MB 65,601,536 128MB 130,154,496 256MB 260,571,136 512MB 521,773,056 1,047,674,880 2,098,446,336 4,224,761,856 8,455,200,768 * = All IDE drives 8GB and larger use 16383 cylinders, 16 heads, and 63 sectors/track due to interface restrictions.

  • Page 15: Electrical Specification

    LECTRICAL PECIFICATION LECTRICAL PECIFICATION SSIGNMENTS The following table describes the SiliconDrive PC Card 50-pin IDE connector signals. PC Card PC Card Memory I/O Mode Mode CE1# CE1# RDY/BSY# IREQ This document and the information contained within it is confidential and proprietary to SiliconSystems, Inc. All unauthorized use and/or reproduction is prohibited.
  • Page 16 LECTRICAL PECIFICATION PC Card PC Card Memory I/O Mode Mode IOIS16# Notes: NU = Not used These signals are required only for 16-bit access, and not required when installed in 8-bit systems. Should be grounded by the host. This document and the information contained within it is confidential and proprietary to SiliconSystems, Inc. All unauthorized use and/or reproduction is prohibited.

  • Page 17: Signal Descriptions

    LECTRICAL PECIFICATION IGNAL ESCRIPTIONS Signal Name A10-A0 A10-A0 (PC Card I/O mode) A2-A0 (True IDE mode) BVD1 (PC Card memory mode) -STSCHG (PC Card I/O mode) -PDIAG (True IDE mode) BVD2 (PC Card memory mode) This document and the information contained within it is confidential and proprietary to SiliconSystems, Inc. All unauthorized use and/or reproduction is prohibited.
  • Page 18 LECTRICAL PECIFICATION Table 8: Signal Descriptions (Continued) Signal Name -SPKR (PC Card I/O mode) -DASP (True IDE mode) -CD1, -CD2 (PC Card memory mode) -CD1, -CD2 (PC Card I/O Mode) -CD1, -CD2 (True IDE mode) -CE1, -CE2 (PC Card memory mode) Card Enable This document and the information contained within it is confidential and proprietary to SiliconSystems, Inc.
  • Page 19 LECTRICAL PECIFICATION Table 8: Signal Descriptions (Continued) Signal Name -CE1, -CE2 (PC Card I/O mode) Card Enable -CS0, -CS1 (True IDE mode) -CSEL (PC Card memory mode) -CSEL (PC Card I/O mode) -CSEL (True IDE mode) -INPACK (PC Card memory mode) -INPACK (PC Card I/O...
  • Page 20 LECTRICAL PECIFICATION Table 8: Signal Descriptions (Continued) Signal Name DMARQ (True IDE mode) D15-D00 (PC Card memory mode) D15-D00 (PC Card I/O mode) D15-D00 (True IDE mode) (PC Card memory mode) (PC Card I/O mode) (True IDE mode) This document and the information contained within it is confidential and proprietary to SiliconSystems, Inc. All unauthorized use and/or reproduction is prohibited.
  • Page 21 LECTRICAL PECIFICATION Table 8: Signal Descriptions (Continued) Signal Name -IORD (PC Card memory mode) -IORD (PC Card I/O mode) -IORD (True IDE mode) -IOWR (PC Card memory mode) -IOWR (PC Card I/O mode) -IOWR (True IDE mode) (PC Card memory mode) (PC Card I/O mode)
  • Page 22 LECTRICAL PECIFICATION Table 8: Signal Descriptions (Continued) Signal Name -ATA SEL (True IDE mode) -RDY/-BSY (PC Card memory mode) -IREQ (PC Card I/O mode) Input Acknowledge -IREQ (True IDE mode) This document and the information contained within it is confidential and proprietary to SiliconSystems, Inc. All unauthorized use and/or reproduction is prohibited.
  • Page 23 LECTRICAL PECIFICATION Table 8: Signal Descriptions (Continued) Signal Name -REG (PC Card memory mode) Attribute Memory Select -REG (PC Card I/O mode) -DMACK (True IDE mode) -RESET (PC Card memory mode) -RESET (PC Card I/O mode) -RESET (True IDE mode) (PC Card memory mode) This document and the information contained within it is confidential and proprietary to SiliconSystems, Inc.
  • Page 24 LECTRICAL PECIFICATION Table 8: Signal Descriptions (Continued) Signal Name (PC Card I/O mode) (True IDE mode) -VS1, -VS2 -VS1, -VS2 (PC Card I/O mode) -VS1, -VS2 (True IDE mode) -WAIT (PC Card memory mode) -WAIT (PC Card I/O mode) -IORDY (True IDE mode) (PC Card memory mode)

  • Page 25: Absolute Maximum Ratings

    LECTRICAL PECIFICATION Table 8: Signal Descriptions (Continued) Signal Name (True IDE mode) (PC Card memory mode) -IOIS16 (PC Card I/O mode) -IOIS16 (True IDE mode) BSOLUTE AXIMUM Symbol Parameter Storage Temperature Operating Temperature Input Voltage Output Voltage This document and the information contained within it is confidential and proprietary to SiliconSystems, Inc. All unauthorized use and/or reproduction is prohibited.

  • Page 26: Capacitance

    LECTRICAL PECIFICATION APACITANCE Symbol Parameter Input Capacitance Output Capacitance Bidirectional Capacitance DC C HARACTERISTICS Symbol Parameter Power Supply Voltage Input Leakage *(1) Current Output Leakage *(1) Current Read Current Write Current Standby Current Input Low Voltage Input High Voltage Output Low Voltage Output High Voltage...

  • Page 27: Ac Characteristics

    LECTRICAL PECIFICATION AC C HARACTERISTICS Attribute and Common Memory Read Timing ____ A[10::0],REG D[15::0] Figure 2: Attribute and Common Memory Read Timing Diagram Table 12: Attribute and Common Memory Read Timing Symbol Parameter Read Cycle Time Address Access Time (CE) Card Enable Access Time (OE) Output Enable Access Time...

  • Page 28: Attribute And Common Memory Write Timing

    LECTRICAL PECIFICATION Attribute and Common Memory Write Timing ____ A[10::0],REG D[15:0](Dout) D[15:0](Dout) Figure 3: Attribute and Common Memory Write Timing Diagram Table 13: Attribute and Common Memory Write Timing Symbol Parameter Write Cycle Time Write Pulse Width WLWH Address Setup Time AVWL Address Setup Time for WE AVWH...

  • Page 29: I/O Access Read Timing

    LECTRICAL PECIFICATION I/O Access Read Timing A[10::0] ____ IORD ______ INPACK ______ IOIS16 D[15::0] Figure 4: I/O Access Read Timing Diagram Symbol Parameter Data Delay after IORD DVRL Data Hold following IORD IGHQX IORD Pulse Width IGLIGH Address Setup before IORD AVIGL Address Hold following IORD GHAX...

  • Page 30: I/O Access Write Timing

    LECTRICAL PECIFICATION I/O Access Write Timing A[10::0] ____ _____ IOWR ______ IOIS16 D[15::0] Figure 5: I/O Access Write Timing Diagram Symbol Parameter Data Hold following IOWR IGHDX Data Setup before IOWR IGHQX IOWR Pulse Width IGLIGH Address Setup before IOWR AVIGL Address Hold following IOWR AXIGH...

  • Page 31: True Ide Read/Write Access Timing

    LECTRICAL PECIFICATION True IDE Read/Write Access Timing ADDRESS Valid CS0, CS1, DA[2::0] ____ _____ DIOR,DIOW WRITE DD[15::00] READ DD[15::00] IORDY ______ IOIS16 Figure 6: True IDE Read/Write Access Timing Diagram Table 16: True IDE Read/Write Access Timing Symbol Parameter Cycle Time Address Valid to DIOR,DIOW Setup Time AVRWL DIOR, DIOW Pulse Width...

  • Page 32: True Ide Multiword Dma Read/Write Access Timing

    LECTRICAL PECIFICATION True IDE Multiword DMA Read/Write Access Timing This function does not apply to SiliconDrives that have DMA disabled. Figure 7: True IDE Multiword DMA Read/Write Access Timing Table 17: True IDE Multiword DMA Read/Write Access Timing Symbol Parameter Cycle Time (mode 2) DIOR/DIOW Pulse Width RWPW...

  • Page 33: Attribute Memory Description And Operation

    TTRIBUTE EMORY ESCRIPTION AND TTRIBUTE EMORY The attribute memory plane can be read or written to by asserting the REG# signal, qualified by the appropriate combination of CE1#, OE#, and WE#. An attribute memory map describing the type and location of the information maintained in the attribute memory plane is provided in Map"...

  • Page 34: Attribute Memory Write Operations

    TTRIBUTE EMORY ESCRIPTION AND TTRIBUTE EMORY Attribute memory write operations are enabled by asserting REG#, WE#, and CE1# low. Odd byte write operations from the attribute memory plane are not valid. Table 19: Attribute Memory Write Operations Function REG# CE1# CE2# A0 Mode Standby Byte Access...

  • Page 35: Attribute Memory Map

    TTRIBUTE EMORY ESCRIPTION AND TTRIBUTE EMORY As stated earlier, the Attribute Memory plane is comprised of two components, the CIS and the FCRs. The following tables detail the type, location, and read/ write requirements for each of the four FCRs maintained in the attribute memory plane.

  • Page 36: Card Information Structure

    TTRIBUTE EMORY ESCRIPTION AND NFORMATION The CIS is data that describes the SiliconDrive CF, and is described by the CFA standard. This information can be used by the host system to determine a number of things about the Card that has been inserted. For information regarding the exact nature of this data and how to design the host software to interpret it, refer to the PC Card Standard Metaformat Specification.

  • Page 37: Silicon Systems Proprietary

    TTRIBUTE EMORY ESCRIPTION AND Table 21: Card Information Structure (Continued) Attribute Data Offset TPLFID_FUNCTION = 04H Reserved Disk Function Extension Tuple Type Disk interface type Disk Function Extension Tuple Type Basic PCMCIA-ATA extension tuple Reserved TPCC_RADR (MSB) Reserved CISTPL_TABLE_ENTRY This document and the information contained within it is confidential and proprietary to SiliconSystems, Inc. All unauthorized use and/or reproduction is prohibited.
  • Page 38 TTRIBUTE EMORY ESCRIPTION AND Table 21: Card Information Structure (Continued) Attribute Data Offset M MS IR Mantissa Mantissa Mantissa Length in 256 bytes pages (LSB) Length in 256 bytes pages (MSB) Length of memory space is 2KB CISTPL_TABLE_ENTRY This document and the information contained within it is confidential and proprietary to SiliconSystems, Inc. All unauthorized use and/or reproduction is prohibited.
  • Page 39 TTRIBUTE EMORY ESCRIPTION AND Table 21: Card Information Structure (Continued) Attribute Data Offset M MS IR Mantissa Mantissa CISTPL_TABLE_ENTRY D Configuration M MS IR This document and the information contained within it is confidential and proprietary to SiliconSystems, Inc. All unauthorized use and/or reproduction is prohibited. 3521P-02DSR PERATION 0 Description of Contents...
  • Page 40 TTRIBUTE EMORY ESCRIPTION AND Table 21: Card Information Structure (Continued) Attribute Data Offset Mantissa Mantissa Mantissa Mantissa 15 14 13 12 11 10 CISTPL__TABLE_ENTRY This document and the information contained within it is confidential and proprietary to SiliconSystems, Inc. All unauthorized use and/or reproduction is prohibited. 3521P-02DSR PERATION 0 Description of Contents...
  • Page 41 TTRIBUTE EMORY ESCRIPTION AND Table 21: Card Information Structure (Continued) Attribute Data Offset M MS IR Mantissa Mantissa Mantissa CISTPL_TABLE_ENTRY M MS IR This document and the information contained within it is confidential and proprietary to SiliconSystems, Inc. All unauthorized use and/or reproduction is prohibited. 3521P-02DSR PERATION 0 Description of Contents...
  • Page 42 TTRIBUTE EMORY ESCRIPTION AND Table 21: Card Information Structure (Continued) Attribute Data Offset Mantissa Mantissa Mantissa Mantissa LS AS First I/0 Base Address First I/0 Base Address First I/0 Base Address Second I/O Base Address Second I/O Base Address Second I/O Range Length CISTPL_TABLE_ENTRY This document and the information contained within it is confidential and proprietary to SiliconSystems, Inc.

  • Page 43: 3521P-02Dsr Age

    TTRIBUTE EMORY ESCRIPTION AND Table 21: Card Information Structure (Continued) Attribute Data Offset M MS IR Mantissa CISTPL_TABLE_ENTRY M MS IR M MS IR This document and the information contained within it is confidential and proprietary to SiliconSystems, Inc. All unauthorized use and/or reproduction is prohibited. 3521P-02DSR PERATION 0 Description of Contents...
  • Page 44 TTRIBUTE EMORY ESCRIPTION AND Table 21: Card Information Structure (Continued) Attribute Data Offset Mantissa Mantissa Mantissa Mantissa LS AS 100h 102h 104h 106h 108h 10Ah CISTPL_TABLE_ENTRY 10Ch This document and the information contained within it is confidential and proprietary to SiliconSystems, Inc. All unauthorized use and/or reproduction is prohibited.
  • Page 45 TTRIBUTE EMORY ESCRIPTION AND Table 21: Card Information Structure (Continued) Attribute Data Offset 10Eh 110h M MS IR 112h 114h Mantissa 116h 118h Mantissa 11Ah 11Ch 11Eh 120h M MS IR 122h 124h 126h 128h 12Ah 12Ch 12Eh 130h 132h 134h 136h 138h...
  • Page 46 TTRIBUTE EMORY ESCRIPTION AND Table 21: Card Information Structure (Continued) Attribute Data Offset 13Ch 13Eh 140h 142h 144h 146h 14Ah 14Ch 14Eh 150h 152h 154h 156h 158h 15Ah 15Ch 160h This document and the information contained within it is confidential and proprietary to SiliconSystems, Inc. All unauthorized use and/or reproduction is prohibited.

  • Page 47: Configuration Option Register (200H)

    TTRIBUTE EMORY ESCRIPTION AND ONFIGURATION PTION The Configuration Option register is used to configure the SiliconDrive CF, define the address decoding, and initiate the software RESET sequence. Table 22: Configuration Option Register (200h) Operation Read/ SRESET LevIREQ Write Default Value Bit(s) Description SRESET...

  • Page 48: Configuration And Status Register (202H)

    TTRIBUTE EMORY ESCRIPTION AND ONFIGURATION AND The Configuration and Status Register (CSR) informs the host of any status changes with regard to power-down. Table 23: Configuration and Status Register (202h) Operation Read Changed SigChg IOis8 Write Changed SigChg IOis8 Default Value Bit(s) Description...

  • Page 49: Pin Placement Register (204H)

    TTRIBUTE EMORY ESCRIPTION AND LACEMENT EGISTER Operation Read/ CBVD1 CBVD2 CRDY CWProt RBVD1 RBVD2 RRDY RWProt Write Default Value Bit(s) Description CRDY Indicates a bit change in the RRDY (D1) bit. CWProt Indicates a bit change in the RWProt (D0) bit. RRDY When set: •...

  • Page 50: Socket And Copy Register (206H)

    TTRIBUTE EMORY ESCRIPTION AND OCKET AND Table 25: Socket and Copy Register (206h) Operation Read/Write Default Value Bit(s) Description Reserved for future use. Copy Indicates the card number. Allows the host to differentiate Number between identical cards by writing to the bit of the card that is being accessed.

  • Page 51: Common Memory Description And Operation

    OMMON EMORY ESCRIPTION AND OMMON EMORY ESCRIPTION AND Common memory space can be accessed when the SiliconDrive is configured in memory-mapped mode. OMMON EMORY Common memory read operations are issued by asserting CE1#, CE2#, or both, and OE# low, REG#, and WE# must be inactive. Table 26: Common Memory Read Operations Function Mode REG# CE1# CE2# A0 OE# Standby...

  • Page 52: I/O Space Description And Operation

    I/O S PACE ESCRIPTION AND I/O S PACE ESCRIPTION AND I/O S PACE PERATIONS Function Mode REG# CE1# CE2# A0 IORD# IOWR# D[15:8] D[7:0] Standby Byte Access Word Access I/O Inhibit Odd Byte Only Access I/O S PACE RITE PERATIONS Function Mode REG# CE1# CE2# A0 IORD# IOWR# D[15:8] D[7:0] Standby Byte Access...

  • Page 53: Ata And True Ide Register Decoding

    IDE R EGISTER IDE R SiliconDrive can be configured as either a a memory-mapped or an an I/O devices. As noted earlier, communication to and from the drive is accomplished using the ATA Command Block. EMORY APPED EGISTER In memory-mapped mode, the SiliconDrive registers are accessed via standard memory references (i.e., OE# and WE#).

  • Page 54: Independent I/O Mode Register Decoding

    IDE R EGISTER I/O M NDEPENDENT Independent I/O mode or contiguous I/O mode requires the host to decode a continuous block of 16 I/O registers to select the SiliconDrive. Table 31: Independent I/O Mode Register Decoding Reg# Offset A10 A9:A4 A3 A2 A1 A0 OE# = L This document and the information contained within it is confidential and proprietary to SiliconSystems, Inc.

  • Page 55: Primary And Secondary I/O Mapped Register Decoding

    IDE R EGISTER RIMARY AND ECONDARY Table 32: Primary and Secondary I/O Mapped Register Decoding A9:A4 Reg# A10 Primary 1Fxh 1Fxh 1Fxh 1Fxh 1Fxh 1Fxh 1Fxh 1Fxh 3Fxh 3Fxh This document and the information contained within it is confidential and proprietary to SiliconSystems, Inc. All unauthorized use and/or reproduction is prohibited.

  • Page 56: Task File Register Specification

    IDE R EGISTER EGISTER The Task File registers are used for reading and writing the storage data in the SiliconDrive. The decoded addresses are as shown in the following table. Table 33: Task File Register Specification CS0# CS1# This document and the information contained within it is confidential and proprietary to SiliconSystems, Inc. All unauthorized use and/or reproduction is prohibited.

  • Page 57: Ata Registers

    ATA R EGISTERS ATA R EGISTERS EGISTER The Data register is a 16-bit register used to transfer data blocks between the host and drive buffers. The register may set to 8-bit mode by using the Set Features Command defined in RROR EGISTER The Error register contains the error status, if any, generated from the last...

  • Page 58: Feature Register

    ATA R EGISTERS EATURE EGISTER The Feature register is command-specific and used to enable and disable interface features. This register supports only either odd or even byte data transfers. Operation Read/Write This document and the information contained within it is confidential and proprietary to SiliconSystems, Inc. All unauthorized use and/or reproduction is prohibited.

  • Page 59: Sector Count Register

    ATA R EGISTERS ECTOR OUNT EGISTER The Sector Count register is used to read or write the sector count of the data for which an ATA transfer has been made. Operation Read/Write Default Value This document and the information contained within it is confidential and proprietary to SiliconSystems, Inc. All unauthorized use and/or reproduction is prohibited.

  • Page 60: Sector Number Register

    ATA R EGISTERS ECTOR UMBER EGISTER The Sector Number register is set by the host to specify the starting sector number associated with the next ATA command to be executed. Following a qualified ATA command sequence, the device sets the register value to the last sector read or written as a result of the previous AT command.

  • Page 61: Cylinder Low Register

    ATA R EGISTERS YLINDER EGISTER The Cylinder Low register is set by the host to specify the cylinder number low byte. Following an ATA command, the content of the register is written by the device, identifying the cylinder number low byte. In LBA mode, the 8-bit register maintains the contents of the Logical Block number address bits A15:A08.

  • Page 62: Cylinder High Register

    ATA R EGISTERS YLINDER EGISTER The Cylinder High register is set by the host to specify the cylinder number high byte. Following an ATA command, the content of the register is set internally by the device, identifying the cylinder number high byte. In LBA mode, the 8-bit register maintains the contents of the Logical Block number address bits A23:A16.

  • Page 63: Drive/Head Register

    ATA R EGISTERS RIVE EGISTER The Drive/Head register is used by the host and the device to select the type of addressing (CHS or LBA), the drive letter, and either bits 3-0 of the head number in CHS mode or logical block number bits 27-24 in LBA mode. Operation Read/Write Default...

  • Page 64: Status Register

    ATA R EGISTERS TATUS EGISTER The Status register provides the device’s current status to the host. The status register is an 8-bit read-only register. When the contents of the register are read by the host, the IREQ# bit is cleared. Operation Read/Write Default Value...

  • Page 65: Command Register

    ATA R EGISTERS OMMAND EGISTER The Command register specifies the ATA command code being issued to the drive by the host. Execution of the command begins immediately following the issuance of the command register code by the host. Operation Read/Write "ATA Command Block and Set Description"...

  • Page 66: Alternate Status Register

    ATA R EGISTERS LTERNATE TATUS The Alternate Status register is a read-only register indicating the status of the device, following the previous ATA command. See for specific details. Operation Read/Write Default Value This document and the information contained within it is confidential and proprietary to SiliconSystems, Inc. All unauthorized use and/or reproduction is prohibited.

  • Page 67: Device Control Register

    ATA R EGISTERS EVICE ONTROL EGISTER The Device Control register is used to control the interrupt request and issue ATA software resets. Operation Write Bit(s) Description Reserved bits. Always set to 1. Software Reset (SRST). When set, resets the ATA software. Interrupt Enable (nIEN).

  • Page 68: Device Address Register

    ATA R EGISTERS EVICE DDRESS EGISTER The Device Address register is used to maintain compatibility with ATA disk drive interfaces. Operation Read/Write Default Value Bit(s) Description Reserved bit. Write Gate (nWTG). Low when a write to the device is in process. nHS3 to nHS0.

  • Page 69: Ata Command Block And Set Description

    ATA C OMMAND LOCK AND ATA C OMMAND LOCK AND In accordance with the ANSI ATA Specification, the device implements seven registers that are used to transfer instructions to the device by the host. These commands follow the ANSI standard ATA protocol. A description of the ATA command block is provided in the following table.
  • Page 70 ATA C OMMAND LOCK AND Table 47: ATA Command Set (Continued) Class Command Name Read Long Sector Read Sector(s) Read Verify Sector(s) 40h, 41h Recalibrate Request Sense Seek Set Features Set Multiple Mode Set Sleep Mode Standby Standby Immediate Translate Sector Wear Level Write Buffer Write DMA*...

  • Page 71: Check Power Mode - 98H, E5H

    ATA C OMMAND LOCK AND Check Power Mode — 98h, E5h The Check Power Mode command verifies the device’s current power mode. When the device is configured for standby mode or is entering or exiting standby, the BSY bit is set, the Sector Count register set to 00h, and the BSY bit is cleared.

  • Page 72: Executive Drive Diagnostic - 90H

    ATA C OMMAND LOCK AND Executive Drive Diagnostic — 90h The Executive Drive Diagnostic performs an internal read write diagnostic test using (AA55h and 55AAh). If an error is detected in the read/write buffer, the Error register reports the appropriate diagnostic code. Table 49: Executive Drive Diagnostic —...

  • Page 73: Format Track - 50H

    ATA C OMMAND LOCK AND Format Track — 50h The Format Track command formats the common solid-state memory array. Register Feature Sector Count Sector Number Cylinder Low Cylinder High Drive Head Command This document and the information contained within it is confidential and proprietary to SiliconSystems, Inc. All unauthorized use and/or reproduction is prohibited.

  • Page 74: Identify Drive - Ech

    ATA C OMMAND LOCK AND Identify Drive — ECh Issued by the host, the Identify Drive command provides 256 bytes of drive attribute data (i.e., sector size, count, and so on) The identify drive data structure is detailed in the following table. Register Feature Sector Count...

  • Page 75: Identify Drive - Drive Attribute Data

    ATA C OMMAND LOCK AND Identify Drive — Drive Attribute Data Table 52: Identify Drive — Drive Attribute Data Word Data Default Address 044Ah (fixed ID bit) in IDE mode XXXXh 0000h 00XXh 0000h XXXXh XXXXh XXXXh 0000h 10-19 XXXXh This document and the information contained within it is confidential and proprietary to SiliconSystems, Inc.
  • Page 76 ATA C OMMAND LOCK AND Table 52: Identify Drive — Drive Attribute Data (Continued) Word Data Default Address 0002h 0002h 0004h 23-26 XXXXh 27-46 XXXXh 0001h 0000h 0002h 0000h 0100h 0000h 0000h XXXXh XXXXh XXXXh 57-58 XXXXh 010Xh 60-61 XXXXh 0000h This document and the information contained within it is confidential and proprietary to SiliconSystems, Inc.
  • Page 77 ATA C OMMAND LOCK AND Table 52: Identify Drive — Drive Attribute Data (Continued) Word Data Default Address 0407h 0003h 0078h 0078h 0078h 0078h 69-127 0000h 128-159 0000h 160-255 0000h This document and the information contained within it is confidential and proprietary to SiliconSystems, Inc. All unauthorized use and/or reproduction is prohibited.

  • Page 78: Idle - 97H, E3H

    ATA C OMMAND LOCK AND Idle — 97h, E3h When issued by the host, the device’s internal controller sets the BSY bit, enters the Idle mode, clears the BSY bit, and generates an interrupt. If the sector count is non-zero, it is interpreted as a timer count with each count being 5ms, and the automatic power-down mode is enabled.

  • Page 79: Idle Immediate - 95H, E1H

    ATA C OMMAND LOCK AND Idle Immediate — 95h, E1h When issued by the host, the device’s internal controller sets the BSY bit, enters Idle Mode, clears the BSY bit, and issues an interrupt. The interrupt is issued whether or not the Idle mode is fully entered. Register Feature Sector Count...

  • Page 80: Initialize Drive Parameters - 91H

    ATA C OMMAND LOCK AND Initialize Drive Parameters — 91h Initialize Drive Parameters allows the host to set the sector counts per track and the head counts per cylinder to 1 Fixed. Upon issuance of the command, the device sets the BSY bit and associated parameters, clears the BSY bit, and issues an interrupt.

  • Page 81: Recalibrate - 1Xh

    ATA C OMMAND LOCK AND Recalibrate — 1Xh The Recalibrate command sets the cylinder low and high, head number to 0h, and sector number to 1h in CHS mode. In LBA mode (i.e., LBA = 1), the sector number is set to 0h. Register Feature Sector Count...

  • Page 82: Read Buffer - E4H

    ATA C OMMAND LOCK AND Read Buffer — E4h The Read Buffer command allows the host to read the contents of the sector buffer. When issued, the device sets the BSY bit and sets up the sector buffer data in preparation for the read operation. When the data is ready, the DRQ bit is set and the BSY bit in the Status register are set and cleared, respectively.

  • Page 83: Read Dma - C8H

    ATA C OMMAND LOCK AND Read DMA — C8h The Read DMA command allows the host to read data using the DMA transfer protocol. Note: This function does not apply to SiliconDrives that have DMA disabled. Register Feature Sector Count Sector Number Cylinder Low Cylinder High...

  • Page 84: Read Multiple - C4H

    ATA C OMMAND LOCK AND Read Multiple — C4h The Read Multiple command executes similarly to the Read Sector command, with the exception that interrupts are issued only when a block containing the counts of sectors defined by the Set Multiple command is transferred. Register Feature Sector Count...

  • Page 85: Read Sector - 20H, 21H

    ATA C OMMAND LOCK AND Read Sector — 20h, 21h The Read Sector command allows the host to read sectors 1 to 256 as specified in the Sector Count register. If the sector count is set to 0h, all 256 sectors of data are made available.

  • Page 86: Read Long Sector(S) - 22H, 23H

    ATA C OMMAND LOCK AND Read Long Sector(s) — 22h, 23h The Read Long Sector(s) command operates similarly to the Read Sector(s) command, with the exception that it transfers requested data sectors and ECC data. The long instruction ECC byte transfer for Long commands is a byte transfer at a fixed length of 4 bytes.

  • Page 87: Read Verify Sector(S) - 40H, 41H

    ATA C OMMAND LOCK AND Read Verify Sector(s) — 40h, 41h The Read Verify Sector(s) command operates similarly to the Read Sector(s) command, with the exception that is does not set the DRQ bit and does not transfer data to the host. When the requested sectors are verified, the onboard controller clears the BSY bit and issues an interrupt.

  • Page 88: Seek - 7Xh

    ATA C OMMAND LOCK AND Seek — 7Xh The Seek command seeks and picks up the head to the tracks specified in the task file. When the command is issued, the solid-state memory chips do not need to be formatted. After an appropriate amount of time, the DSC bit is set. Register Feature Sector Count...

  • Page 89: Set Features - Efh

    ATA C OMMAND LOCK AND Set Features — EFh The Set Features command allows the host to configure the feature set of the device according to the attributes listed in Register Feature Sector Count Sector Number Cylinder Low Cylinder High Drive Head Command Feature...

  • Page 90: Set Multiple Mode - C6H

    ATA C OMMAND LOCK AND Set Multiple Mode — C6h The Set Multiple Mode command allows the host to access the drive via Read Multiple and Write Multiple ATA commands. Additionally, the command sets the block count (i.e., the number of sectors within the block) for the Read/Write Multiple command.

  • Page 91: Set Sleep Mode - 99H, E6H

    ATA C OMMAND LOCK AND Set Sleep Mode — 99h, E6h The Set Sleep Mode command allows the host to set the device in sleep mode. When the onboard controller transitions to sleep mode, it clears the BSY bit and issues an interrupt. The device interface then becomes inactive. Sleep mode can be exited by issuing either a hardware or software reset.

  • Page 92: Standby - 96H, E2H

    ATA C OMMAND LOCK AND Standby — 96h, E2h When the Standby command is issued by the host, it transitions the device into standby mode. If the Sector Count register is set to a value other than 0h, the Auto Powerdown function is enabled and the device returns to Idle mode. Register Feature Sector Count...

  • Page 93: Standby Immediate - 94H, E0H

    ATA C OMMAND LOCK AND Standby Immediate — 94h, E0h When the Standby Immediate command is issued by the host, it transitions the device into standby mode. Table 69: Standby Immediate — 94h, E0h Register Feature Sector Count Sector Number Cylinder Low Cylinder High Drive Head...

  • Page 94: Write Buffer - E8H

    ATA C OMMAND LOCK AND Write Buffer — E8h The Write Buffer command allows the host to rewrite the contents of the 512- byte data buffer with the wanted data. Register Feature Sector Count Sector Number Cylinder Low Cylinder High Drive Head Command This document and the information contained within it is confidential and proprietary to SiliconSystems, Inc.

  • Page 95: Write Dma - Cah

    ATA C OMMAND LOCK AND Write DMA — CAh The Write DMA command allows the host to write data using the DMA transfer protocol. Note: This function does not apply to SiliconDrives that have DMA disabled. Register Feature Sector Count Sector Number Cylinder Low Cylinder High...

  • Page 96: Write Multiple - C5H

    ATA C OMMAND LOCK AND Write Multiple — C5h The Write Multiple command operates in the same manner as the Write Sector command. When issued, the device sets the BSY bit within 400ns and generates an interrupt at the completion of a transferred block of sectors. The DRQ bit is set at the beginning of a block transfer.

  • Page 97: Write Sector(S) - 30H, 31H

    ATA C OMMAND LOCK AND Write Sector(s) — 30h, 31h The Write Sector(s) command writes from 1 to 256 sectors as specified in the Sector Count register. A sector count of 0 requests 256 sectors. When issued, the device sets the BSY bit within 400ns and generates an interrupt at the completion of a transferred block of sectors.

  • Page 98: Write Long Sector(S) - 32H, 33H

    ATA C OMMAND LOCK AND Write Long Sector(s) — 32h, 33h The Write Long Sector(s) command operates in the same manner as the Write Sector command — when issued, the device sets the BSY bit within 400ns and generates an interrupt at the completion of a transferred block of sectors. The DRQ bit is set at the beginning of a block transfer.

  • Page 99: Erase Sector(S) - C0H

    ATA C OMMAND LOCK AND Erase Sector(s) — C0h The Erase Sector(s) command is issued prior to the issuance of a Write Sector(s) or Write Multiple w/o Erase command. Register Feature Sector Count Sector Number Cylinder Low Cylinder High Drive Head Command This document and the information contained within it is confidential and proprietary to SiliconSystems, Inc.

  • Page 100: Request Sense - 03H

    ATA C OMMAND LOCK AND Request Sense — 03h The Request Sense command identifies the extended error codes generated by the preceding ATA command. The Request Sense command must be issued immediately following the detection of an error via the Error register. Register Feature Sector Count...

  • Page 101: Translate Sector - 87H

    ATA C OMMAND LOCK AND Translate Sector — 87h The Translate Sector command is not currently supported by the SiliconSystems’ SiliconDrive. If the host issues this command, the device responds with 0x00h in the data register. Register Feature Sector Count Sector Number Cylinder Low Cylinder High...

  • Page 102: Wear-Level - F5H

    ATA C OMMAND LOCK AND Wear-Level — F5h The Wear-Level command is supported as an NOP command for the purposes of backward compatibility with the ANSI AT attachment standard. This command sets the Sector Count register to 0x00h. Register Feature Sector Count Sector Number Cylinder Low...

  • Page 103: Write Multiple W/O Erase - Cdh

    ATA C OMMAND LOCK AND Write Multiple w/o Erase — CDh The Write Multiple w/o Erase command functions identically to the Write Multiple command, with the exception that the implied pre-erase (i.e., Erase Sector(s) command) is not issued prior to writing the sectors. Table 80: Write Multiple w/o Erase —...

  • Page 104: Write Sector(S) W/O Erase - 38H

    ATA C OMMAND LOCK AND Write Sector(s) w/o Erase — 38h The Write Sector(s) w/o Erase command functions similar to the Write Sector command, with the exception that the implied pre-erase (i.e., Erase Sector(s) command) is not issued prior to writing the sectors. Table 81: Write Sector(s) w/o Erase —...

  • Page 105: Write Verify - 3Ch

    ATA C OMMAND LOCK AND Write Verify — 3Ch The Write Verify command verifies each sector immediately after it is written. This command performs identically to the Write Sector(s) command, with the added feature of verifying each sector written. Register Feature Sector Count Sector Number...

  • Page 106: Sales And Support

    ALES AND UPPORT ALES AND UPPORT To order or obtain information on pricing and delivery, contact your SiliconSystems Sales Representative. UMBERING OMENCLATURE The following table defines the SiliconDrive PC Card part numbering scheme. SSD- Form Factor: • C = CF •...

  • Page 107: Part Numbers

    UMBERING UMBERS The following table lists the SiliconDrive’s part numbers. Part Number SSD-P08G(I)-3521 SSD-P04G(I)-3521 SSD-P02G(I)-3521 SSD-P01G(I)-3521 SSD-P51M(I)-3521 SSD-P25M(I)-3521 SSD-P12M(I)-3521 SSD-P64M(I)-3521 SSD-P32M(I)-3521 HS 6 RODUCT The Pb-free identification label indicates that the enclosed components/ devices and/or assemblies do not contain any lead (i.e., they are lead-free, as defined in RoHS directive 2002/95/ED).

  • Page 108: Sample Label

    UMBERING AMPLE ABEL Front Label SSD-P08G(I)-3521 This document and the information contained within it is confidential and proprietary to SiliconSystems, Inc. All unauthorized use and/or reproduction is prohibited. 3521P-02DSR Standard Back Label with Figure 8: Sample Label ILICON YSTEMS ROPRIETARY SSD-P (I)-3521 D HEET...

  • Page 109: Related Documentation

    ELATED OCUMENTATION ELATED OCUMENTATION For more information, visit SiliconSystems Sales Representative. SiliconDrive Application-Specific Technology PowerArmor SiliconSystems' performance tests, ratings, and product specifications are measured using specific computer systems and/or components and reflect the approximate performance of SiliconSystems’ products as measured by those tests. Any difference in system hardware or software design or configuration, as well as system use, may affect actual test results, ratings, and product specifications.

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