Perpendicular Magnetic Recording (Pmr); System-On-Chip (Soc); Command Transport (Sct) - Western Digital Blue WD20SPZX Technical Reference Manual

secondary drive. WD Align software aligns partitions on the Advanced Format drive
to ensure it provides full performance for certain configurations.
3.3

Perpendicular Magnetic Recording (PMR)

In perpendicular magnetic recording (PMR), the magnetization of each data bit is
aligned vertically to the spinning disk, rather than longitudinally as has been the case
in hard drive technology for decades. In longitudinal recording, as the bits become
smaller and closer together, they experience an increasing demagnetizing field, much
like two bar magnets that are placed end-to-end repel one another. A property of the
media called coercivity must be increased to counteract the demagnetization to keep
the bits stable under thermal fluctuations; otherwise data corruption may occur over
time. Higher media coercivity has pushed the recording head write field to the limit of
known materials.
In perpendicular recording, the adjacent bits attract instead of repel (as with bar
magnets placed side by side,) creating more thermally stable bits. In addition, the
media contains a magnetically soft underlayer (SUL) beneath the recording layer. This
SUL allows a larger effective write field, thus higher coercivity media, enabling further
increases in density. Lastly, because of the vertical orientation of the bits, the PMR
recording layer tends to be thicker than that used for longitudinal recording,
providing increased signal for the read heads. All of these benefits enable WD
engineers to reliably pack more data on a given disk than is possible with
conventional longitudinal recording.
3.4

System-on-Chip (SOC)

The System-on-Chip (SOC) is the foundation for WD's next generation electronics and
firmware architecture. The native SATA SOC lowers component count by integrating
a hard disk controller, high performance processor, high speed execution SRAM, and
read channel in a 172-pin package. The processor has a 5-stage pipeline which can
execute instructions in a single cycle and a DSP engine for enhanced operations. The
SOC has on-chip tightly coupled memory for high speed code and data execution
that maximizes the processing bandwidth for timing critical operations. It has a high
performance disk controller that incorporates maximum flexibility, modularity,
performance, and low power consumption. The read/write channel has advanced
detection capabilities for high-density drives.
3.5 S.M.A.R.T. Command Transport (SCT)
The SCT Command Transport feature set provides a method for a host to send
commands and data to a device and for a device to send data and status to a host
using log pages. Standard ATA commands may be interspersed with SCT commands,
but SCT commands cannot be nested. SCT commands that do not require a
subsequent data transfer operation are not interspersed with any ATA commands or
each other.
This capability is used to pass commands through a driver interface or a bridge where
new or unknown commands may be filtered and not passed to the drive. SCT is also
used for issuing commands that require more than 8 parameter bytes. ATA8-ACS
provides detailed information on the usage and capabilities of SCT. The SCT feature
set includes the following commands:
Product Features
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