Peripheral Interface - Roland MicroComposer MC-4 Service Notes

MC-4
JAN
.13,1982
{Top Vitfw)
^PD7S0
C/D-(
8
BIT
MICROPROCESSOR
1}
CPU AKD
5T^5TEH
CONTROL
SIGNALS
ADDRESS BUS
A14, A15
Used to
select the follt>-wing
memory blocks through
respeotive Address Decoders.
Address Decoder
IC60'
IClOj IC12
1024, 1025
Memory
TO'52-1036
ROKq on
CPU Board
IC1-IC8, RJU^s
on
CKf Board
IC1-IC8, IG16-I023
SJffls
on
HAM Board
A0^A7
Used
to select 1/0 DeYices
through Port Addresa Decoder
1C57 on CPU Board. (See I/O MAP right)
1029\10]
D/A,
MODE LED Display, DIH OUT,
A/D
IN,
Clock Out,
^-^
CYCLE 3W IN
IQ5o[40)
Timing Signals generation, -Total
Time
measurement
IC58r77ri
Key Scanning,
Dot Display, iXIetronome,
Mode sw IN,
i^
DIN IN
Tiie
numbers
|4ol
,
[60|
and
[to]
above, also
shown
in
the^CHj
circuit
diagWn,
We
abbreviated
J/0 divice numbers ±n hex,
to
be
represented on
address bus, that is x
x
4
x,
iC
x
b
x
a:id
X X 7 X.
If bits 0111
(7)
appear
on A7-A4, IG57 selects
IC29.
Then bits on
Al-AO will
cause one ot the
following
in
IC29 to
be selected; 00-Port A,
01-Port B,
10-Port
and 11^
Control Word Register.
Similarly, if
0100
(4)
are on A7-A4, IG57 selects
IG30, and
00
on Al-AO Counter
0.
^PD8255C
PROGRAMMABLE
PERIPHERAL INTERFACE
2A
Programmable
WO
Pins
BASIC
OPERATION
APDS253C-5
PROGRAMMABLE IMTEflVAL
TIMER
3
Ind«p«nden1 16-Blt
Counters
SND
d
pc(**Qi
PCo-{i±
PCi**[i5
pci-*!
PCs*-
EI
PBi**[i|
PB2'
*PAl
:l]«PB.s
1/0
mr
40
IC50
8253
'jO
EXT
MTR-100
60
IC5S
8255
70
IC29
8255
DATA BUS
Used
to
transfer Instructions and Data to/from
l/O
Devices and
HAJ4s,
4MHs,
square Clock signal derived from devide-by-2
divider ICIS
^
An
HO
WH
S
INPUT OPERATION
[REAOl
t
1
D POFIT
A-DATABUS
r>
\ 1
POfiTB-OATA&US
1
1
1
PORT C-CJATA BUS
OUTPUT
OPE BAT! PN
WRITE]
n
1
a
tJATABUS-PORT A
f>
;
1
DATA BUS
-
PORT B
\
1
DATA BUS- PORT
C
1
1
a
DATA
PUS -fCONTROt
DISABLE
FUMCnON
X
X x X
I
DATA BUS- J-STATE
1 t 1
ILLEGAL CONDITION
x:
X
1 1
Q
DATA
BUS-
J-STATE
D,
^
D,
»
D,
*
Do*
CLKO
»
OUTO*
GATE '
GNDo
<-
2*
2S
21
10
19
1&
P
17
IS
ID
I]
14
13 13
.,
*o
A;
A.
CLK2
OUT
2
GATE
2
«
CLKl
CATEl
In
the
MCA
B25&C
operates in
MODE
and
8253
in different
MODEs.
ED
¥R
IHT
NMI
VIAIT
Ml
RESET
cs
RD WH
At
Ad
1
toadCouniBrNo.O
B \
(.Mci
CoumsF
No. 1
1
D
1
Load Counter No. 7
1
»
VJfilt
Mode Word
1 CI
RmiJ
Coumer
No,
1
Read Cojrbter Nd,
1
n
} 1
Read
Coumer No.
2
Q 1 1
Nrj
OpwratlDn 3-StBt«
1
X
X X X DiwblE: 3-StaW
% 1
X
X No-Operation
3-
Sut*
Indicates that
the address bus holds
a
valid memory
address for
a
memory
read or memory write cycle.
Indicates that lover 3 bits (I/O
Device
tober)
are
on the
address bus
for an l/O
read or
I/O write cycle.
Indicates that the
GPU wants to
read data from memory
or
an I/O device.
Indicates that
the
CHJ data bus holds
valid data to
be
stored
in the
addressed memory
or
I/O device.
Used as
Tempo GlocK in
PLAY mode and
is
accepted by
the
CHJ after
it
completes the current instruction
being executed provided that CPU internal
INT enable
flip-flop
Is
set on.
Used
to time the lightings of
Dot Matrix
Display and
•
Shift lEDs,
Key
Switch Scanning, and
the
outputtmgs
of
CV and GATE.
Accepted by the
CPU unconditi-onally
upon finishing of
current instruction.
Used
to
keep the
CPU wait for
1
clock cycle to Provide
enough performance time for relatively low speed
ROM
and RAM being accessed by the
CPU",
Indicates Fetch cycle.
Used
to reset and
start the GPU from a power down
condition resulting from failure
or initial start-
up of
the processor.