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Pin Assignment
Name
GND
VCC
VBAT
SCL
GIO10
SDA
GIO11
GIO12
GIO13
PAEN
EN
XANTN
USBN
XANTP
USBP
CSN
SCLK
MOSI
MISO
GIO1
GIO2
GIO3
RSTN
MCLK
GIO4
BCLK
GIO5
Pin function
The exposed die attach pad must be connected to a solid
Ground
ground plane underneath the chip
Power
2.0-3.6V analog power supply connection
Battery voltage supervisor (threshold level programmable by
Analog input
external resistor to positive battery terminal)
I2C master clock line. Must be connected to external pull-up
1
Digital I/O
General-purpose digital I/O pin 10
I2C master clock line. Must be connected to external pull-up
1
Digital I/O
General-purpose digital I/O pin 11
1
Digital I/O
General-purpose digital I/O pin 12
1
Digital I/O
General-purpose digital I/O pin 13
2
Digital I/O
Control external PA
2
Digital I/O
Control external LNA
CC85x0: DO NOT CONNECT (Future FW: Controlling
1
Digital I/O
external antenna switch) CC85x1: USB D- data line
CC85x0: DO NOT CONNECT (Future FW: Controlling
1
Digital I/O
external antenna switch) CC85x1: USB D+ data line
Digital Input
Serial SPI configuration interface, active low chip select
(pull-up)
1
Digital I/O
Serial SPI configuration interface, clock input/output
Serial SPI configuration interface, master data output, slave
1
Digital I/O
data input
Serial SPI configuration interface, master data input, slave
1
Digital I/O
data output
General-purpose digital I/O pin 1
1
Digital I/O
Configurable with PurePath™ Wireless Configurator
1
Digital I/O
General-purpose digital I/O pin 2
General-purpose digital I/O pin 3
2
Digital I/O
Configurable with PurePath™ Wireless Configurator
Digital Input
Active-low device reset
(pull-up)
Master clock output for external audio devices
1
Digital I/O
General-purpose digital I/O pin 4
I2S/DSP audio interface bit clock (in/out)
1
Digital I/O
General-purpose digital I/O pin 5
Description
4
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