Sharp R-2397 Service Manual page 22

R-2397
Pin No. Signal
46 P10 OUT
47-48 P07-P06 OUT
49 P05 OUT
50-54 P04-P00 OUT
55-57 P27-P25 OUT
58-59 P24-P23 OUT
60 P22 OUT
61 P21 OUT
62 P20
63/64 AVCC/VCC
AT24C04 is a 4K-bit, serial memory, enabling CMOS to be erased/written electrically. This memory is constructed with 512
registers x 8bits, enabling individual access, read and write operations to be performed. Details of input/output signal for IC2
are as shown in the following diagram.
TOP VIEW
A0
1
2
A1
A2 3
VSS 4
I/O
Segment data signal.
Signal similar to P17.
Segment data signal.
Signal similar to P17.
Digit selection signal.
The relation between digit signal and digit are as
follows:
Digit signal Digit
P05 1st.
P04 2nd.
P03 3rd.
P02 4th.
P01 5th.
P00 6th.
Normally, one pulse is output in every ß period,
and input to the grid of the Fluorescent Display.
Digit selection signal.
Signal similar to P16.
Terminal not used.
Segment data signal.
Signal similar to P17.
(Sound) Voltage level control terminal.
This terminal (P22) is to control volume level of buzzer sound with terminals P21. Since
the volume level of buzzer sound depends on voltage energized, it is control level in 3
steps by combining signal levels for P22,P21. Relationship of signal level combination to
sound volume level is shown in the following table, 1~3 in the table, however, are indicated
in the descending order from the maximum level of sound volume through the minimum
level.
Sound Volume
1,(Max.)
2,
3,(Min.)
*At Output terminal P32, rectangular wave signal of 2.5kHz is output.
Sound level control signal.
Refer to above signal P22.
IN Input signal which communicates the door open/close information to LSI.
Door closed; "H" level signal(0V).
Door opened; "L" level signal(-31.0V).
IN Connected to GND.
2-2 Memory IC (IC2)
VCC
8
TEST
7
SCL
6
SDA
5
Figure T-4 Relation between Pin Nos, and Signals
Description
P21 P22
L L
H L
L H
FUNCTIONAL DIAGRAM
(3) Vcc
(4) Vss
(5) SDA
START
STOP
LOGIC
SLAVE ADDRESS
REGISTER
(6) SCL
COMPARATOR
LOAD
ADDRESS
COUNTER
R/W
Dout
ACK
20
ß(50Hz)
P05
P04
P03
P02
P01
P00
A : 1,(Max) 20V
A
2,
3,(Min)
H.V. GENERATION
START CYCLE
TIMING
& CONTROL
CONTROL
LOGIC
2
E PROM
64
512 x 8
XDEC
INC
WORD
1
64
5
3
YDEC
8
CK
Dout
PIN
DATA REGISTER
H
L
GND
-31(V)
GND
-31(V)
13V
7V