Summary of Contents for Acces PCI-WDG-CSM
- Page 1 10623 Roselle Street, San Diego, CA 92121 • (858) 550-9559 • FAX (858) 550-7322 contactus@accesio.com • www.accesio.com MODEL PCI-WDG-CSM USER MANUAL FILE: MPCI-WDG-CSM.F1d...
- Page 2 ACCES, nor the rights of others. IBM PC, PC/XT, and PC/AT are registered trademarks of the International Business Machines Corporation. Printed in USA. Copyright 2001, 2005 by ACCES I/O Products Inc, 10623 Roselle Street, San Diego, CA 92121. All rights reserved. WARNING!! ALWAYS CONNECT AND DISCONNECT YOUR FIELD CABLING WITH THE COMPUTER POWER OFF.
- Page 3 Prior to shipment, ACCES equipment is thoroughly inspected and tested to applicable specifications. However, should equipment failure occur, ACCES assures its customers that prompt service and support will be available. All equipment originally manufactured by ACCES which is found to be defective will be repaired or replaced subject to the following considerations.
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Page 4: Table Of Contents
Watchdog Programming Options ................19 Chapter 6: Connector Pin Assignments ..............22 Table 6-1: DB25F Connector J1 Pin Assignments................22 Table 6-2: On-Board Terminal Block Pin Assignments..............23 Appendix A: Programmable Interval Timer .............. 24 Operation Modes ..................... 24 Programming ......................25 Manual PCI-WDG-CSM... -
Page 5: Chapter 1: Introduction
Discussion of these Watchdog Programming Options is given in a later chapter. Manual PCI-WDG-CSM... - Page 6 This output goes high to signal a watchdog reset condition. Finally, a 130.208 kHz, TTL-level, 50 percent duty cycle signal is provided at I/O connector pin 13 when the watchdog circuit is enabled and no reset is in progress. Otherwise, this output is in a low state. Manual PCI-WDG-CSM...
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Page 7: Options
+D is required. To activate the Opto-Isolated NOT reset, a write to base address+E is required. To deactivate a read to base address +E is required. Both of these outputs are deactivated by a computer reset. Manual PCI-WDG-CSM... - Page 8 Watchdog counter refresh reminder (Active low) Temperature good (Active high) Isolated Input #0 status (Same as input) Isolated Input #1 status (Same as input) Fan good (Active high) Power Supply overvoltage (Active low) Power Supply undervoltage (Active low) IRQ generated (Active high) Manual PCI-WDG-CSM...
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Page 9: Specification
-50 °C. to +120 °C • Humidity: 10% to 90% RH, non-condensing • Power Required: +5 VDC at 125 mA w/ no options, 250 mA all options installed • Size: 6.7 inches long (170 mm) x 3.9 inches high (99 mm) Manual PCI-WDG-CSM... - Page 10 Figure 1-1: Block Diagram Manual PCI-WDG-CSM...
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Page 11: Chapter 2: Installation
Caution! * ESD A single static discharge can damage your card and cause premature failure! Please follow all reasonable precautions to prevent a static discharge such as grounding yourself by touching any grounded surface prior to touching the card. Manual PCI-WDG-CSM... - Page 12 BIOS calls used to determine the address and IRQ assigned to installed PCI devices. In Windows, the Windows sample programs demonstrate querying the registry entries (created by PCIFind and NTIOPCI.SYS during boot-up) to determine this same information. Manual PCI-WDG-CSM...
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Page 13: Connecting The Reset Line
2-3, or connect the power good line to the “NC” header as shown in figure 2-2. Note: If the “NC” header is used ensure that a jumper is installed on the “GND” and the “EN” headers on the Watchdog card. To Motherboard CAB-WDG-RST Reset Pins From Reset Button RELAY Figure 2-1: Reset Button Connection Manual PCI-WDG-CSM... -
Page 14: Connecting A Fan
FAN + terminal. To restart a fan that has stopped, push the momentary switch which should signal the fan controller chip on our card to switch the status bit to FAN GOOD, which should then restart the fan. Manual PCI-WDG-CSM... -
Page 15: Chapter 3: Option Selection
A connector for an external or on-board LED is provided at two solder pads labeled J2. The output is limited by a 470 ohm resistor in series with a 5V output. This output is only active if the Buzzer option is installed. Manual PCI-WDG-CSM... - Page 16 GR OU N D W D R S T FA N P OW E R + FA N P OW E R - FA N R E S E T R E LAY C ON TR OL Figure 3-1: Option Selection Manual PCI-WDG-CSM...
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Page 17: Chapter 4: Address Selection
PCIFind uses the Vendor ID and Device ID to search for your card, then reads the base address and IRQ. To determine the base address and IRQ yourself, use the following information. The Vendor ID for the card is 494F. (ASCII for "IO") The Device ID for the card is 22C0h. Manual PCI-WDG-CSM... -
Page 18: Chapter 5: Programming
Base Address +C Hi Rate Clock Select Low Rate Clock Select Base Address +D Disable Opto-Output NWDRST Enable Opto-Output NWDRST Base Address +E Disable Opto-Output WDRST Enable Opto-Output WDRST Base Address +F Unused Unused Table 5-1: Register Address Map Manual PCI-WDG-CSM... -
Page 19: Interrupts
Once the counters have been enabled, the computer will reset if the 32-bit counter decrements all the way to zero. (Note: An alternative use of the reset signal is to simply notify an external device that a reset is necessary.) Manual PCI-WDG-CSM... - Page 20 This combined method eliminates the negatives associated with either method used individually, but does require extensive modifications to existing code, or even rewriting code entirely. In this scheme, both foreground and background routines can prompt the watchdog. Manual PCI-WDG-CSM...
- Page 21 After prompting the watchdog, it returns control to the foreground process. If the count of missed prompts gets too high, it could write status to a disk file or serial port, then skip the prompt, allowing the computer to reset. Manual PCI-WDG-CSM...
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Page 22: Chapter 6: Connector Pin Assignments
Opto-Isolated Input #0 Source (Anode) Opto-Isolated Input #0 Return (Cathode) Opto-Isolated Input #1 Return (Cathode) Opto-Isolated Input #1 Source (Anode) Fan Restart Input (pulled down, active high) Ground Ground Ground Ground Table 6-1: DB25F Connector J1 Pin Assignments Manual PCI-WDG-CSM... - Page 23 +12V (Fan Red or Yellow Wire) Terminal FAN – (BLACK) Open Collector PWM (Fan Black Wire) Bottom Terminal FAN RESET Fan Restart Input - Active High (See Pin 21 - Connector) Table 6-2: On-Board Terminal Block Pin Assignments Manual PCI-WDG-CSM...
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Page 24: Appendix A: Programmable Interval Timer
In this mode, the counter will start counting after the rising edge of the trigger input and will go low for one clock period when the terminal count is reached. The counter is retriggerable. The output will go low until the full count after the rising edge of the trigger. Manual PCI-WDG-CSM... -
Page 25: Programming
Read/Write MS Byte Read/Write LS Byte, then MS Byte M0, M1, and M2: These bits set the operational mode of the selected counter. Mode M2 M1 M0 BCD: Set the selected counter to count in binary (0) or BCD (1). Manual PCI-WDG-CSM... - Page 26 If STA and CNT bits in the readback command byte are set low and the RW1 and RW0 bits have both been previously set high in the counter control register (thus selecting two-byte reads), then reading a counter address location will yield: Manual PCI-WDG-CSM...
- Page 27 After any latching operation of a counter, the contents of its hold register must be read before any subsequent latches of that counter will have any effect. If a status latch command is issued before the hold register is read, then the first read will read the status, not the latched value. Manual PCI-WDG-CSM...
- Page 28 If you experience any problems with this manual or just want to give us some feedback, please email us at: manuals@accesio.com. Please detail any errors you find and include your mailing address so that we can send you any manual updates. 10623 Roselle Street, San Diego CA 92121 Tel. (858)550-9559 FAX (858)550-7322 www.accesio.com Manual PCI-WDG-CSM...
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