3. The Helio Board Hardware Descriptions 3.1 Overview This document describes the hardware features of the Helio board, including the detailed pin-out and component reference information required to create custom FPGA designs that interface with all components of the board.
Mpression Helio Board 4. The Helio board Components 4.1 Board Overview This section provides an overview of the Helio board Figure 4-1-1 shows a top view of the board. User Defined User Defined Warm Reset Cold Reset JTAG Master MICTOR_38P...
Mpression Helio Board 4.2 Featured Device: Cyclone V SoC Cyclone V SoC 5CSXFC6C6U23CNES and 5CSXFC5C6U23C7N device in a 672-pin UBGA package is surface-mounted on the Helio board. Table 4-2-1 describes the features of the Cyclone V SoC 5CSXFC6C6U23C and 5CSXFC5C6U23C device.
Mpression Helio Board 4.3 JTAG Configuration This section describes configuration methods of FPGA and HPS supported by the Helio board. The Helio board supports the following three configuration methods: On-board USB-Blaster II is the default method for configuring the FPGA/HPS using the ...
Mpression Helio Board 4.4 Status Elements The Helio board includes status LEDs. This section describes the status elements. Table 4-4-1 lists the LED board references, name, and functional descriptions. Table 4-4-1. Board-Specific LEDs Board Schematic I/O Standard Description Reference Signal Name Green LED.
Mpression Helio Board 4.5 Setup Elements The Helio board includes some of setup elements. This section describes the following setup elements: JTAG settings DIP switch HPS operation mode setting Jumper HPS reset push button Program configuration push button ...
USB Blaster II MAXII EZ-USB CY7C68013A Figure 4-5-1. Reset tree on the Helio board 4.5.4 Program configuration push button The program configuration push button, nCONFIG (SW3), is an input to the Cyclone V SoC nCONFIG pin. This input forces a FPGA reconfiguration from the EPCQ memory. Table 4-5-5 lists the switch control and its description.
3.3-V Push this button when FPGA is required configuration again. 4.5.5 MSEL pins Settings In the Helio board, the MSEL pins of the Cyclone V SoC are set as follows. Table 4-5-6. MSEL pins Setting MSEL[4..0] Configuration mode POR Delay...
4.6.1 On board Oscillators The Helio board includes oscillators with a frequency of 25-MHz, 50-MHz, 100-MHz and 125-MHz. Figure 4-6-1 shows the default frequencies of all external clocks going to the Helio board. 10/100/1000 Ba s e-T Fi xed OSC...
4.6.2 Off-board inputs / outputs The Helio board has input and output clocks which can be driven onto the board. The output clocks can be programmed to different levels and I/O standards according to the FPGA device's specification. Table4-6-2 lists the clock inputs for the Helio board.
4.7.1 User-Defined push button The Helio board includes seven user-defined push buttons. Board references SW11, SW12 and SW13 are push buttons for controlling FPGA logic of Cyclone V SoC FPGA. Board references SW7 through SW10 are push buttons to inputs to HPS_GPI on the Cyclone V SoC HPS.
4.7.3 User-Defined LEDs The Helio Board includes general user-defined LEDs. Board references LED3 through LED6 are user-defined LEDs. For example, status and debugging signals are driven to the LEDs from Cyclone V SoC FPGA logic. Driving logic 0 on the I/O port turns the LED on while driving logic 1 turns the LED off.
4.7.5 Debug Header The Helio board includes four debug through hole for debug purposes. Cyclone V SoC HPS GPIO route directly to the through hole for the debugging, or quick verification. Table 4-7-5 lists the debug through hole pin assignments, signal names, and functions.
Mpression Helio Board 4.8 Components and Interfaces This section describes the Helio board's communication ports and interface relative to the Cyclone V SoC device. The Helio board supports the following communication ports: 10/100/1000 Ethernet HSMC USB2.0 OTG ...
4.8.2 HSMC The Helio board supports a HSMC interface. The HSMC interface also supports a full SPI4.2 interface (17 LVDS channels), three input and output clocks, as well as SMB signals. The LVDS channels can be used for CMOS signaling or LVDS.
4.8.3 USB2.0 OTG The Helio board supports USB 2.0 OTG using an external SMSC USB3300 PHY and HPS ULPI LINK function. The PHY-to-LINK interface is ULPI interface. The LINK function must be provided in the Cyclone V SoC HPS for typical USB applications.
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CP210x USB to UART Bridge VCP Drivers J10 header In the Helio board, J10 is header for UART loop back test. Do not short J10 header at normal operation. 4.8.5 The Helio board supports microSD card interface using Cyclone V SoC HPS SD function.
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Mpression Helio Board 4.9 Memory This section describes the Helio board's memory interface support and also their signal names, types, and connectivity relative to the Cyclone V SoC. The Helio board has the following memory interfaces: DDR3-SDRAM QSPI FlashROM ( QSPI device is not mounted. Only interface is supported. ) ...
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Note: Macnica doesn't guarantee the operation when you mounted QSPI Flash ROM to this product. 4.9.3 EEPROM The Helio board supports using Cyclone V SoC HPS I2C function a 32kbit EEPROM device for MAC Address of Ethernet. Refer to 4.8.6 I2C if you want to confirm detail EEPROM.
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