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LSI EB402 User Manual

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USER'S GUIDE
EB402 Evaluation Board
J u l y 2 0 0 1
®
l14020.A

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Summary of Contents for LSI EB402

  • Page 1 USER’S GUIDE EB402 Evaluation Board J u l y 2 0 0 1 ® l14020.A...
  • Page 2 LSI Logic; nor does the purchase or use of a product from LSI Logic convey a license under any patent rights, copyrights, trademark rights, or any other of the intellectual property rights of LSI Logic or third parties.
  • Page 3 This document is the primary reference and user’s guide for Revision 1 and Revision 2 of the EB402 Evaluation Board. Unless otherwise noted, references to the EB402 apply to Revision 1 and Revision 2 printed circuit boards (PCBs). LSI Logic incorporated the following changes in Revision 2 of the EB402 Evaluation Board: •...
  • Page 4 Operation, explains the EB402 operating modes. • Chapter 5, Board Layout and Jumper Settings, shows the physical layout of the EB402, lists jumpers and their default settings, and provides the pinouts for the PCB interface connectors. • Appendix A, Schematics, contains the schematics for the EB402 and the BD-EBM-CODEC-1 Codec Daughterboard.
  • Page 5 ZSP web site, www.zsp.com. If you would like further information about components that are not LSI Logic products, refer to the manufacturers’ information. Conventions Used in This Manual The word assert means to drive a signal true or active. The word deassert means to drive a signal false or inactive.
  • Page 6 Preface...

  • Page 7: Table Of Contents

    Contents Chapter 1 Introduction Product Features Operating Modes 1.2.1 JTAG Mode 1.2.2 RS-232 Mode 1.2.3 Stand-Alone Mode Block Diagram Packing List Related Components Chapter 2 Installation Board Layout Preparing to Install the Evaluation Board Installing the Evaluation Board Power-Up Sequence Chapter 3 Hardware Overview Clock and Control Signals...
  • Page 8 RS-232-Based Emulation 4.3.1 Connecting RS-232 Hardware 4.3.2 Installing SDK and Using the RS-232 Interface Using Stand-Alone Mode Chapter 5 Board Layout and Jumper Settings EB402 Jumpers External Connectors Appendix A Schematics Appendix B Bill of Materials Customer Feedback viii Contents...
  • Page 9 J11, EEI A/D Connector 5-10 J8, EEI Control Connector 5-11 EB402 Schematics (Sheet 1 of 6) EB402 Schematics (Sheet 2 of 6) EB402 Schematics (Sheet 3 of 6) EB402 Schematics (Sheet 4 of 6) EB402 Schematics (Sheet 5 of 6)
  • Page 10 Memory Chip Select 3-24 Evaluation Board Jumper Settings and Descriptions Connector Summary EB402 Bill of Materials BD-EBM-CODEC Bill of Materials Contents...

  • Page 11: Introduction

    Chapter 1 Introduction The EB402 is the evaluation board for the LSI Logic Corporation LSI402ZX Digital Signal Processor (DSP) device. The EB402 provides a hardware platform for evaluating the device and a software platform for developing, debugging, and demonstrating real-time applications for the LSI402ZX DSP.

  • Page 12: Operating Modes

    Two serial port interfaces for flexible peripheral configurations. • Codec Daughterboard(s) that supports up to eight channels of real-time analog audio I/O. • Host Processor Interface (HPI) for connecting the EB402 to a host microprocessor. 1.2 Operating Modes The EB402 has three operating modes: •...

  • Page 13: Rs-232 Mode

    JTAG-based emulation requires an IBM-compatible PC, a Corelis JTAG controller (PCI or PCMCIA) installed on the PC, a JTAG cable connecting the PC to the EB402, and the LSI Logic Corporation SDK Software Development Kit. SDK provides a compiler, assembler, linker, debugger, and other utilities required to create, simulate, debug and execute LSI402ZX programs on the EB402.

  • Page 14: Block Diagram

    EB402, or use the demonstration code that is included in the flash ROM. The flash ROM is preprogrammed with code that supports serial port debug and illuminates LEDs that indicate a successful self-test.

  • Page 15: Packing List

    • This user’s guide, Document DB15-000143-01. • EB402 Evaluation Board Getting Started. Confirm that these items are included with your EB402. If any items are missing, contact LSI Logic Corporation or your LSI Logic manufacturer’s representative. 1.5 Related Components Although the following items are not part of the EB402 package, you may need these items to use with the EB402.
  • Page 16 The following software components are available on the ZSP web site (http://www.zsp.com): • Example code • Utility software LSI Logic international distributors are listed in the back of this user’s guide. Introduction...

  • Page 17: Installation

    Chapter 2 Installation This chapter explains how to install the EB402 and verify that it is functioning correctly. It includes the following sections: • Section 2.1, “Board Layout” • Section 2.2, “Preparing to Install the Evaluation Board” • Section 2.3, “Installing the Evaluation Board”...

  • Page 18: Preparing To Install The Evaluation Board

    JP22 EXT A/D 2.2 Preparing to Install the Evaluation Board Prepare to install the EB402 by following this procedure: 1. Using appropriate antistatic measures to prevent electrostatic discharge (ESD) damage, unpack the PCB and the other components. 2. Verify that you have received all the components. Refer to Section 1.4, “Packing List”...

  • Page 19: Installing The Evaluation Board

    EB402 power supply is compatible with 120 V or 60 Hz and 240 V or 50 Hz sources. 3. Connect the power supply’s DC output to the EB402 power jack, J9. 4. Select either RS-232- or JTAG-based emulation. You may not use both emulation modes simultaneously.
  • Page 20 5. Select the boot device. You may boot from either the on-board external memory or the on-chip internal memory. To boot from on-board external memory, install the IBOOT jumper, JP3. Also, verify that the XBOOT jumper, JP18, is installed. The position of JP18 determines whether flash memory or asynchronous SRAM is the boot memory.

  • Page 21: Power-Up Sequence

    If necessary, adjust the voltage with 25-turn potentiometer R12. 5. Verify that the self-test diagnostic completes successfully. The EB402 runs a self-test diagnostic when it boots from its internal ROM. The LSI402ZX illuminates LED3 when the test starts and extinguishes LED3 when the self-test completes successfully.
  • Page 22 Installation...

  • Page 23: Hardware Overview

    Only a few LSI402ZX signals are described in this chapter. Each of these signals has a jumper, switch, or external connection that a user must manipulate to configure the Evaluation Board. These configuration options are explained in the following sections. For a complete listing of EB402 jumper settings, refer to Table 5.1.

  • Page 24: Evaluation Board Block Diagram

    Figure 3.1 Evaluation Board Block Diagram Macraigor Connector Corelis JTAG Connector JTAG PIO0-6 Power 3.3 V Pull-Up/Pull-Down Monitor Selection Switch 10 MHz EXT CLKIN 1.8 V Power Monitor Buffer SYSRESETN UART PIO7 to CHIP SELECT JTAG CLKIN RSTN CONFIG IBOOT INT0 From EEI PIO7...

  • Page 25: Clock And Control Signals

    LSI402ZX. Connect pins 1–2 of JP1 to select the on-board oscillator. External Oscillator – The EB402 also allows an external oscillator to clock the LSI402ZX. To use an external oscillator, connect pins 2–3 of JP1, and connect an external oscillator to BNC connector J4.

  • Page 26: Pllbypass (Pll Bypass)

    Set the multiplier with the rotary hex encoder, S2. The encoder has 16 positions that correspond to multipliers of 10–25. Multiplier 25 is reserved for test. The EB402 provides a 10 MHz clock to CLKIN. Therefore, using the on-board oscillator, the range of operating frequencies is 100–240 MHz.

  • Page 27: Rstn (Device Reset)

    LSI402ZX. The power monitor holds SYSRESETN LOW for 1.12 seconds. SYSRESETN is inverted and routed to the EB402 on-board UART to reset serial communications. For test purposes, SYSRESETN is connected to J8, which is the control connector for the EEI.

  • Page 28: Iboot (Memory Map Select)

    3-19. 3.1.7 INT[4:0] (External Hardware Interrupts), NMI (Nonmaskable Interrupt) INT[4:0] and NMI are external interrupt signals to the LSI402ZX. These active-HIGH input signals are pulled LOW on the EB402. The EB402 uses these interrupts as shown in Table 3.2. Table 3.2...

  • Page 29: Halt (Halt Processor Clock)

    HALT is an input to the LSI402ZX. When HALT is asserted, the processor clock is disabled and halts the processor. This signal is pulled LOW on the EB402. To halt the processor while it is running, install jumper JP4. RSTN or NMI must be used to wake a halted DSP. RSTN resets the processor.

  • Page 30: Controlling The Codecs

    You must reset the serial port audio codec daughterboards (BD-EBM-CODEC-1), select their operating mode, and enable them before using them. Use PIO[3:0] to reset and enable the codecs. One codec is included with the EB402 package. It is configured and installed on SPORT0. Hardware Overview...

  • Page 31: Controlling The Hpi Mode

    Each PIO has a user configured jumper to select pull-up or pull-down termination. The default configuration is pulled-up. When the PIOs are configured as inputs, the jumpers can be used to continuously reset, or enable, a codec for testing or debugging. PIO0 enables the codec on Serial Port 0.

  • Page 32: External Interfaces

    3.3 External Interfaces The section provides an overview of the EB402 external interfaces. In this section, external interfaces are the physical interfaces users encounter when operating the EB402. Refer to Section 5.2, “External Connectors,” page 5-5, for additional information about external interfaces.

  • Page 33: Jtag Interfaces

    3.3.1 JTAG Interfaces The EB402 provides two JTAG interfaces to support emulators from Corelis and Macraigor. 3.3.1.1 Corelis JTAG Interface The Corelis JTAG connector, J7, provides a physical interface to the host computer. The JTAG interface signals are buffered and connected to a 10-pin, low-profile header.

  • Page 34: Macraigor Jtag Connector

    Figure 3.3 Macraigor JTAG Connector XTDO XTDI XTRSTN VDD_SENSE XTCK SYSRESTN The Macraigor JTAG interface works with the Green Hills Software development tools and the Macraigor JTAG emulator that is attached to the PC parallel port to provide full-speed in-circuit emulation. 3-12 Hardware Overview...

  • Page 35: Rs-232 Interface

    3.3.2 RS-232 Interface The EB402 has an RS-232 interface to provide a communication link between the Evaluation Board and a host PC or workstation. The RS-232 interface uses a 9-pin female D-type connector, J10. The interface may be used for emulation, or as a general-purpose serial interface.

  • Page 36: Bd-Ebm-Codec-1 Daughterboard

    Serial Port 0 is connected to J3; Serial Port 1 is connected to J2. The connectors provide a physical interface for mounting daughterboards on the EB402. The standard daughterboard is an audio codec module, BD-EBM-CODEC-1. One BD-EBM-CODEC-1, configured and installed on SPORTO, is included...
  • Page 37 There are two of these devices on each daughterboard, and each device has two ADCs. After the analog signals are digitized, they are transmitted to the EB402 through the AD73322’s serial ports. The codec module receives processed digital signals from the EB402 through the AD73322 serial ports.

  • Page 38: Bd-Ebm-Codec-1 Audio Connectors

    Each BD-EBM-CODEC-1 module provides four 3.5 mm stereo audio jacks for connecting external audio signals to the board. There are two input-jacks and two output-jacks; one input-jack and one output-jack is dedicated to each AD73322. Because each jack is a stereo connector, the daughterboard supports a maximum of four inputs and four outputs.

  • Page 39: Ebm Codec-1 Board Layout

    The daughterboard ADCs must be configured in cascade mode to permit the maximum number of I/Os. The codec module is configured with removable jumpers. Cascade mode is the default configuration. The BD-EBM-CODEC-1 board layout, shown in Figure 3.7, shows the location of these jumpers.

  • Page 40: Host Processor Interface (Hpi)

    3.3.4 Host Processor Interface (HPI) The LSI402ZX HPI is an asynchronous 16-bit parallel port that allows an external device to connect to the EB402. The HPI supports word transfers for Motorola- and Intel-style memory interfaces. The LSI402ZX internal boot ROM supports downloading code through the HPI, so an external device connected to this interface can download code from a host processor to the DSP.

  • Page 41: External Expansion Interface (Eei)

    PCS3N is programmed for zero wait states by setting register p3wait = 0x0000. 3.4 Memory and Memory-Mapped Peripherals The EB402 memory consists of internal memory, which is inside the LSI402ZX, and external memory, which can be on-board or off-board. On-board external memory consists of flash memory, asynchronous SRAM, and SBSRAM.

  • Page 42: Internal Memory

    LSI402ZX memory architecture. 3.4.2 External Memory and Memory-Mapped Peripherals The EB402 provides external memory space that is accessible to the LSI402ZX through its XBUS interface. The LSI402ZX can address up to 2 Mwords of external memory. External memory may be on-or off-board.

  • Page 43: External Memory

    Figure 3.8 External Memory Data Bus [31:0] Address Bus [17:0] JP14 DCS0N D[31:0] SyncBurst RD WR0N WR1N SRAM JP18 128K x 32 A[17:0] ICS0N D[15:0] RD WR0N Flash 512K x 16 JP17 DCS2N A[17:0] LSI402ZX JP13 ICS1N D[15:0] RD WR0N Asynchronous JP16 DCS1N...
  • Page 44 3.4.2.1 SRAM The on-board SRAM is an IDT 71V416S10Y, a 256 kword x 16-bit asynchronous SRAM with a 10 ns access time. The 71V416S10Y can be configured as instruction memory or data memory. To configure the SRAM as instruction memory that is enabled by ICS1N, install JP13. To configure the SRAM as instruction memory that is enabled by ICS0N, install a jumper between pins 2–3 of JP18.
  • Page 45 (10 ns for access SRAM and 100 ns for Flash ROM). • is the required EB402 external data set-up time (4 ns). setup • is the processor instruction cycle time. cycle For example, assume the LSI402ZX processor clock is operating at 100 MHz.

  • Page 46: Memory Chip Select

    3.4.2.5 Memory Space Allocation External memory can be configured as instruction memory, data memory, or peripheral memory. In general, on-board jumpers configure the memory. Table 3.6 shows how the Evaluation Board uses the chip selects to map on-board memory. Table 3.6 Memory Chip Select Chip Select Memory Space...
  • Page 47 3.4.2.6 UART Memory Space Although not memory, the on-board UART is mapped into the LSI402ZX peripheral memory space. It is enabled by PCS0N. Accessing peripheral memory requires wait states. These calculations are shown in Section 3.4.2.4, “Wait States.” 3.4.2.7 External Expansion Interface (EEI) The XBUS control, address, and data signals are buffered and routed to two external connectors: the control signals go to J8;...
  • Page 48 3-26 Hardware Overview...

  • Page 49: Operation

    HIGH, then reset to input mode. The Evaluation Board uses PIO0 as a discrete signal to the Serial Port 0 Interface connector, where it is used to enable the codec daughterboard. Jumper JP11 selects pull-up or pull-down termination for this signal. EB402 Evaluation Board User’s Guide...

  • Page 50: Jtag Emulation

    LSI402ZX Digital Signal Processor User’s Guide for additional information about the JTAG port and the DEU. 4.2.1 JTAG Software Tools To use the EB402 in the JTAG mode, you need software tools that are compatible with your JTAG controller hardware. 4.2.1.1 ZSP SDK Software Development KIt Using the Corelis JTAG controller with the EB402 requires the ZSP SDK Software Development Kit.

  • Page 51: Jtag Hardware Tools

    4.2.1.2 Green Hills Software ZSP Development Kit Using the Macraigor JTAG controller with the EB402 requires the Green Hills Software ZSP Development Kit. The kit includes a C-language cross compiler, assembler and linker, simulator, debugger, and software drivers for the Macraigor JTAG controller.

  • Page 52: Installing Jtag Tools

    4.3 RS-232-Based Emulation RS-232-based emulation requires the RS-232 cable that is included with the EB402 to connect it to the host computer. The ZSP400 SDK Software Development Kit must be installed on the host computer. On the evaluation board, the RS-232 interface connects to the LSI402ZX through an on-board UART and provides access to all on-chip resources.

  • Page 53: Connecting Rs-232 Hardware

    Processor User’s Guide for additional information about the DEU. 4.3.1 Connecting RS-232 Hardware To use the EB402 in RS-232-based emulation mode, connect the host computer’s RS-232 serial port to J10 on the evaluation board using the RS-232 cable, as shown in Figure 4.2.

  • Page 54: Using Stand-Alone Mode

    4.4 Using Stand-Alone Mode In stand-alone mode, the EB402 executes code from on-board memory. No host computer is required. To operate the Evaluation Board in stand-alone mode, use the following procedure: 1. The on-board flash memory is preprogrammed with executable demonstration code that you can use without modification.

  • Page 55: Board Layout And Jumper Settings

    Jumper Settings 12 pc 12.938 p 13.851 p This chapter describes the physical layout of the EB402. It includes connectors, jumpers, and default jumper settings for the Evaluation Board, as shipped by LSI Logic Corporation. Figure 5.1 is a simplified drawing of the Evaluation Board that locates all the major components discussed in this section.

  • Page 56: Eb402 Jumpers

    3.75 pc 10.25 pc 11.25 pc 38.25 pc 34.5 pc 4.333 pc Figure 5.1 Evaluation Board Layout EB402 S/N 134-30 EB402 S/N 134-30 REV 2/2.1 BD-EBM_CODEC-1 Module REV 2/2.1 BD-EBM_CODEC-1 Module PLL OUT PLL OUT REF IN JTAG REF IN...

  • Page 57: Evaluation Board Jumper Settings And Descriptions

    PIO1. PIO1 is used by the SPORT0 Daughterboard Interface. JP11 PIO0 Selects pull-up or pull-down Pull-down PIO0 Pull-up Pins 2–3 for termination for PIO0. PIO0 is used by the SPORT0 Daughterboard Interface. 48.583 p EB402 Jumpers 52.5 pc...
  • Page 58 3.75 pc 10.25 pc 11.25 pc 38.25 pc 34.5 pc 4.333 pc Table 5.1 Evaluation Board Jumper Settings and Descriptions (Cont.) Label Description Pin 1 Pin 2 Pin 3 Default JP12 PLLBYPASS – Remove this PLLBYPA Installed jumper to bypass the on-chip SS pull-up PLL, and use CLKIN for the processor clock.

  • Page 59: External Connectors

    3.75 pc 10.25 pc 11.25 pc 38.25 pc 34.5 pc 4.333 pc 5.2 External Connectors This section describes the evaluation board’s external connectors. Table 5.2 lists all evaluation board connectors. It shows the connector number, silk-screen label, and a functional description of each connector. Figures referenced in the table illustrate connector pinout information.

  • Page 60: J5, Macraigor, Jtag Connector

    3.75 pc 10.25 pc 11.25 pc 38.25 pc 34.5 pc 4.333 pc Figure 5.2 shows the Macraigor JTAG Interface connector, connector pins, and signal names. Figure 5.2 J5, Macraigor, JTAG Connector VDD_SENSE TRSTN HRESTN NC-Key 44.25 pc 48.583 p Board Layout and Jumper Settings 52.5 pc...

  • Page 61: J6, Hpi Interface Connector

    3.75 pc 10.25 pc 11.25 pc 38.25 pc 34.5 pc 4.333 pc Figure 5.3 shows the HPI Interface connector, connector pins, and signal names. Figure 5.3 J6, HPI Interface Connector + 9VDC HPI DATA 00 HPI DATA 01 HPI DATA 02 HPI DATA 03 HPI DATA 04 HPI DATA 05...

  • Page 62: J10, Rs-232 Interface Connector

    3.75 pc 10.25 pc 11.25 pc 38.25 pc 34.5 pc 4.333 pc Figure 5.5 shows the RS-232 Interface connector, connector pins, and signal names. Figure 5.5 J10, RS-232 Interface Connector *DCD *DSR *DTR RI (No Connection) Note: Pins 1, 4, and 6 are tied together. Figure 5.6 shows the Serial Port 0 Daughterboard Interface connector, connector pins, and signal names.

  • Page 63: J2, Sport1 Daughterboard Interface Connector

    3.75 pc 10.25 pc 11.25 pc 38.25 pc 34.5 pc 4.333 pc Figure 5.7 shows the Serial Port 1 Daughterboard Interface connector, connector pins, and signal names. Figure 5.7 J2, SPORT1 Daughterboard Interface Connector VDDIO33 VDDIO33 INT3 S1DI PIO2 S1RFS PIO3 SYSRESET *10 MHz...

  • Page 64: J11, Eei A/D Connector

    3.75 pc 10.25 pc 11.25 pc 38.25 pc 34.5 pc 4.333 pc Figure 5.8 shows the EEI address and data connector, connector pins, and signal names. Figure 5.8 J11, EEI A/D Connector RGND +3.3 VDC +3.3 VDC RGND XD01 XD00 XD02 XD03 XD04...

  • Page 65: J8, Eei Control Connector

    3.75 pc 10.25 pc 11.25 pc 38.25 pc 34.5 pc 4.333 pc Figure 5.9 shows the EEI control connector, connector pins, and signal names. Figure 5.9 J8, EEI Control Connector RGND Reserved Reserved +3.3 VDC +3.3 VDC Reserved RGND Reserved XRDY XHOLD XINT0...
  • Page 66 3.75 pc 10.25 pc 11.25 pc 38.25 pc 34.5 pc 4.333 pc 44.25 pc 48.583 p 5-12 Board Layout and Jumper Settings 52.5 pc...

  • Page 67: Schematics

    12.938 p 13.851 p This appendix contains the schematics for the EB402 (Revision 2 PCB) and the BD-EBM-CODEC-1 module. These drawings are also viewable on the CD-ROM that is included with the EB402 package in portable document format (PDF). • Figure A.1,...

  • Page 68: A.1 Eb402 Schematics (Sheet 1 Of 6)

    1.5 pc 5.4 pc 49.65 pc Figure A.1 EB402 Schematics (Sheet 1 of 6) 3.75 pc 44.25 pc 44.25 pc 34.5 pc 38.25 pc...

  • Page 69: A.2 Eb402 Schematics (Sheet 2 Of 6)

    3.75 pc 1.5 pc 5.4 pc 49.65 pc Figure A.2 EB402 Schematics (Sheet 2 of 6) 44.25 pc 44.25 pc 34.5 pc 38.25 pc...

  • Page 70: A.3 Eb402 Schematics (Sheet 3 Of 6)

    1.5 pc 5.4 pc 49.65 pc Figure A.3 EB402 Schematics (Sheet 3 of 6) 3.75 pc 44.25 pc 44.25 pc 34.5 pc 38.25 pc...

  • Page 71: A.4 Eb402 Schematics (Sheet 4 Of 6)

    3.75 pc 1.5 pc 5.4 pc 49.65 pc Figure A.4 EB402 Schematics (Sheet 4 of 6) 44.25 pc 44.25 pc 34.5 pc 38.25 pc...

  • Page 72: A.5 Eb402 Schematics (Sheet 5 Of 6)

    1.5 pc 5.4 pc 49.65 pc Figure A.5 EB402 Schematics (Sheet 5 of 6) 3.75 pc 44.25 pc 44.25 pc 34.5 pc 38.25 pc...

  • Page 73: A.6 Eb402 Schematics (Sheet 6 Of 6)

    3.75 pc 1.5 pc 5.4 pc 49.65 pc Figure A.6 EB402 Schematics (Sheet 6 of 6) 44.25 pc 44.25 pc 34.5 pc 38.25 pc...

  • Page 74: A.7 Bd-Ebm-Codec-1 Schematic Sheet 1 Of 1

    1.5 pc 5.4 pc 49.65 pc Figure A.7 BD-EBM-CODEC-1 Schematic Sheet 1 of 1 3.75 pc 44.25 pc 44.25 pc 34.5 pc 38.25 pc...

  • Page 75: B.1 Eb402 Bill Of Materials

    Appendix B Bill of Materials 12 pc 12.938 p 13.851 p Appendix B provides the bills of materials for the EB402 and the BD-EBM-CODEC-1 codec module. The EB402 (Revision 2 PCB) bill of materials is listed in Table B.1. Table B.1...
  • Page 76 3.75 pc 10.25 pc 11.25 pc 38.25 pc 34.5 pc 4.333 pc Table B.1 EB402 Bill of Materials (Cont.) Item Quantity Reference Part Description Source SE2818CT-ND 10 MHz Crystal Epson Oscillator Electronics America, Inc. SE2814CT-ND 7.372 MHz Epson Crystal Electronics Oscillator America, Inc.
  • Page 77 3.75 pc 10.25 pc 11.25 pc 38.25 pc 34.5 pc 4.333 pc Table B.1 EB402 Bill of Materials (Cont.) Item Quantity Reference Part Description Source R1, R2, R4 770-101-10k 10 kΩ Resistor Network 0.1 µF C10–C14, C16, C17, PCC1762CT-ND Panasonic...
  • Page 78 3.75 pc 10.25 pc 11.25 pc 38.25 pc 34.5 pc 4.333 pc Table B.1 EB402 Bill of Materials (Cont.) Item Quantity Reference Part Description Source 16PJ031 Power Jack Mouser 66506-076 34-Pin Berg Connector JP1, JP5–JP11, JP18, 69190-403 3-Pin Straight Berg...

  • Page 79: B.2 Bd-Ebm-Codec Bill Of Materials

    3.75 pc 10.25 pc 11.25 pc 38.25 pc 34.5 pc 4.333 pc Table B.2 BD-EBM-CODEC Bill of Materials Item Quantity Reference Part Description Source SN74LV74 Dual D-Type Texas Flip-Flop Instruments U2, U3 AD73322AR Dual Analog Analog Devices Front End SG-8002JC16.384M- 16.384 MHz Epson Oscillator...
  • Page 80 3.75 pc 10.25 pc 11.25 pc 38.25 pc 34.5 pc 4.333 pc 44.25 pc 48.583 p Bill of Materials 52.5 pc...
  • Page 81 Customer Feedback We would appreciate your feedback on this document. Please copy the following page, add your comments, and fax it to us at the number shown. If appropriate, please also fax copies of any marked-up pages from this document. Important: Please include your name, phone number, fax number, and company address so that we may contact you directly for...
  • Page 82 Fax your comments to: LSI Logic Corporation Technical Publications M/S E-198 Fax: 408.433.4333 Please tell us how you rate this document: EB402 Evaluation Board User’s Guide. Place a check mark in the appropriate blank for each category. Excellent Good Average Fair...
  • Page 83 You can find a current list of our U.S. distributors, international distributors, and sales offices and design resource centers on our web site at http://www.lsilogic.com/contacts/na_salesoffices.html...

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