Display Timing Configuration - Advantech Qseven SOM-3567 Manual

Note:
1. SOM-3567 is NC.

2.10.1.1 Display Timing Configuration

The graphic controller needs to be configured to match the timing parameters of the
attached flat panel display. To properly configure the controller, there needs to be some
method to determine the display parameters. Different Module vendors provide differing
ways to access display timing parameters. Some vendors store the data in non-volatile
memory with the BIOS setup screen as the method for entering the data, other vendors
might use a Module or Carrier based EEPROM. Some vendors might hard code the
information into the BIOS, and other vendors might support panel located timing via the
signals LVDS_I2C_CLK and LVDS_I2C_DAT with an EEPROM strapped to 1010 000x.
Regardless of the method used to store the panel timing parameters, the video BIOS will
need to have the ability to access and decode the parameters. Given the number of
variables it is recommended that Carrier designers contact Module suppliers to determine
the recommend method to store and retrieve the display timing parameters.
The Video Electronics Standards Association (VESA) recently released DisplayID, a
second generation display identification standard that can replace EDID and other
proprietary methods for storing flat panel timing data. DisplayID defines a data structure
which contains information such as display model, identification information, colorimetry,
feature support, and supported timings and formats. The DisplayID data allows the video
controller to be configured for optimal support for the attached display without user
intervention. The basic data structure is a variable length block up to 256 bytes with
additional 256 byte extensions as required. The DisplayID data is typically stored in a
serial EPROM connected to the LVDS_I2C bus. The EPROM can reside on the display or
Carrier. DisplayID is not backwards compatible with EDID. Contact VESA (www.vesa.org)
for more information.
Connect to SSC data of external clock chip
N/C if not used
６１
CMOS