NAD D5100 Service Manual page 10

PIC24FJ128GB106
MAIN BOARD
PSV & Table
Data Access
Control Block
Address Latch
Program Memory
Data Latch
OSCO/CLKO
OSCI/CLKI
Timing
Generation
FRC/LPRC
REFO
Oscillators
Precision
Band Gap
Reference
ENVREG
Voltage
Regulator
V /V
DDCORE CAP
Timer1 Timer2/3
PWM/OC
IC
( 3) ( 3)
1-9 1-9
Interrupt
Controller
8 16
PCH PCL
23
Program Counter
Stack Repeat
Control
Control
Logic Logic
23
Address Bus
24
Instruction
Decode &
Control
Control Signals
Power-up
Timer
Oscillator
Start-up Timer
Power-on
Reset
Watchdog
Timer
BOR and
( 2)
LVD
V , V
DD SS MCLR
( 3)
( 3)
RTCC
Timer4/5
SPI
( 1)
ICNs ( 3)
1/2/3
Data Bus
16
16
Data Latch
Data RAM
Address
Latch
16
Read AGU
Write AGU
EA MUX
16
Inst Latch
Inst Register
Divide
Support
16 x 16
W Reg Array
17x17
Multiplier
16-Bit ALU
10-Bit
( 3)
Comparators USB OTG
ADC
UART
I2C
CTMU
( 3)
1/2/3
1/2/3/4
10
( 1)
PORTA
(13 I/O)
PORTB
(16 I/O)
16
( 1)
PORTC
(8 I/O)
16
16
( 1)
PORTD
(16 I/O)
( 1)
PORTE
(10 I/O)
( 1)
PORTF
(9 I/O)
16
( 1)
PORTG
(12 I/O)
PMP/PSP