Related Manuals for SolidRun i.MX8M QuadLite
Summary of Contents for SolidRun i.MX8M QuadLite
- Page 1 SOM i.MX 8M User Manual NXP i.MX 8M™ based SOM | Rev. 1.0 EMBEDDED EDGE COMPUTING SolidRun Ltd. www.solid-run.com 7 Hamada st. | Yokne'am Illit 2069201 | Israel...
- Page 2 To the extent permitted by law no liability (including liability to any person by reason of negligence) will be accepted by SolidRun Ltd., its subsidiaries or employees for any direct or indirect loss or damage caused by omissions from or inaccuracies in this document. SolidRun Ltd. reserves the right to change details in this publication without prior notice.
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Page 3: Table Of Contents
Table of Content Introduction ................................ 4 Overview ................................4 Highlighted Features ............................4 Supporting Products ............................5 Description ................................. 5 Block Diagram ..............................5 Feature Summary ............................6 Core System Components ..........................7 i.MX8 SoC Family ............................7 Memory ................................8 10/100/1000 MBPS ETHERNET PHY ...................... -
Page 4: Introduction
• Quad lite core ARM A53 (1.5GHz) of the i.MX8M SoC. • Quad core ARM A53 (1.5GHz) of the i.MX8M SoC. Overview The SolidRun’s SOM i.MX8M is a high-performance system on module (SOM) based on the highly integrated NXP i.MX8M family of products. Highlighted Features •... -
Page 5: Supporting Products
Supporting Products The following products are provided from SolidRun both as production level platforms and as reference examples on how to incorporate the SOM in different levels of integration: • HummingBoard Pulse– A board computer that incorporates the SOM retains the same Android and different Linux distributions while adding extra hardware functionalities and access to the hardware. -
Page 6: Feature Summary
Feature Summary Following is the features summary of the SOM. Notice that some of the features are pinout multiplexed (please refer to the pin mux table below and the NXP i.MX8M data sheets): • NXP i.MX8M series SoC (Dual/Quad Lite/Quad ARM® Cortex™ A53 Processor, up to 1.5 GHz) •... -
Page 7: Core System Components
Core System Components i.MX8 SoC Family The i.MX8M Dual / 8M QuadLite / 8M Quad processors feature advanced implementation of a quad Arm® Cortex®-A53 core, which operates at speeds of up to 1.5 GHz. A general- purpose Cortex®-M4 core processor is for low-power processing. The following figure describes the i.MX8 SoC’s main features (For more details refer to NXP’s i.MX8 datasheet). -
Page 8: Memory
Memory The IMX-8 SOM support varieties of memory interfaces for booting and data storage. The following figure describes the IMX-8 SOM memory interfaces. Carrier 32 Bits LPDDR4 USB2/3 ESPI2, SS0 QSPAI, SS0 IMX-8 QUAD SDIO1, 8 Bits eMMC SDIO2, 4 Bits QUAD-Light DUAL I2C1... - Page 9 Quad Serial NOR Flash (SOM) • Each channel can be configured as 1/2/4-bit operation. • Support both SDR mode and DDR mode • No reset • IMX-8 QSPIA/nSS0. • Can be used as BOOT NVM * EEPROM (SOM) • 1Kb EEPROM •...
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Page 10: 10/100/1000 Mbps Ethernet Phy
10/100/1000 MBPS ETHERNET PHY The Ethernet PHY is based on the Qualcomm / Atheros AR8031. The following figure describes the Giga Ethernet interface. IMX-8 RGMII REF_CLK PHY & P PS AR8031 MDC/MDIO • IMX-8 RGMII interface. • IEEE 802.3 Ethernet interface for 1000BASE-T, 100BASE-TX, and 10BASE-Te. •... -
Page 11: Mipi Csi-2 Camera Interface
WI-FI The WI-FI module is an M.2 1216 standard LGA module. The i.MX8 WI-FI module is Silex’s WCBN3507A which based on Qualcomm Atheros QCA6174A-5 chip. The WI-FI main features are: • Operate at ISM frequency Band (2.4/ 5 GHz) • IEEE Standards Support 802.11ac, 802.11a, 802.11b, 802.11g and 802.11n •... -
Page 12: I.mx8 Som External Interfaces
Availability (worldwide distribution channels) • Excellent signal integrity (supports 6Gbps) Please contact Hirose or SolidRun for reliability and test result data. • Mating height of between 1.5mm to 4.0mm (1.5mm to 3.0mm if using 70-pin Board- to- Board header). SR-SOM-MX6 headers are fixed, the final mating height is determined by carrier implementation. - Page 13 The PCIe main features are: • On board clock buffer sources all PCIe interfaces, on SOM and on Carrier. • The IMX-8 CLK2_P/N clock output feeds the PCIe clock buffer. • PCIe-1 can be used by the WI-FI module on the SOM or other module on the carrier. It is an assembly option.
- Page 14 Host Mode: SS/HS/FS/LS Device Mode: SS/HS/FS OTG: HS/FS/LS. • Power control signal are not part of the USB module, any available GPIO can be used. MIPI CSI The following figure describes the CSI interface. IMX-8 CSI_LANE CSI_LANE CSI_LANE CSI 1 CSI_LANE CSI_CL •...
- Page 15 • Host Version. • Scalable data lane support, 1 to 4 Data Lanes. (Optional bidirectional support on lane 0). • Support for all DSI data types and formats. • Virtual Channel support. • MIPI Alliance Specification for Display Serial Interface Version 1.1 compliant. Audio The i.MX8 SOM supports up to three Audio channels, SAI1, SAI2 and SAI3.
- Page 16 HDMI The i.MX8 supports the HDMI interface including the signal termination. The following figure describes the HDMI interface. The HDMI main features are: • On board pull-up termination to support HDMI levels. • HDMI HPD support 5V level, • HDMI DDC doesn’t support PU, need to support on carrier board. •...
- Page 17 UART The i.MX8 SOM can support up to 4 UART interfaces. The following figure describes the UART interfaces. RX, TX (TerminaL IMX-8 UART 1 RX, TX,CTS, RT UART 3 RX, T UART 2 Resistor 4 - RX, T RX, TX UART 4 Assembly 2 –...
- Page 18 eSPI The i.MX8 SOM supports an eSPI interface. The following figure describes the eSPI interface. IMX-8 nSS0, MOSI, MISO, CLK eSPI 2 • i.MX8’s eSPI channel 2. • Single chip select nSS0. • Master/Slave configurable. • Polarity and phase of the Chip Select (SS) and SPI Clock (SCLK) are configurable. Please Note: eSPI channel 1 is not available as default configuration.
- Page 19 • In Standard mode, I2C supports the data transfer rates up to 100 kbits/s. • In Fast mode, data transfer rates up to 400 kbits/s can be achieved. For more details check the i.MX8 datasheet. The uSD supports the following features: •...
- Page 20 Connector’s Signal Description J5001 Main GPIO PIN PWR Main GPIO PMIC_ON BOOT_MODE0 DSI_DN3 BOOT_MODE1 DSI_DP3 8 GND 10 GND DSI_CKP DSI_CKN DSI_DN0 DSI_DP0 16 GND DSI_DN2 DSI_DP2 PCIE1_REF_CLKP_CN PCIE1_REF_CLKN_CN 22 GND DSI_DN1 24 3V3 DSI_DP1 PCIE_nPME gpio3.IO[5] 26 3V3 PCIe_nWAKE gpio3.IO[12] 28 3V3 PWM1_OUT...
- Page 21 Main GPIO PIN PWR Main GPIO PCIE2_REF_CLKP_CN PCIE2_RXN PCIE2_REF_CLKN_CN PCIE2_RXP 6 GND 8 3V3 PCIE2_TXN SAI3_MCLK gpio5.IO[2] 10 3V3 PCIE2_TXP SAI3_RXC gpio4.IO[29] 12 3V3 SAI1_TXC gpio4.IO[11] gpio4.IO[31] 14 3V3 SAI3_TXFS SAI3_TXC gpio5.IO[0] gpio4.IO[28] 16 3V3 SAI3_RXFS SPDIF_TX gpio5.IO[3] 18 3V3 IR_CAP gpio1.IO[12] 20 3V3...
- Page 22 Main GPIO PIN PWR Main GPIO 2 GND MDI_TRXN3 MDI_TRXP3 USB1_TXP USB1_TXN 8 GND MDI_TRXN2 MDI_TRXP2 USB1_RXP USB1_RXN 14 GND MDI_TRXN1 MDI_TRXP1 USB1_DP USB1_DN 20 GND MDI_TRXN0 MDI_TRXP0 USB2_DP USB2_DN 26 GND LED_10_100_LED_1000 28 3V3 LED_ACT USB_H1_PWR_EN gpio3.IO[4] 30 3V3 USB_OTG_PWR_EN gpio3.IO[2] gpio5.IO[18]...
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Page 23: Power And Reset
Power and Reset The i.MX8 power is a single 5V source. It uses NXP’s PMIC and discreet power converter to source all the i.MX8 power rails. The following figure describes the i.MX8 power architecture. 3.3V NVCC_SNVS_3V3 DCDC BUCK 3.38V/4A SNVS_3V3 0.9V/0.3A 0.9V PMIC_ON... -
Page 24: Mx8 Som Integration Manual
i.MX8 SOM Integration Manual Power up sequence The IMX-8 is source by a single 5V input. Al power sequences are supported by the SOM. When using the SOM 3.3V output there is no need to consider its power sequence. If an external power source is used, it needs to be power according to the power sequence rules. - Page 25 The booting signals are SAI1RXD[0..7] and SAI1TXD[0..7]. The following table describes the booting signals and its status during and after POR. The following table describes how the booting signals need to be set to support the different booting options. Notes: •...
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Page 26: I2C Interfaces
I2C Interfaces The i.MX8 SOM uses I2C1 interface for its internal configurations. The following table describes the address mapping. Ref. Chip I2C Port Address A Port Address B Description PMIC IMX8 PMIC EEPROM EEPROM GPIO Interfaces The i.MX8 SOM uses some GPIO signals for it internal controls. The following table describes the GPIO allocation. -
Page 27: I.mx8 Typical Power Consumption
software infrastructure used in CuBox-Pulse and HummingBoard Pulse uses those two signals for debugging. JTAG interface is on the IMX-8 SOM and is exposed as test pins on component side. Following is a snapshot of the test points and its connectivity traces: TP-4 ->... -
Page 28: Mx8 Som Mechanical Description
1.5mm is dedicated to the SOM i.MX8 print side components and the remaining 2mm for the carrier components underneath the SOM i.MX8. Refer to SolidRun HummingBoard and CuBox Pulse design and layout, where there are examples of the main and second 80 pin header board-to- board usage. -
Page 29: Ordering Information
Ordering Information Please refer to the SolidRun website for more information regarding part numbers and the procedure for placing an order. http://www.solid-run.com...
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